ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_rsip_regs_offsets.h
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1
25
26#pragma once
27
28#include <stddef.h>
29#include <stdint.h>
30
42typedef enum : uintptr_t {
43 k_ra8_rsip_base_addr = 0x403B0000UL,
44} ra8_rsip_addr_t;
45
58typedef enum : uint16_t {
59 /* ---- Control / status mailbox (sub-block @ 0x0000) ------------------- */
60 k_ra8_rsip_off_ctrl = 0x0000U,
61 k_ra8_rsip_off_status = 0x0004U,
62 k_ra8_rsip_off_ier = 0x0008U,
63 k_ra8_rsip_off_isr = 0x000CU,
64 k_ra8_rsip_off_bist = 0x0010U,
65
66 /* ---- Tamper / SPA-DPA control (HUM Ch 52.3.3 p 3307) ----------------- */
67 k_ra8_rsip_off_tamper_ctrl = 0x0014U,
68 k_ra8_rsip_off_tamper_status = 0x0018U,
69 k_ra8_rsip_off_dpa_ctrl = 0x001CU,
70
71 /* ---- DOTF key delivery routing (modelled mailbox; no HUM reg map) ---- */
72 k_ra8_rsip_off_dotf0_ctrl = 0x0030U,
73 k_ra8_rsip_off_dotf1_ctrl = 0x0034U,
74
75 /* ---- OEM boot loader version (modelled mailbox; no HUM reg map) ------ */
76 k_ra8_rsip_off_oem_bl_ver = 0x0050U,
77 k_ra8_rsip_off_oem_bl_inc = 0x0054U,
78 k_ra8_rsip_off_oem_bl_lock = 0x0058U,
79
80 /* ---- Hardware Unique Key + Unique ID gates --------------------------- */
81 k_ra8_rsip_off_huk_ctrl = 0x0070U,
82 k_ra8_rsip_off_uid_ctrl = 0x0074U,
83
84 /* ---- Key Derivation Function mailbox --------------------------------- */
85 k_ra8_rsip_off_kdf_ctrl = 0x0090U,
86 k_ra8_rsip_off_kdf_status = 0x0094U,
87 k_ra8_rsip_off_kdf_label = 0x0098U,
88 k_ra8_rsip_off_kdf_out = 0x009CU,
89
90 /* ---- Device lifecycle (HUM Ch 51.1 p 3263 "Device lifecycle") -------- */
91 k_ra8_rsip_off_life_state = 0x00C0U,
92 k_ra8_rsip_off_debug_level = 0x00C4U,
93
94 /* ---- Generic command mailbox + arg window ---------------------------- */
95 k_ra8_rsip_off_mbox_op = 0x0100U,
96 k_ra8_rsip_off_mbox_arg0 = 0x0104U,
97 k_ra8_rsip_off_mbox_arg1 = 0x0108U,
98 k_ra8_rsip_off_mbox_arg2 = 0x010CU,
99 k_ra8_rsip_off_mbox_arg3 = 0x0110U,
100 k_ra8_rsip_off_mbox_ret = 0x0140U,
101
102 /* ---- Data window (encrypt/decrypt input + output) ------------------- */
103 k_ra8_rsip_off_data_in0 = 0x1400U,
104 k_ra8_rsip_off_data_in1 = 0x1404U,
105 k_ra8_rsip_off_data_in2 = 0x1408U,
106 k_ra8_rsip_off_data_in3 = 0x140CU,
107 k_ra8_rsip_off_data_out0 = 0x1410U,
108 k_ra8_rsip_off_data_out1 = 0x1414U,
109 k_ra8_rsip_off_data_out2 = 0x1418U,
110 k_ra8_rsip_off_data_out3 = 0x141CU,
111
112 /* ---- Wrapped-key staging port + status ------------------------------- */
113 k_ra8_rsip_off_key_stage = 0x1420U,
114 k_ra8_rsip_off_key_op_status = 0x1424U,
119
120 /* ---- Random number generator ----------------------------------------- */
121 k_ra8_rsip_off_rnd_ctrl = 0x1440U,
122 k_ra8_rsip_off_rnd_status = 0x1444U,
123 k_ra8_rsip_off_rnd_data = 0x1458U,
124
125 /* ---- Hash engine ----------------------------------------------------- */
126 k_ra8_rsip_off_hash_ctrl = 0x1600U,
127 k_ra8_rsip_off_hash_status = 0x1604U,
128 k_ra8_rsip_off_hash_data_in = 0x1608U,
129 k_ra8_rsip_off_hash_digest = 0x1610U,
130 k_ra8_rsip_off_hash_hmac = 0x1660U,
131
132 /* ---- Asymmetric (RSA / ECC) scratch + control ------------------------ */
133 k_ra8_rsip_off_asym_ctrl = 0x1700U,
134 k_ra8_rsip_off_asym_status = 0x1704U,
135 k_ra8_rsip_off_asym_curve = 0x1708U,
136 k_ra8_rsip_off_asym_arg = 0x170CU,
137 k_ra8_rsip_off_asym_key = 0x1710U,
138 k_ra8_rsip_off_asym_msg_in = 0x1714U,
139 k_ra8_rsip_off_asym_sig_in = 0x1718U,
140 k_ra8_rsip_off_asym_sig_out = 0x171CU,
141 k_ra8_rsip_off_asym_pub_x = 0x1720U,
142 k_ra8_rsip_off_asym_pub_y = 0x1724U,
143 k_ra8_rsip_off_asym_shared = 0x1728U,
144 k_ra8_rsip_off_asym_rsa_size = 0x172CU,
145
146 /* ---- Wrapped-key vault read/write window ----------------------------- */
147 k_ra8_rsip_off_kv_ctrl = 0x1800U,
148 k_ra8_rsip_off_kv_slot = 0x1804U,
149 k_ra8_rsip_off_kv_data = 0x1808U,
150 k_ra8_rsip_off_kv_count = 0x180CU,
151
152 /* ---- Key-wrap / key-unwrap engine ------------------------------------ */
153 k_ra8_rsip_off_kw_ctrl = 0x1900U,
154 k_ra8_rsip_off_kw_kek = 0x1904U,
155 k_ra8_rsip_off_kw_iv0 = 0x1908U,
156 k_ra8_rsip_off_kw_iv1 = 0x190CU,
157 k_ra8_rsip_off_kw_iv2 = 0x1910U,
158 k_ra8_rsip_off_kw_iv3 = 0x1914U,
159 k_ra8_rsip_off_kw_handle = 0x1918U,
160 k_ra8_rsip_off_kw_blob_in = 0x191CU,
161 k_ra8_rsip_off_kw_blob_out = 0x1920U,
162
163 /* ---- Symmetric (AES + ChaCha20) cipher control + state --------------- */
164 k_ra8_rsip_off_sym_ctrl = 0x1500U,
165 k_ra8_rsip_off_sym_status = 0x1504U,
166 k_ra8_rsip_off_sym_keyh = 0x1508U,
167 k_ra8_rsip_off_sym_iv0 = 0x150CU,
168 k_ra8_rsip_off_sym_iv1 = 0x1510U,
169 k_ra8_rsip_off_sym_iv2 = 0x1514U,
170 k_ra8_rsip_off_sym_iv3 = 0x1518U,
171 k_ra8_rsip_off_sym_aad_in = 0x151CU,
172 k_ra8_rsip_off_sym_tag = 0x1520U,
173 k_ra8_rsip_off_sym_aad_len = 0x1524U,
174 k_ra8_rsip_off_sym_pt_len = 0x1528U,
175
176 /* ---- KDF additional context lanes ------------------------------------ */
177 k_ra8_rsip_off_kdf_info = 0x00A0U,
178 k_ra8_rsip_off_kdf_salt = 0x00A4U,
179 k_ra8_rsip_off_kdf_len = 0x00A8U,
180 k_ra8_rsip_off_kdf_ikm = 0x00ACU,
181
182 /* ---- OEM-key install primitives (FSP r_rsip_pe5*.c / r_rsip_pe6.c) -- */
183 k_ra8_rsip_off_oem_ctrl = 0x1A00U,
184 k_ra8_rsip_off_oem_arg = 0x1A04U,
185 k_ra8_rsip_off_oem_iv = 0x1A08U,
186
187 /* ---- Command FIFO (opcode + key handle, FSP r_rsip_p47i.c et al) ---- */
188 k_ra8_rsip_off_cmd_fifo = 0x1B00U,
189} ra8_rsip_off_t;
190
231
232/* -------------------------------------------------------------------------- *
233 * Layout insurance for ra8_rsip_off_t.
234 *
235 * Two-line policy for every register the HAL touches:
236 *
237 * 1. Pin the exact byte offset (catches accidental edits and rebases).
238 * 2. Verify the offset is 4-byte aligned and lands inside the
239 * documented sub-block window (catches typos that would alias
240 * onto an unrelated sub-block -- the bug pattern that put
241 * ``key_op_status`` on top of the TRNG status word).
242 *
243 * Cross-references:
244 * * File-header table at top of this file (sub-block layout).
245 * * FSP ``RSIP_PRV_ADDR_VAL_*`` anchors in
246 * ``crypto_procedures_protected/.../common/primitive/r_rsip_reg.h``.
247 * * HUM Ch 52 "Renesas Secure IP (RSIP-E50D)" p 3302-3307 (no
248 * register table -- mailbox model).
249 * -------------------------------------------------------------------------- */
250
251/* Every register cell is a 32-bit word. */
253#define RA8_RSIP_ASSERT_ALIGN(off_) \
254 static_assert(((size_t)(off_) & 0x3U) == 0U, #off_ " must be 4-byte aligned")
255
256/* Range check: low <= off <= high. */
258#define RA8_RSIP_ASSERT_IN_WIN(off_, lo_, hi_) \
259 static_assert((size_t)(off_) >= (size_t)(lo_) && (size_t)(off_) <= (size_t)(hi_), \
260 #off_ " outside window [" #lo_ ", " #hi_ "]")
261
262/* The pinning asserts below cross-check each named offset against the
263 * exact byte value already declared in the enum above. The hex literal
264 * IS the value being pinned, so the magic-number lint is suppressed
265 * for the assert wall. */
266/* NOLINTBEGIN(readability-magic-numbers) -- the assert wall pins each declared offset to its literal value. */
267/* ---- CTRL / status mailbox sub-block ------------------------------------- */
268static_assert((size_t)k_ra8_rsip_off_ctrl == 0x0000U, "CTRL offset");
269static_assert((size_t)k_ra8_rsip_off_status == 0x0004U, "STATUS offset");
270static_assert((size_t)k_ra8_rsip_off_ier == 0x0008U, "IER offset");
271static_assert((size_t)k_ra8_rsip_off_isr == 0x000CU, "ISR offset");
272static_assert((size_t)k_ra8_rsip_off_bist == 0x0010U, "BIST offset");
273static_assert((size_t)k_ra8_rsip_off_tamper_ctrl == 0x0014U, "TAMPER_CTRL offset");
274static_assert((size_t)k_ra8_rsip_off_tamper_status == 0x0018U, "TAMPER_STATUS offset");
275static_assert((size_t)k_ra8_rsip_off_dpa_ctrl == 0x001CU, "DPA_CTRL offset");
276static_assert((size_t)k_ra8_rsip_off_dotf0_ctrl == 0x0030U, "DOTF0_CTRL offset");
277static_assert((size_t)k_ra8_rsip_off_dotf1_ctrl == 0x0034U, "DOTF1_CTRL offset");
278static_assert((size_t)k_ra8_rsip_off_oem_bl_ver == 0x0050U, "OEM_BL_VER offset");
279static_assert((size_t)k_ra8_rsip_off_oem_bl_inc == 0x0054U, "OEM_BL_INC offset");
280static_assert((size_t)k_ra8_rsip_off_oem_bl_lock == 0x0058U, "OEM_BL_LOCK offset");
281static_assert((size_t)k_ra8_rsip_off_huk_ctrl == 0x0070U, "HUK_CTRL offset");
282static_assert((size_t)k_ra8_rsip_off_uid_ctrl == 0x0074U, "UID_CTRL offset");
283static_assert((size_t)k_ra8_rsip_off_kdf_ctrl == 0x0090U, "KDF_CTRL offset");
284static_assert((size_t)k_ra8_rsip_off_kdf_status == 0x0094U, "KDF_STATUS offset");
285static_assert((size_t)k_ra8_rsip_off_kdf_label == 0x0098U, "KDF_LABEL offset");
286static_assert((size_t)k_ra8_rsip_off_kdf_out == 0x009CU, "KDF_OUT offset");
287static_assert((size_t)k_ra8_rsip_off_kdf_info == 0x00A0U, "KDF_INFO offset");
288static_assert((size_t)k_ra8_rsip_off_kdf_salt == 0x00A4U, "KDF_SALT offset");
289static_assert((size_t)k_ra8_rsip_off_kdf_len == 0x00A8U, "KDF_LEN offset");
290static_assert((size_t)k_ra8_rsip_off_kdf_ikm == 0x00ACU, "KDF_IKM offset");
291static_assert((size_t)k_ra8_rsip_off_life_state == 0x00C0U, "LIFE_STATE offset");
292static_assert((size_t)k_ra8_rsip_off_debug_level == 0x00C4U, "DEBUG_LEVEL offset");
293
294/* ---- Generic command mailbox sub-block ---------------------------------- */
295static_assert((size_t)k_ra8_rsip_off_mbox_op == 0x0100U, "MBOX_OP offset");
296static_assert((size_t)k_ra8_rsip_off_mbox_arg0 == 0x0104U, "MBOX_ARG0 offset");
297static_assert((size_t)k_ra8_rsip_off_mbox_arg1 == 0x0108U, "MBOX_ARG1 offset");
298static_assert((size_t)k_ra8_rsip_off_mbox_arg2 == 0x010CU, "MBOX_ARG2 offset");
299static_assert((size_t)k_ra8_rsip_off_mbox_arg3 == 0x0110U, "MBOX_ARG3 offset");
300static_assert((size_t)k_ra8_rsip_off_mbox_ret == 0x0140U, "MBOX_RET offset");
301
302/* ---- Data + KEY_STAGE window @ 0x1400 ----------------------------------- */
303static_assert((size_t)k_ra8_rsip_off_data_in0 == 0x1400U, "DATA_IN0 offset");
304static_assert((size_t)k_ra8_rsip_off_data_in1 == 0x1404U, "DATA_IN1 offset");
305static_assert((size_t)k_ra8_rsip_off_data_in2 == 0x1408U, "DATA_IN2 offset");
306static_assert((size_t)k_ra8_rsip_off_data_in3 == 0x140CU, "DATA_IN3 offset");
307static_assert((size_t)k_ra8_rsip_off_data_out0 == 0x1410U, "DATA_OUT0 offset");
308static_assert((size_t)k_ra8_rsip_off_data_out1 == 0x1414U, "DATA_OUT1 offset");
309static_assert((size_t)k_ra8_rsip_off_data_out2 == 0x1418U, "DATA_OUT2 offset");
310static_assert((size_t)k_ra8_rsip_off_data_out3 == 0x141CU, "DATA_OUT3 offset");
311static_assert((size_t)k_ra8_rsip_off_key_stage == 0x1420U, "KEY_STAGE offset");
312static_assert((size_t)k_ra8_rsip_off_key_op_status == 0x1424U,
313 "KEY_OP_STATUS offset (must NOT collide with TRNG status @ 0x1444)");
314
315/* ---- TRNG sub-block @ 0x1440 -------------------------------------------- */
316static_assert((size_t)k_ra8_rsip_off_rnd_ctrl == 0x1440U, "RND_CTRL offset");
317static_assert((size_t)k_ra8_rsip_off_rnd_status == 0x1444U, "RND_STATUS offset");
318static_assert((size_t)k_ra8_rsip_off_rnd_data == 0x1458U, "RND_DATA offset");
319
320/* The KEY_STAGE-vs-TRNG collision is the high-stakes bug this audit
321 * prevents from coming back: ``KEY_OP_STATUS`` and ``RND_STATUS``
322 * must live in different sub-blocks so a wrapped-key load cannot be
323 * acknowledged by reading TRNG health flags. */
324static_assert((size_t)k_ra8_rsip_off_key_op_status != (size_t)k_ra8_rsip_off_rnd_status,
325 "KEY_OP_STATUS and RND_STATUS must not overlap");
326
327/* ---- Symmetric cipher sub-block @ 0x1500 -------------------------------- */
328static_assert((size_t)k_ra8_rsip_off_sym_ctrl == 0x1500U, "SYM_CTRL offset");
329static_assert((size_t)k_ra8_rsip_off_sym_status == 0x1504U, "SYM_STATUS offset");
330static_assert((size_t)k_ra8_rsip_off_sym_keyh == 0x1508U, "SYM_KEYH offset");
331static_assert((size_t)k_ra8_rsip_off_sym_iv0 == 0x150CU, "SYM_IV0 offset");
332static_assert((size_t)k_ra8_rsip_off_sym_iv1 == 0x1510U, "SYM_IV1 offset");
333static_assert((size_t)k_ra8_rsip_off_sym_iv2 == 0x1514U, "SYM_IV2 offset");
334static_assert((size_t)k_ra8_rsip_off_sym_iv3 == 0x1518U, "SYM_IV3 offset");
335static_assert((size_t)k_ra8_rsip_off_sym_aad_in == 0x151CU, "SYM_AAD_IN offset");
336static_assert((size_t)k_ra8_rsip_off_sym_tag == 0x1520U, "SYM_TAG offset");
337static_assert((size_t)k_ra8_rsip_off_sym_aad_len == 0x1524U, "SYM_AAD_LEN offset");
338static_assert((size_t)k_ra8_rsip_off_sym_pt_len == 0x1528U, "SYM_PT_LEN offset");
339
340/* ---- HASH sub-block @ 0x1600 -------------------------------------------- */
341static_assert((size_t)k_ra8_rsip_off_hash_ctrl == 0x1600U, "HASH_CTRL offset");
342static_assert((size_t)k_ra8_rsip_off_hash_status == 0x1604U, "HASH_STATUS offset");
343static_assert((size_t)k_ra8_rsip_off_hash_data_in == 0x1608U, "HASH_DATA_IN offset");
344static_assert((size_t)k_ra8_rsip_off_hash_digest == 0x1610U, "HASH_DIGEST offset");
345static_assert((size_t)k_ra8_rsip_off_hash_hmac == 0x1660U, "HASH_HMAC offset");
346
347/* ---- Asymmetric (RSA / ECC) sub-block @ 0x1700 -------------------------- */
348static_assert((size_t)k_ra8_rsip_off_asym_ctrl == 0x1700U, "ASYM_CTRL offset");
349static_assert((size_t)k_ra8_rsip_off_asym_status == 0x1704U, "ASYM_STATUS offset");
350static_assert((size_t)k_ra8_rsip_off_asym_curve == 0x1708U, "ASYM_CURVE offset");
351static_assert((size_t)k_ra8_rsip_off_asym_arg == 0x170CU, "ASYM_ARG offset");
352static_assert((size_t)k_ra8_rsip_off_asym_key == 0x1710U, "ASYM_KEY offset");
353static_assert((size_t)k_ra8_rsip_off_asym_msg_in == 0x1714U, "ASYM_MSG_IN offset");
354static_assert((size_t)k_ra8_rsip_off_asym_sig_in == 0x1718U, "ASYM_SIG_IN offset");
355static_assert((size_t)k_ra8_rsip_off_asym_sig_out == 0x171CU, "ASYM_SIG_OUT offset");
356static_assert((size_t)k_ra8_rsip_off_asym_pub_x == 0x1720U, "ASYM_PUB_X offset");
357static_assert((size_t)k_ra8_rsip_off_asym_pub_y == 0x1724U, "ASYM_PUB_Y offset");
358static_assert((size_t)k_ra8_rsip_off_asym_shared == 0x1728U, "ASYM_SHARED offset");
359static_assert((size_t)k_ra8_rsip_off_asym_rsa_size == 0x172CU, "ASYM_RSA_SIZE offset");
360
361/* ---- Key-vault sub-block @ 0x1800 --------------------------------------- */
362static_assert((size_t)k_ra8_rsip_off_kv_ctrl == 0x1800U, "KV_CTRL offset");
363static_assert((size_t)k_ra8_rsip_off_kv_slot == 0x1804U, "KV_SLOT offset");
364static_assert((size_t)k_ra8_rsip_off_kv_data == 0x1808U, "KV_DATA offset");
365static_assert((size_t)k_ra8_rsip_off_kv_count == 0x180CU, "KV_COUNT offset");
366
367/* ---- Key-wrap sub-block @ 0x1900 ---------------------------------------- */
368static_assert((size_t)k_ra8_rsip_off_kw_ctrl == 0x1900U, "KW_CTRL offset");
369static_assert((size_t)k_ra8_rsip_off_kw_kek == 0x1904U, "KW_KEK offset");
370static_assert((size_t)k_ra8_rsip_off_kw_iv0 == 0x1908U, "KW_IV0 offset");
371static_assert((size_t)k_ra8_rsip_off_kw_iv1 == 0x190CU, "KW_IV1 offset");
372static_assert((size_t)k_ra8_rsip_off_kw_iv2 == 0x1910U, "KW_IV2 offset");
373static_assert((size_t)k_ra8_rsip_off_kw_iv3 == 0x1914U, "KW_IV3 offset");
374static_assert((size_t)k_ra8_rsip_off_kw_handle == 0x1918U, "KW_HANDLE offset");
375static_assert((size_t)k_ra8_rsip_off_kw_blob_in == 0x191CU, "KW_BLOB_IN offset");
376static_assert((size_t)k_ra8_rsip_off_kw_blob_out == 0x1920U, "KW_BLOB_OUT offset");
377
378/* ---- OEM-install sub-block @ 0x1A00 ------------------------------------- */
379static_assert((size_t)k_ra8_rsip_off_oem_ctrl == 0x1A00U, "OEM_CTRL offset");
380static_assert((size_t)k_ra8_rsip_off_oem_arg == 0x1A04U, "OEM_ARG offset");
381static_assert((size_t)k_ra8_rsip_off_oem_iv == 0x1A08U, "OEM_IV offset");
382
383/* ---- Command FIFO sub-block @ 0x1B00 ------------------------------------ */
384static_assert((size_t)k_ra8_rsip_off_cmd_fifo == 0x1B00U, "CMD_FIFO offset");
385
386/* ---- Alignment sweep: every register must be a 32-bit word boundary ----- */
387RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_ctrl);
388RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_status);
389RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_ier);
390RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_isr);
391RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_bist);
392RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_tamper_ctrl);
393RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_tamper_status);
394RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_dpa_ctrl);
395RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_dotf0_ctrl);
396RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_dotf1_ctrl);
397RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_oem_bl_ver);
398RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_oem_bl_inc);
399RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_oem_bl_lock);
400RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_huk_ctrl);
401RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_uid_ctrl);
402RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kdf_ctrl);
403RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kdf_status);
404RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kdf_label);
405RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kdf_out);
406RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kdf_info);
407RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kdf_salt);
408RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kdf_len);
409RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kdf_ikm);
410RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_life_state);
411RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_debug_level);
412RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_mbox_op);
413RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_mbox_arg0);
414RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_mbox_arg1);
415RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_mbox_arg2);
416RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_mbox_arg3);
417RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_mbox_ret);
418RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_data_in0);
419RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_data_in1);
420RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_data_in2);
421RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_data_in3);
422RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_data_out0);
423RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_data_out1);
424RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_data_out2);
425RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_data_out3);
426RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_key_stage);
427RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_key_op_status);
428RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_rnd_ctrl);
429RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_rnd_status);
430RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_rnd_data);
431RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_ctrl);
432RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_status);
433RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_keyh);
434RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_iv0);
435RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_iv1);
436RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_iv2);
437RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_iv3);
438RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_aad_in);
439RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_tag);
440RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_aad_len);
441RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_sym_pt_len);
442RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_hash_ctrl);
443RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_hash_status);
444RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_hash_data_in);
445RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_hash_digest);
446RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_hash_hmac);
447RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_ctrl);
448RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_status);
449RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_curve);
450RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_arg);
451RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_key);
452RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_msg_in);
453RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_sig_in);
454RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_sig_out);
455RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_pub_x);
456RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_pub_y);
457RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_shared);
458RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_asym_rsa_size);
459RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kv_ctrl);
460RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kv_slot);
461RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kv_data);
462RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kv_count);
463RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kw_ctrl);
464RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kw_kek);
465RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kw_iv0);
466RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kw_iv1);
467RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kw_iv2);
468RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kw_iv3);
469RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kw_handle);
470RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kw_blob_in);
471RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_kw_blob_out);
472RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_oem_ctrl);
473RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_oem_arg);
474RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_oem_iv);
475RA8_RSIP_ASSERT_ALIGN(k_ra8_rsip_off_cmd_fifo);
476
477/* ---- Sub-block containment sweep ---------------------------------------- */
478RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_ctrl, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
479RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_status, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
480RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_ier, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
481RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_isr, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
482RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_bist, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
483RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_tamper_ctrl, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
484RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_tamper_status,
485 k_ra8_rsip_win_ctrl_lo,
486 k_ra8_rsip_win_ctrl_hi);
487RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_dpa_ctrl, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
488RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_dotf0_ctrl, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
489RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_dotf1_ctrl, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
490RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_oem_bl_ver, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
491RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_oem_bl_inc, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
492RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_oem_bl_lock, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
493RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_huk_ctrl, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
494RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_uid_ctrl, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
495RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kdf_ctrl, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
496RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kdf_status, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
497RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kdf_label, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
498RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kdf_out, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
499RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kdf_info, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
500RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kdf_salt, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
501RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kdf_len, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
502RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kdf_ikm, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
503RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_life_state, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
504RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_debug_level, k_ra8_rsip_win_ctrl_lo, k_ra8_rsip_win_ctrl_hi);
505RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_mbox_op, k_ra8_rsip_win_mbox_lo, k_ra8_rsip_win_mbox_hi);
506RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_mbox_arg0, k_ra8_rsip_win_mbox_lo, k_ra8_rsip_win_mbox_hi);
507RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_mbox_arg1, k_ra8_rsip_win_mbox_lo, k_ra8_rsip_win_mbox_hi);
508RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_mbox_arg2, k_ra8_rsip_win_mbox_lo, k_ra8_rsip_win_mbox_hi);
509RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_mbox_arg3, k_ra8_rsip_win_mbox_lo, k_ra8_rsip_win_mbox_hi);
510RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_mbox_ret, k_ra8_rsip_win_mbox_lo, k_ra8_rsip_win_mbox_hi);
511RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_data_in0, k_ra8_rsip_win_data_lo, k_ra8_rsip_win_data_hi);
512RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_data_in1, k_ra8_rsip_win_data_lo, k_ra8_rsip_win_data_hi);
513RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_data_in2, k_ra8_rsip_win_data_lo, k_ra8_rsip_win_data_hi);
514RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_data_in3, k_ra8_rsip_win_data_lo, k_ra8_rsip_win_data_hi);
515RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_data_out0, k_ra8_rsip_win_data_lo, k_ra8_rsip_win_data_hi);
516RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_data_out1, k_ra8_rsip_win_data_lo, k_ra8_rsip_win_data_hi);
517RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_data_out2, k_ra8_rsip_win_data_lo, k_ra8_rsip_win_data_hi);
518RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_data_out3, k_ra8_rsip_win_data_lo, k_ra8_rsip_win_data_hi);
519RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_key_stage, k_ra8_rsip_win_data_lo, k_ra8_rsip_win_data_hi);
520RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_key_op_status,
521 k_ra8_rsip_win_data_lo,
522 k_ra8_rsip_win_data_hi);
523RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_rnd_ctrl, k_ra8_rsip_win_trng_lo, k_ra8_rsip_win_trng_hi);
524RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_rnd_status, k_ra8_rsip_win_trng_lo, k_ra8_rsip_win_trng_hi);
525RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_rnd_data, k_ra8_rsip_win_trng_lo, k_ra8_rsip_win_trng_hi);
526RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_ctrl, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
527RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_status, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
528RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_keyh, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
529RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_iv0, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
530RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_iv1, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
531RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_iv2, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
532RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_iv3, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
533RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_aad_in, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
534RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_tag, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
535RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_aad_len, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
536RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_sym_pt_len, k_ra8_rsip_win_sym_lo, k_ra8_rsip_win_sym_hi);
537RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_hash_ctrl, k_ra8_rsip_win_hash_lo, k_ra8_rsip_win_hash_hi);
538RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_hash_status, k_ra8_rsip_win_hash_lo, k_ra8_rsip_win_hash_hi);
539RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_hash_data_in, k_ra8_rsip_win_hash_lo, k_ra8_rsip_win_hash_hi);
540RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_hash_digest, k_ra8_rsip_win_hash_lo, k_ra8_rsip_win_hash_hi);
541RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_hash_hmac, k_ra8_rsip_win_hash_lo, k_ra8_rsip_win_hash_hi);
542RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_ctrl, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
543RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_status, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
544RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_curve, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
545RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_arg, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
546RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_key, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
547RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_msg_in, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
548RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_sig_in, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
549RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_sig_out, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
550RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_pub_x, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
551RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_pub_y, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
552RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_shared, k_ra8_rsip_win_asym_lo, k_ra8_rsip_win_asym_hi);
553RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_asym_rsa_size,
554 k_ra8_rsip_win_asym_lo,
555 k_ra8_rsip_win_asym_hi);
556RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kv_ctrl, k_ra8_rsip_win_kv_lo, k_ra8_rsip_win_kv_hi);
557RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kv_slot, k_ra8_rsip_win_kv_lo, k_ra8_rsip_win_kv_hi);
558RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kv_data, k_ra8_rsip_win_kv_lo, k_ra8_rsip_win_kv_hi);
559RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kv_count, k_ra8_rsip_win_kv_lo, k_ra8_rsip_win_kv_hi);
560RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kw_ctrl, k_ra8_rsip_win_kw_lo, k_ra8_rsip_win_kw_hi);
561RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kw_kek, k_ra8_rsip_win_kw_lo, k_ra8_rsip_win_kw_hi);
562RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kw_iv0, k_ra8_rsip_win_kw_lo, k_ra8_rsip_win_kw_hi);
563RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kw_iv1, k_ra8_rsip_win_kw_lo, k_ra8_rsip_win_kw_hi);
564RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kw_iv2, k_ra8_rsip_win_kw_lo, k_ra8_rsip_win_kw_hi);
565RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kw_iv3, k_ra8_rsip_win_kw_lo, k_ra8_rsip_win_kw_hi);
566RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kw_handle, k_ra8_rsip_win_kw_lo, k_ra8_rsip_win_kw_hi);
567RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kw_blob_in, k_ra8_rsip_win_kw_lo, k_ra8_rsip_win_kw_hi);
568RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_kw_blob_out, k_ra8_rsip_win_kw_lo, k_ra8_rsip_win_kw_hi);
569RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_oem_ctrl, k_ra8_rsip_win_oem_lo, k_ra8_rsip_win_oem_hi);
570RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_oem_arg, k_ra8_rsip_win_oem_lo, k_ra8_rsip_win_oem_hi);
571RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_oem_iv, k_ra8_rsip_win_oem_lo, k_ra8_rsip_win_oem_hi);
572RA8_RSIP_ASSERT_IN_WIN(k_ra8_rsip_off_cmd_fifo, k_ra8_rsip_win_cmd_lo, k_ra8_rsip_win_cmd_hi);
573/* NOLINTEND(readability-magic-numbers) */
ra8_rsip_addr_t
ra8_rsip_addr_t
Memory-mapped base address for the RSIP-E50D engine.
Definition ra8_rsip_regs_offsets.h:42
k_ra8_rsip_base_addr
@ k_ra8_rsip_base_addr
RSIP-E50D mailbox window base.
Definition ra8_rsip_regs_offsets.h:43
ra8_rsip_window_t
ra8_rsip_window_t
Sub-block boundary constants used by the layout asserts below.
Definition ra8_rsip_regs_offsets.h:207
k_ra8_rsip_win_cmd_hi
@ k_ra8_rsip_win_cmd_hi
Command FIFO window high.
Definition ra8_rsip_regs_offsets.h:229
k_ra8_rsip_win_data_lo
@ k_ra8_rsip_win_data_lo
Data + KEY_STAGE window low.
Definition ra8_rsip_regs_offsets.h:212
k_ra8_rsip_win_kw_hi
@ k_ra8_rsip_win_kw_hi
Key-wrap window high.
Definition ra8_rsip_regs_offsets.h:225
k_ra8_rsip_win_sym_hi
@ k_ra8_rsip_win_sym_hi
Symmetric cipher window high.
Definition ra8_rsip_regs_offsets.h:217
k_ra8_rsip_win_cmd_lo
@ k_ra8_rsip_win_cmd_lo
Command FIFO window low.
Definition ra8_rsip_regs_offsets.h:228
k_ra8_rsip_win_trng_lo
@ k_ra8_rsip_win_trng_lo
TRNG window low.
Definition ra8_rsip_regs_offsets.h:214
k_ra8_rsip_win_asym_hi
@ k_ra8_rsip_win_asym_hi
Asymmetric (RSA/ECC) window high.
Definition ra8_rsip_regs_offsets.h:221
k_ra8_rsip_win_asym_lo
@ k_ra8_rsip_win_asym_lo
Asymmetric (RSA/ECC) window low.
Definition ra8_rsip_regs_offsets.h:220
k_ra8_rsip_win_kw_lo
@ k_ra8_rsip_win_kw_lo
Key-wrap window low.
Definition ra8_rsip_regs_offsets.h:224
k_ra8_rsip_win_kv_lo
@ k_ra8_rsip_win_kv_lo
Key-vault window low.
Definition ra8_rsip_regs_offsets.h:222
k_ra8_rsip_win_ctrl_lo
@ k_ra8_rsip_win_ctrl_lo
CTRL/status mailbox low.
Definition ra8_rsip_regs_offsets.h:208
k_ra8_rsip_win_oem_lo
@ k_ra8_rsip_win_oem_lo
OEM-install window low.
Definition ra8_rsip_regs_offsets.h:226
k_ra8_rsip_win_mbox_lo
@ k_ra8_rsip_win_mbox_lo
Generic mailbox low.
Definition ra8_rsip_regs_offsets.h:210
k_ra8_rsip_win_hash_hi
@ k_ra8_rsip_win_hash_hi
HASH window high.
Definition ra8_rsip_regs_offsets.h:219
k_ra8_rsip_win_hash_lo
@ k_ra8_rsip_win_hash_lo
HASH window low.
Definition ra8_rsip_regs_offsets.h:218
k_ra8_rsip_win_kv_hi
@ k_ra8_rsip_win_kv_hi
Key-vault window high.
Definition ra8_rsip_regs_offsets.h:223
k_ra8_rsip_win_data_hi
@ k_ra8_rsip_win_data_hi
Data + KEY_STAGE window high.
Definition ra8_rsip_regs_offsets.h:213
k_ra8_rsip_win_oem_hi
@ k_ra8_rsip_win_oem_hi
OEM-install window high.
Definition ra8_rsip_regs_offsets.h:227
k_ra8_rsip_win_mbox_hi
@ k_ra8_rsip_win_mbox_hi
Generic mailbox high.
Definition ra8_rsip_regs_offsets.h:211
k_ra8_rsip_win_trng_hi
@ k_ra8_rsip_win_trng_hi
TRNG window high.
Definition ra8_rsip_regs_offsets.h:215
k_ra8_rsip_win_ctrl_hi
@ k_ra8_rsip_win_ctrl_hi
CTRL/status mailbox high.
Definition ra8_rsip_regs_offsets.h:209
k_ra8_rsip_win_sym_lo
@ k_ra8_rsip_win_sym_lo
Symmetric cipher window low.
Definition ra8_rsip_regs_offsets.h:216
ra8_rsip_off_t
ra8_rsip_off_t
Byte offsets of every register the HAL touches.
Definition ra8_rsip_regs_offsets.h:58
k_ra8_rsip_off_kdf_len
@ k_ra8_rsip_off_kdf_len
Output length (bytes).
Definition ra8_rsip_regs_offsets.h:179
k_ra8_rsip_off_mbox_arg2
@ k_ra8_rsip_off_mbox_arg2
Argument 2.
Definition ra8_rsip_regs_offsets.h:98
k_ra8_rsip_off_asym_sig_out
@ k_ra8_rsip_off_asym_sig_out
Signature output lane.
Definition ra8_rsip_regs_offsets.h:140
k_ra8_rsip_off_ctrl
@ k_ra8_rsip_off_ctrl
Engine control word.
Definition ra8_rsip_regs_offsets.h:60
k_ra8_rsip_off_asym_msg_in
@ k_ra8_rsip_off_asym_msg_in
Message / digest input port.
Definition ra8_rsip_regs_offsets.h:138
k_ra8_rsip_off_asym_curve
@ k_ra8_rsip_off_asym_curve
ECC curve selector.
Definition ra8_rsip_regs_offsets.h:135
k_ra8_rsip_off_kv_data
@ k_ra8_rsip_off_kv_data
Vault data port.
Definition ra8_rsip_regs_offsets.h:149
k_ra8_rsip_off_data_in3
@ k_ra8_rsip_off_data_in3
Data input lane 3.
Definition ra8_rsip_regs_offsets.h:106
k_ra8_rsip_off_kv_ctrl
@ k_ra8_rsip_off_kv_ctrl
Vault command (read/write/erase).
Definition ra8_rsip_regs_offsets.h:147
k_ra8_rsip_off_mbox_ret
@ k_ra8_rsip_off_mbox_ret
Completion code from engine.
Definition ra8_rsip_regs_offsets.h:100
k_ra8_rsip_off_data_out0
@ k_ra8_rsip_off_data_out0
Data output lane 0.
Definition ra8_rsip_regs_offsets.h:107
k_ra8_rsip_off_life_state
@ k_ra8_rsip_off_life_state
Current lifecycle state.
Definition ra8_rsip_regs_offsets.h:91
k_ra8_rsip_off_sym_ctrl
@ k_ra8_rsip_off_sym_ctrl
Cipher command (mode|dir|alg).
Definition ra8_rsip_regs_offsets.h:164
k_ra8_rsip_off_oem_iv
@ k_ra8_rsip_off_oem_iv
OEM install IV.
Definition ra8_rsip_regs_offsets.h:185
k_ra8_rsip_off_status
@ k_ra8_rsip_off_status
Status / state monitor.
Definition ra8_rsip_regs_offsets.h:61
k_ra8_rsip_off_kw_iv1
@ k_ra8_rsip_off_kw_iv1
Wrap IV lane 1.
Definition ra8_rsip_regs_offsets.h:156
k_ra8_rsip_off_bist
@ k_ra8_rsip_off_bist
Built-in self-test trigger / result.
Definition ra8_rsip_regs_offsets.h:64
k_ra8_rsip_off_kdf_out
@ k_ra8_rsip_off_kdf_out
Derived-key output handle.
Definition ra8_rsip_regs_offsets.h:88
k_ra8_rsip_off_asym_key
@ k_ra8_rsip_off_asym_key
Key-handle slot.
Definition ra8_rsip_regs_offsets.h:137
k_ra8_rsip_off_hash_digest
@ k_ra8_rsip_off_hash_digest
HASH output digest base.
Definition ra8_rsip_regs_offsets.h:129
k_ra8_rsip_off_kv_count
@ k_ra8_rsip_off_kv_count
Vault populated-slot count.
Definition ra8_rsip_regs_offsets.h:150
k_ra8_rsip_off_asym_shared
@ k_ra8_rsip_off_asym_shared
ECDH shared-secret handle.
Definition ra8_rsip_regs_offsets.h:143
k_ra8_rsip_off_uid_ctrl
@ k_ra8_rsip_off_uid_ctrl
Unique-ID access gate.
Definition ra8_rsip_regs_offsets.h:82
k_ra8_rsip_off_dotf0_ctrl
@ k_ra8_rsip_off_dotf0_ctrl
DOTF0 key route enable + slot.
Definition ra8_rsip_regs_offsets.h:72
k_ra8_rsip_off_isr
@ k_ra8_rsip_off_isr
Interrupt status (W1C).
Definition ra8_rsip_regs_offsets.h:63
k_ra8_rsip_off_asym_arg
@ k_ra8_rsip_off_asym_arg
Argument-block descriptor.
Definition ra8_rsip_regs_offsets.h:136
k_ra8_rsip_off_data_in0
@ k_ra8_rsip_off_data_in0
Data input lane 0.
Definition ra8_rsip_regs_offsets.h:103
k_ra8_rsip_off_sym_iv3
@ k_ra8_rsip_off_sym_iv3
IV / nonce lane 3.
Definition ra8_rsip_regs_offsets.h:170
k_ra8_rsip_off_rnd_ctrl
@ k_ra8_rsip_off_rnd_ctrl
TRNG control word.
Definition ra8_rsip_regs_offsets.h:121
k_ra8_rsip_off_kdf_ctrl
@ k_ra8_rsip_off_kdf_ctrl
KDF request word.
Definition ra8_rsip_regs_offsets.h:85
k_ra8_rsip_off_ier
@ k_ra8_rsip_off_ier
Interrupt enable.
Definition ra8_rsip_regs_offsets.h:62
k_ra8_rsip_off_sym_keyh
@ k_ra8_rsip_off_sym_keyh
Cipher key-handle slot.
Definition ra8_rsip_regs_offsets.h:166
k_ra8_rsip_off_rnd_data
@ k_ra8_rsip_off_rnd_data
TRNG output (32-bit per read).
Definition ra8_rsip_regs_offsets.h:123
k_ra8_rsip_off_hash_status
@ k_ra8_rsip_off_hash_status
HASH ready / done flags.
Definition ra8_rsip_regs_offsets.h:127
k_ra8_rsip_off_cmd_fifo
@ k_ra8_rsip_off_cmd_fifo
32-bit opcode descriptor write.
Definition ra8_rsip_regs_offsets.h:188
k_ra8_rsip_off_oem_bl_lock
@ k_ra8_rsip_off_oem_bl_lock
Lock-after-validation latch.
Definition ra8_rsip_regs_offsets.h:78
k_ra8_rsip_off_kw_iv3
@ k_ra8_rsip_off_kw_iv3
Wrap IV lane 3.
Definition ra8_rsip_regs_offsets.h:158
k_ra8_rsip_off_data_out3
@ k_ra8_rsip_off_data_out3
Data output lane 3.
Definition ra8_rsip_regs_offsets.h:110
k_ra8_rsip_off_rnd_status
@ k_ra8_rsip_off_rnd_status
TRNG ready / health flags.
Definition ra8_rsip_regs_offsets.h:122
k_ra8_rsip_off_kw_iv2
@ k_ra8_rsip_off_kw_iv2
Wrap IV lane 2.
Definition ra8_rsip_regs_offsets.h:157
k_ra8_rsip_off_sym_iv1
@ k_ra8_rsip_off_sym_iv1
IV / nonce lane 1.
Definition ra8_rsip_regs_offsets.h:168
k_ra8_rsip_off_oem_bl_ver
@ k_ra8_rsip_off_oem_bl_ver
Latched OEM BL Ver counter.
Definition ra8_rsip_regs_offsets.h:76
k_ra8_rsip_off_data_out1
@ k_ra8_rsip_off_data_out1
Data output lane 1.
Definition ra8_rsip_regs_offsets.h:108
k_ra8_rsip_off_hash_ctrl
@ k_ra8_rsip_off_hash_ctrl
HASH control (algorithm select).
Definition ra8_rsip_regs_offsets.h:126
k_ra8_rsip_off_asym_pub_x
@ k_ra8_rsip_off_asym_pub_x
ECC peer X / RSA pubkey lane.
Definition ra8_rsip_regs_offsets.h:141
k_ra8_rsip_off_tamper_status
@ k_ra8_rsip_off_tamper_status
Latched tamper-event flags.
Definition ra8_rsip_regs_offsets.h:68
k_ra8_rsip_off_tamper_ctrl
@ k_ra8_rsip_off_tamper_ctrl
Tamper-source enable mask.
Definition ra8_rsip_regs_offsets.h:67
k_ra8_rsip_off_data_in2
@ k_ra8_rsip_off_data_in2
Data input lane 2.
Definition ra8_rsip_regs_offsets.h:105
k_ra8_rsip_off_kw_iv0
@ k_ra8_rsip_off_kw_iv0
Wrap IV lane 0.
Definition ra8_rsip_regs_offsets.h:155
k_ra8_rsip_off_mbox_arg0
@ k_ra8_rsip_off_mbox_arg0
Argument 0.
Definition ra8_rsip_regs_offsets.h:96
k_ra8_rsip_off_hash_hmac
@ k_ra8_rsip_off_hash_hmac
HMAC mode + key-handle slot.
Definition ra8_rsip_regs_offsets.h:130
k_ra8_rsip_off_sym_tag
@ k_ra8_rsip_off_sym_tag
AEAD authentication tag.
Definition ra8_rsip_regs_offsets.h:172
k_ra8_rsip_off_dpa_ctrl
@ k_ra8_rsip_off_dpa_ctrl
SPA/DPA countermeasure arm.
Definition ra8_rsip_regs_offsets.h:69
k_ra8_rsip_off_mbox_op
@ k_ra8_rsip_off_mbox_op
Opcode written by host.
Definition ra8_rsip_regs_offsets.h:95
k_ra8_rsip_off_data_in1
@ k_ra8_rsip_off_data_in1
Data input lane 1.
Definition ra8_rsip_regs_offsets.h:104
k_ra8_rsip_off_asym_ctrl
@ k_ra8_rsip_off_asym_ctrl
Asymmetric command word.
Definition ra8_rsip_regs_offsets.h:133
k_ra8_rsip_off_kw_blob_out
@ k_ra8_rsip_off_kw_blob_out
Wrapped-blob output lane.
Definition ra8_rsip_regs_offsets.h:161
k_ra8_rsip_off_sym_aad_len
@ k_ra8_rsip_off_sym_aad_len
AEAD AAD length (bytes).
Definition ra8_rsip_regs_offsets.h:173
k_ra8_rsip_off_hash_data_in
@ k_ra8_rsip_off_hash_data_in
HASH input window (32-bit each).
Definition ra8_rsip_regs_offsets.h:128
k_ra8_rsip_off_kw_blob_in
@ k_ra8_rsip_off_kw_blob_in
Wrapped-blob input lane.
Definition ra8_rsip_regs_offsets.h:160
k_ra8_rsip_off_kv_slot
@ k_ra8_rsip_off_kv_slot
Vault slot index.
Definition ra8_rsip_regs_offsets.h:148
k_ra8_rsip_off_kdf_salt
@ k_ra8_rsip_off_kdf_salt
HKDF salt lane.
Definition ra8_rsip_regs_offsets.h:178
k_ra8_rsip_off_dotf1_ctrl
@ k_ra8_rsip_off_dotf1_ctrl
DOTF1 key route enable + slot.
Definition ra8_rsip_regs_offsets.h:73
k_ra8_rsip_off_debug_level
@ k_ra8_rsip_off_debug_level
AL0/AL1/AL2 debug level.
Definition ra8_rsip_regs_offsets.h:92
k_ra8_rsip_off_asym_status
@ k_ra8_rsip_off_asym_status
Asymmetric busy / done.
Definition ra8_rsip_regs_offsets.h:134
k_ra8_rsip_off_sym_status
@ k_ra8_rsip_off_sym_status
Cipher busy / done.
Definition ra8_rsip_regs_offsets.h:165
k_ra8_rsip_off_asym_sig_in
@ k_ra8_rsip_off_asym_sig_in
Signature input lane.
Definition ra8_rsip_regs_offsets.h:139
k_ra8_rsip_off_oem_arg
@ k_ra8_rsip_off_oem_arg
OEM install argument descriptor.
Definition ra8_rsip_regs_offsets.h:184
k_ra8_rsip_off_oem_ctrl
@ k_ra8_rsip_off_oem_ctrl
OEM install command word.
Definition ra8_rsip_regs_offsets.h:183
k_ra8_rsip_off_asym_rsa_size
@ k_ra8_rsip_off_asym_rsa_size
RSA modulus-size selector.
Definition ra8_rsip_regs_offsets.h:144
k_ra8_rsip_off_mbox_arg3
@ k_ra8_rsip_off_mbox_arg3
Argument 3.
Definition ra8_rsip_regs_offsets.h:99
k_ra8_rsip_off_kw_kek
@ k_ra8_rsip_off_kw_kek
KEK handle slot.
Definition ra8_rsip_regs_offsets.h:154
k_ra8_rsip_off_mbox_arg1
@ k_ra8_rsip_off_mbox_arg1
Argument 1.
Definition ra8_rsip_regs_offsets.h:97
k_ra8_rsip_off_key_op_status
@ k_ra8_rsip_off_key_op_status
Key/data op status (one 32-bit word past KEY_STAGE, inside the KEY_STAGE sub-block 0x1420-0x143F – th...
Definition ra8_rsip_regs_offsets.h:114
k_ra8_rsip_off_kdf_info
@ k_ra8_rsip_off_kdf_info
KDF info / context lane.
Definition ra8_rsip_regs_offsets.h:177
k_ra8_rsip_off_asym_pub_y
@ k_ra8_rsip_off_asym_pub_y
ECC peer Y lane.
Definition ra8_rsip_regs_offsets.h:142
k_ra8_rsip_off_key_stage
@ k_ra8_rsip_off_key_stage
Wrapped-key load port.
Definition ra8_rsip_regs_offsets.h:113
k_ra8_rsip_off_kw_ctrl
@ k_ra8_rsip_off_kw_ctrl
Key-wrap command word.
Definition ra8_rsip_regs_offsets.h:153
k_ra8_rsip_off_kdf_ikm
@ k_ra8_rsip_off_kdf_ikm
Input keying material handle.
Definition ra8_rsip_regs_offsets.h:180
k_ra8_rsip_off_sym_iv0
@ k_ra8_rsip_off_sym_iv0
IV / nonce lane 0.
Definition ra8_rsip_regs_offsets.h:167
k_ra8_rsip_off_data_out2
@ k_ra8_rsip_off_data_out2
Data output lane 2.
Definition ra8_rsip_regs_offsets.h:109
k_ra8_rsip_off_kw_handle
@ k_ra8_rsip_off_kw_handle
Source / destination handle slot.
Definition ra8_rsip_regs_offsets.h:159
k_ra8_rsip_off_huk_ctrl
@ k_ra8_rsip_off_huk_ctrl
HUK access gate (read-only data).
Definition ra8_rsip_regs_offsets.h:81
k_ra8_rsip_off_kdf_status
@ k_ra8_rsip_off_kdf_status
KDF complete / busy.
Definition ra8_rsip_regs_offsets.h:86
k_ra8_rsip_off_sym_aad_in
@ k_ra8_rsip_off_sym_aad_in
AEAD additional-data input.
Definition ra8_rsip_regs_offsets.h:171
k_ra8_rsip_off_kdf_label
@ k_ra8_rsip_off_kdf_label
KDF context label slot.
Definition ra8_rsip_regs_offsets.h:87
k_ra8_rsip_off_sym_pt_len
@ k_ra8_rsip_off_sym_pt_len
AEAD plaintext length (bytes).
Definition ra8_rsip_regs_offsets.h:174
k_ra8_rsip_off_sym_iv2
@ k_ra8_rsip_off_sym_iv2
IV / nonce lane 2.
Definition ra8_rsip_regs_offsets.h:169
k_ra8_rsip_off_oem_bl_inc
@ k_ra8_rsip_off_oem_bl_inc
Increment trigger (W1).
Definition ra8_rsip_regs_offsets.h:77
RA8_RSIP_ASSERT_ALIGN
#define RA8_RSIP_ASSERT_ALIGN(off_)
RA8 RSIP ASSERT ALIGN.
Definition ra8_rsip_regs_offsets.h:253
RA8_RSIP_ASSERT_IN_WIN
#define RA8_RSIP_ASSERT_IN_WIN(off_, lo_, hi_)
RA8 RSIP ASSERT IN WIN.
Definition ra8_rsip_regs_offsets.h:258