ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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board_periph_pdctr.c File Reference

Graphics power-domain gating (PDCTRGD) model. More...

#include <stdint.h>
#include <stdio.h>
#include "board_periph_block.h"
#include "board_periph_pdctr_internal.h"
#include "board_periph_prcr_internal.h"
#include "emu_host_io_internal.h"
#include "ra8_attributes.h"
Include dependency graph for board_periph_pdctr.c:

Go to the source code of this file.

Data Structures

struct  pdctr_state_t
 Graphics power-domain state. More...

Enumerations

enum  pdctr_geom_t : uint64_t {
  k_pdctr_gd_base = 0x4001E110UL ,
  k_pdctr_gd_span = 0x1UL
}
 PDCTRGD window geometry (HUM Ch 11.2.14 p 452). More...
enum  pdctr_mask_t : uint8_t {
  k_pdctr_pdde_mask = 0x01U ,
  k_pdctr_pdcsf_mask = 0x40U ,
  k_pdctr_pdpgsf_mask = 0x80U ,
  k_pdctr_reset_value = 0x81U
}
 PDCTRGD field masks (HUM Ch 11.2.14 p 452). More...
enum  pdctr_order_t : uint32_t { k_pdctr_block_order = 172U }
 Per-tick order slot for the power-domain block. More...

Functions

static void internal_pdctr_reset (void)
 Return PDCTRGD to its documented reset value: domain gated OFF.
bool priv_board_pdctr_graphics_powered (void)
 Report whether the graphics power domain is currently powered.
static uint64_t internal_pdctr_read (uc_engine *uc, uint64_t addr, unsigned size)
 MMIO read of PDCTRGD: PDDE as written, status flags derived.
static void internal_pdctr_write (uc_engine *uc, uint64_t addr, unsigned size, uint64_t value)
 MMIO write of PDCTRGD: apply PDDE, settle the gating flags.
static void internal_pdctr_report (void)
 End-of-run graphics power-domain section.
static void internal_pdctr_block_register (void)
 Register the power-domain block before main (host constructor).

Variables

static pdctr_state_t s_pdctr
static const board_periph_block_t s_k_pdctr_block
 Graphics power-domain block descriptor (self-registered).

Detailed Description

Graphics power-domain gating (PDCTRGD) model.

Models the RA8D2 Graphics Power Domain Control Register, PDCTRGD at SYSC + 0x110 (0x4001_E110) – HUM Ch 11.2.14 p 452. The domain it gates holds MIPI DSI, MIPI CSI, VIN, DRW and GLCDC (HUM Ch 11.5.1 Table 11.7 p 480).

The register's reset value is 0x81: PDPGSF (bit 7) = 1 meaning the domain is gated OFF, and PDDE (bit 0) = 1 meaning "power off the target domain". So every graphics peripheral is unpowered out of reset, and cancelling a module-stop bit is not enough to make one respond. PDDE has inverted polarity: writing 0 powers the domain ON.

Modelling this is what closes issue #247. The D/AVE 2D engine had never rasterised a pixel on real silicon because nothing ever cleared PDDE; ra8_emulator, which modelled no power domain at all, happily let the firmware drive a DRW that on the bench was simply switched off. Bench evidence on an EK-RA8D2: with PDCTRGD at its 0x81 reset value the DRW HWREVISION register reads 0x00000000; after clearing PDDE (with PRCR.PRC1 unlocked) it reads 0x0FBE0107 and the engine rasterises.

PDCTRGD is PRC1-protected (HUM Ch 13.1 Table 13.1 p 521), so writes are routed through priv_board_prcr_group_unlocked and silently discarded while that group is locked – the same silence the hardware gives.

The model completes gating instantly: PDCSF (control-in-progress) always reads 0, so a driver polling "PDCSF == 0" makes progress, while PDPGSF tracks PDDE so the "domain still gated" check is real.

Since
0.1.0

Definition in file board_periph_pdctr.c.

Enumeration Type Documentation

◆ pdctr_geom_t

enum pdctr_geom_t : uint64_t

PDCTRGD window geometry (HUM Ch 11.2.14 p 452).

Enumerator
k_pdctr_gd_base 

PDCTRGD: SYSC 0x4001_E000 + 0x110.

k_pdctr_gd_span 

One 8-bit register.

Definition at line 48 of file board_periph_pdctr.c.

◆ pdctr_mask_t

enum pdctr_mask_t : uint8_t

PDCTRGD field masks (HUM Ch 11.2.14 p 452).

Enumerator
k_pdctr_pdde_mask 

PDDE @ bit 0: 1 = power OFF.

k_pdctr_pdcsf_mask 

PDCSF @ bit 6: control busy.

k_pdctr_pdpgsf_mask 

PDPGSF @ bit 7: 1 = gated off.

k_pdctr_reset_value 

"Value after reset": gated off.

Definition at line 54 of file board_periph_pdctr.c.

◆ pdctr_order_t

enum pdctr_order_t : uint32_t

Per-tick order slot for the power-domain block.

Enumerator
k_pdctr_block_order 

Between PRCR and the VBATT block.

Definition at line 62 of file board_periph_pdctr.c.

Function Documentation

◆ internal_pdctr_block_register()

void internal_pdctr_block_register ( void )
static

Register the power-domain block before main (host constructor).

Definition at line 192 of file board_periph_pdctr.c.

References board_periph_register_block(), internal_pdctr_reset(), RA8_INTERNAL, and s_k_pdctr_block.

◆ internal_pdctr_read()

uint64_t internal_pdctr_read ( uc_engine * uc,
uint64_t addr,
unsigned size )
static

MMIO read of PDCTRGD: PDDE as written, status flags derived.

MMIO read of pdctrgd: pdde as written, status flags derived; this step is contained within the board periph pdctr model and uses bounded caller or module-owned storage.

Parameters
[in,out]ucUnicorn engine whose emulated state is read or updated.
[in]addrGuest address involved in the operation.
[in]sizeSize of the requested region or access in bytes.
Returns
The pdctr read result produced by the board periph pdctr model.
Return values
valueThe operation-specific pdctr read value.
Precondition
Arguments satisfy the ranges documented for pdctr read.
The call executes on the emulator's single owning thread.
Postcondition
State changes remain confined to the board periph pdctr model and documented output objects.
Ownership of caller-supplied storage is unchanged.
Note
The operation is synchronous and does not transfer heap ownership.
Since
0.1.0

Definition at line 107 of file board_periph_pdctr.c.

References RA8_INTERNAL, and s_pdctr.

◆ internal_pdctr_report()

void internal_pdctr_report ( void )
static

End-of-run graphics power-domain section.

End-of-run graphics power-domain section; this step is contained within the board periph pdctr model and uses bounded caller or module-owned storage.

Precondition
Arguments satisfy the ranges documented for pdctr report.
The call executes on the emulator's single owning thread.
Postcondition
State changes remain confined to the board periph pdctr model and documented output objects.
Ownership of caller-supplied storage is unchanged.
Note
The operation is synchronous and does not transfer heap ownership.
Since
0.1.0

Definition at line 163 of file board_periph_pdctr.c.

References priv_emu_io_errf(), RA8_INTERNAL, and s_pdctr.

◆ internal_pdctr_reset()

void internal_pdctr_reset ( void )
static

Return PDCTRGD to its documented reset value: domain gated OFF.

Return pdctrgd to its documented reset value: domain gated off; this step is contained within the board periph pdctr model and uses bounded caller or module-owned storage.

Precondition
Arguments satisfy the ranges documented for pdctr reset.
The call executes on the emulator's single owning thread.
Postcondition
State changes remain confined to the board periph pdctr model and documented output objects.
Ownership of caller-supplied storage is unchanged.
Note
The operation is synchronous and does not transfer heap ownership.
Since
0.1.0

Definition at line 83 of file board_periph_pdctr.c.

References k_pdctr_reset_value, RA8_INTERNAL, and s_pdctr.

Referenced by internal_pdctr_block_register().

◆ internal_pdctr_write()

void internal_pdctr_write ( uc_engine * uc,
uint64_t addr,
unsigned size,
uint64_t value )
static

MMIO write of PDCTRGD: apply PDDE, settle the gating flags.

HUM Ch 11.2.14 p 452: PDDE selects the target state (0 = power on, 1 = power off), PDCSF reports a transition in progress and PDPGSF reports the resulting gate state. Gating is modelled as instantaneous, so PDCSF always settles to 0 and PDPGSF simply follows PDDE.

Parameters
[in,out]ucUnicorn engine whose emulated state is read or updated.
[in]addrGuest address involved in the operation.
[in]sizeSize of the requested region or access in bytes.
[in]valueRegister or payload value involved in the operation.
Precondition
Arguments satisfy the ranges documented for pdctr write.
The call executes on the emulator's single owning thread.
Postcondition
State changes remain confined to the board periph pdctr model and documented output objects.
Ownership of caller-supplied storage is unchanged.
Note
The operation is synchronous and does not transfer heap ownership.
Since
0.1.0

Definition at line 133 of file board_periph_pdctr.c.

References k_board_prcr_grp1_lpm, k_pdctr_pdde_mask, k_pdctr_pdpgsf_mask, priv_board_pdctr_graphics_powered(), priv_board_prcr_group_unlocked(), and s_pdctr.

◆ priv_board_pdctr_graphics_powered()

bool priv_board_pdctr_graphics_powered ( void )

Report whether the graphics power domain is currently powered.

Tracks PDCTRGD.PDPGSF: false while the domain is gated off (the reset state), true once firmware has cleared PDDE with PRCR.PRC1 unlocked.

Returns
true when the graphics domain is powered on.
Return values
truePDPGSF == 0: DRW / GLCDC / MIPI / VIN are alive.
falseDomain still gated; those peripherals read 0.
Precondition
The PDCTRGD block is registered (host constructor, before main).
Postcondition
No state is mutated.
Note
Not thread-safe; ra8_emulator drives all blocks from one thread.
Since
0.1.0
Precondition
The call executes on the emulator's single owning thread.
Postcondition
Ownership of caller-supplied storage is unchanged.

Definition at line 89 of file board_periph_pdctr.c.

References k_pdctr_pdpgsf_mask, RA8_PRIV, and s_pdctr.

Referenced by internal_drw_read(), internal_drw_render_modelled(), internal_drw_write(), and internal_pdctr_write().

Variable Documentation

◆ s_k_pdctr_block

const board_periph_block_t s_k_pdctr_block
static
Initial value:
= {
.base = (uint64_t)k_pdctr_gd_base,
.span = (uint64_t)k_pdctr_gd_span,
.order = (uint32_t)k_pdctr_block_order,
.tick = nullptr,
.name = "PWR-GRAPHICS",
}
static void internal_pdctr_report(void)
End-of-run graphics power-domain section.
@ k_pdctr_gd_span
One 8-bit register.
@ k_pdctr_gd_base
PDCTRGD: SYSC 0x4001_E000 + 0x110.
static void internal_pdctr_write(uc_engine *uc, uint64_t addr, unsigned size, uint64_t value)
MMIO write of PDCTRGD: apply PDDE, settle the gating flags.
static void internal_pdctr_reset(void)
Return PDCTRGD to its documented reset value: domain gated OFF.
static uint64_t internal_pdctr_read(uc_engine *uc, uint64_t addr, unsigned size)
MMIO read of PDCTRGD: PDDE as written, status flags derived.
@ k_pdctr_block_order
Between PRCR and the VBATT block.
-proof

Graphics power-domain block descriptor (self-registered).

Definition at line 179 of file board_periph_pdctr.c.

Referenced by internal_pdctr_block_register().

◆ s_pdctr