ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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r_i3c_i2c_regs_t Struct Reference

Memory-mapped register block for one IIC_B / I3C channel. More...

#include <ra8_i3c_i2c_regs.h>

Data Fields

volatile uint32_t PRTS
 +0x000 Protocol Selection (HUM 40.2, p 2452).
volatile uint32_t RESERVED0 [3]
 Reserved.
volatile uint32_t CECTL
 +0x010 Clock Enable Control (HUM 40.2, p 2453).
volatile uint32_t BCTL
 +0x014 Bus Control (HUM 40.2, p 2454).
volatile uint32_t MSDVAD
 +0x018 Controller Device Address (HUM 40.2, p 2455).
volatile uint32_t RESERVED1
 Reserved.
volatile uint32_t RSTCTL
 +0x020 Reset Control (HUM 40.2, p 2456).
volatile uint32_t PRSST
 +0x024 Present State (HUM 40.2, p 2457).
volatile uint32_t RESERVED2 [2]
 Reserved.
volatile uint32_t INST
 +0x030 Internal Status (HUM 40.2, p 2458).
volatile uint32_t INSTE
 +0x034 Internal Status Enable (HUM 40.2, p 2459).
volatile uint32_t INIE
 +0x038 Internal Interrupt Enable (HUM 40.2, p 2460).
volatile uint32_t INSTFC
 +0x03C Internal Status Force (HUM 40.2, p 2460).
volatile uint32_t RESERVED3
 Reserved.
volatile uint32_t DVCT
 +0x044 Device Characteristic Table (HUM 40.2, p 2460).
volatile uint32_t RESERVED4 [4]
 Reserved.
volatile uint32_t IBINCTL
 +0x058 IBI Notify Control (HUM 40.2, p 2460).
volatile uint32_t RESERVED5
 Reserved.
volatile uint32_t BFCTL
 +0x060 Bus Function Control (HUM 40.2, p 2461).
volatile uint32_t SVCTL
 +0x064 Peripheral Control (HUM 40.2, p 2461).
volatile uint32_t RESERVED6 [2]
 Reserved.
volatile uint32_t REFCKCTL
 +0x070 Reference Clock Control (HUM 40.2, p 2462).
volatile uint32_t STDBR
 +0x074 Standard Bit Rate (HUM 40.2, p 2462).
volatile uint32_t EXTBR
 +0x078 Extended Bit Rate (HUM 40.2, p 2463).
volatile uint32_t BFRECDT
 +0x07C Bus Free Cond Detect Time (HUM 40.2, p 2463).
volatile uint32_t BAVLCDT
 +0x080 Bus Available Cond Detect Time (HUM 40.2, p 2464).
volatile uint32_t BIDLCDT
 +0x084 Bus Idle Cond Detect Time (HUM 40.2, p 2464).
volatile uint32_t OUTCTL
 +0x088 Output Control (HUM 40.2, p 2465).
volatile uint32_t INCTL
 +0x08C Input Control (HUM 40.2, p 2466).
volatile uint32_t TMOCTL
 +0x090 Timeout Control (HUM 40.2, p 2466).
volatile uint32_t RESERVED7
 Reserved.
volatile uint32_t WUCTL
 +0x098 Wake Up Unit Control (HUM 40.2, p 2467).
volatile uint32_t RESERVED8
 Reserved.
volatile uint32_t ACKCTL
 +0x0A0 Acknowledge Control (HUM 40.2, p 2468).
volatile uint32_t SCSTRCTL
 +0x0A4 SCL Stretch Control (HUM 40.2, p 2469).
volatile uint32_t RESERVED9 [2]
 Reserved.
volatile uint32_t SCSTLCTL
 +0x0B0 SCL Stalling Control (HUM 40.2, p 2470).
volatile uint32_t RESERVED10 [3]
 Reserved.
volatile uint32_t SVTDLG0
 +0x0C0 Peripheral Xfer Data Length 0 (HUM 40.2, p 2470).
volatile uint32_t RESERVED11 [k_ra8_i3c_i2c_rsv_words_svtdlg_to_stctl]
 Reserved.
volatile uint32_t STCTL
 +0x120 Synchronous Timing Control (HUM 40.2, p 2471).
volatile uint32_t ATCTL
 +0x124 Asynchronous Timing Control (HUM 40.2, p 2472).
volatile uint32_t ATTRG
 +0x128 Asynchronous Timing Trigger (HUM 40.2, p 2472).
volatile uint32_t ATCCNTE
 +0x12C Async Timing Counter Enable (HUM 40.2, p 2472).
volatile uint32_t RESERVED12 [4]
 Reserved.
volatile uint32_t CNDCTL
 +0x140 Condition Control (HUM 40.2, p 2473).
volatile uint32_t RESERVED13 [3]
 Reserved.
volatile uint32_t NCMDQP
 +0x150 Normal Command Queue Port (HUM 40.2, p 2473).
volatile uint32_t NRSPQP
 +0x154 Normal Response Queue Port (HUM 40.2, p 2475).
volatile uint32_t NTDTBP0
 +0x158 Normal Tx/Rx Data Buffer 0 (HUM 40.2, p 2476).
volatile uint32_t RESERVED14 [k_ra8_i3c_i2c_rsv_words_ntdtbp0_to_nibiqp]
 Reserved.
volatile uint32_t NIBIQP
 +0x17C Normal IBI Queue Port (HUM 40.2, p 2477).
volatile uint32_t NRSQP
 +0x180 Normal Receive Status Queue (HUM 40.2, p 2477).
volatile uint32_t HCMDQP
 +0x184 High Priority Cmd Queue Port (HUM 40.2, p 2478).
volatile uint32_t HRSPQP
 +0x188 High Priority Resp Queue (HUM 40.2, p 2478).
volatile uint32_t HTDTBP
 +0x18C High Priority Tx Data Buffer (HUM 40.2, p 2478).
volatile uint32_t NQTHCTL
 +0x190 Normal Queue Threshold Ctrl (HUM 40.2, p 2479).
volatile uint32_t NTBTHCTL0
 +0x194 Normal Tx/Rx Threshold 0 (HUM 40.2, p 2480).
volatile uint32_t RESERVED15 [k_ra8_i3c_i2c_rsv_words_ntbthctl_to_nrqthc]
 Reserved.
volatile uint32_t NRQTHCTL
 +0x1C0 Normal RxStatus Threshold (HUM 40.2, p 2481).
volatile uint32_t HQTHCTL
 +0x1C4 High Priority Q Threshold (HUM 40.2, p 2481).
volatile uint32_t HTBTHCTL
 +0x1C8 High Priority Tx Threshold (HUM 40.2, p 2482).
volatile uint32_t RESERVED16
 Reserved.
volatile uint32_t BST
 +0x1D0 Bus Status (HUM 40.2, p 2482).
volatile uint32_t BSTE
 +0x1D4 Bus Status Enable (HUM 40.2, p 2483).
volatile uint32_t BIE
 +0x1D8 Bus Interrupt Enable (HUM 40.2, p 2484).
volatile uint32_t BSTFC
 +0x1DC Bus Status Force (HUM 40.2, p 2485).
volatile uint32_t NTST
 +0x1E0 Normal Transfer Status (HUM 40.2, p 2486).
volatile uint32_t NTSTE
 +0x1E4 Normal Xfer Status Enable (HUM 40.2, p 2487).
volatile uint32_t NTIE
 +0x1E8 Normal Xfer Interrupt Enable (HUM 40.2, p 2488).
volatile uint32_t NTSTFC
 +0x1EC Normal Xfer Status Force (HUM 40.2, p 2489).
volatile uint32_t RESERVED17 [4]
 Reserved.
volatile uint32_t HTST
 +0x200 High Priority Xfer Status (HUM 40.2, p 2489).
volatile uint32_t HTSTE
 +0x204 High Priority Xfer St En (HUM 40.2, p 2490).
volatile uint32_t HTIE
 +0x208 High Priority Xfer Int En (HUM 40.2, p 2490).
volatile uint32_t HTSTFC
 +0x20C High Priority Xfer St Force (HUM 40.2, p 2491).
volatile uint32_t BCST
 +0x210 Bus Condition Status (HUM 40.2, p 2491).

Detailed Description

Memory-mapped register block for one IIC_B / I3C channel.

Layout matches HUM Ch 40.2 "I3C Bus Interface Register Descriptions" (p 2452-2614). All registers are 32-bit; bit fields are accessed via the k_ra8_i3c_i2c_*_pos and k_ra8_i3c_i2c_*_msk enums below.

Fields prefixed RESERVED are holes per the HUM and must not be touched.

Definition at line 89 of file ra8_i3c_i2c_regs.h.

Field Documentation

◆ ACKCTL

volatile uint32_t r_i3c_i2c_regs_t::ACKCTL

+0x0A0 Acknowledge Control (HUM 40.2, p 2468).

Definition at line 123 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_apply_init_regs(), internal_i3c_i2c_drain_rx(), and internal_i3c_i2c_rx_phase().

◆ ATCCNTE

volatile uint32_t r_i3c_i2c_regs_t::ATCCNTE

+0x12C Async Timing Counter Enable (HUM 40.2, p 2472).

Definition at line 134 of file ra8_i3c_i2c_regs.h.

◆ ATCTL

volatile uint32_t r_i3c_i2c_regs_t::ATCTL

+0x124 Asynchronous Timing Control (HUM 40.2, p 2472).

Definition at line 132 of file ra8_i3c_i2c_regs.h.

◆ ATTRG

volatile uint32_t r_i3c_i2c_regs_t::ATTRG

+0x128 Asynchronous Timing Trigger (HUM 40.2, p 2472).

Definition at line 133 of file ra8_i3c_i2c_regs.h.

◆ BAVLCDT

volatile uint32_t r_i3c_i2c_regs_t::BAVLCDT

+0x080 Bus Available Cond Detect Time (HUM 40.2, p 2464).

Definition at line 115 of file ra8_i3c_i2c_regs.h.

◆ BCST

volatile uint32_t r_i3c_i2c_regs_t::BCST

+0x210 Bus Condition Status (HUM 40.2, p 2491).

Definition at line 169 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_bus_free().

◆ BCTL

volatile uint32_t r_i3c_i2c_regs_t::BCTL

+0x014 Bus Control (HUM 40.2, p 2454).

Definition at line 93 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_apply_init_regs(), internal_i3c_i2c_block_bringup(), ra8_i3c_i2c_deinit(), ra8_i3c_i2c_peripheral_close(), and ra8_i3c_i2c_peripheral_open().

◆ BFCTL

volatile uint32_t r_i3c_i2c_regs_t::BFCTL

+0x060 Bus Function Control (HUM 40.2, p 2461).

Definition at line 108 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_apply_init_regs().

◆ BFRECDT

volatile uint32_t r_i3c_i2c_regs_t::BFRECDT

+0x07C Bus Free Cond Detect Time (HUM 40.2, p 2463).

Definition at line 114 of file ra8_i3c_i2c_regs.h.

◆ BIDLCDT

volatile uint32_t r_i3c_i2c_regs_t::BIDLCDT

+0x084 Bus Idle Cond Detect Time (HUM 40.2, p 2464).

Definition at line 116 of file ra8_i3c_i2c_regs.h.

◆ BIE

volatile uint32_t r_i3c_i2c_regs_t::BIE

+0x1D8 Bus Interrupt Enable (HUM 40.2, p 2484).

Definition at line 158 of file ra8_i3c_i2c_regs.h.

Referenced by ra8_i3c_i2c_abort(), and ra8_i3c_i2c_attach_handler().

◆ BST

volatile uint32_t r_i3c_i2c_regs_t::BST

+0x1D0 Bus Status (HUM 40.2, p 2482).

Definition at line 156 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_drain_tx(), priv_i3c_i2c_clear_bst(), priv_i3c_i2c_stop(), ra8_i3c_i2c_clear_errors(), ra8_i3c_i2c_get_errors(), ra8_i3c_i2c_peripheral_status(), ra8_i3c_i2c_read(), ra8_i3c_i2c_scan(), and ra8_i3c_i2c_write().

◆ BSTE

volatile uint32_t r_i3c_i2c_regs_t::BSTE

+0x1D4 Bus Status Enable (HUM 40.2, p 2483).

Definition at line 157 of file ra8_i3c_i2c_regs.h.

◆ BSTFC

volatile uint32_t r_i3c_i2c_regs_t::BSTFC

+0x1DC Bus Status Force (HUM 40.2, p 2485).

Definition at line 159 of file ra8_i3c_i2c_regs.h.

◆ CECTL

volatile uint32_t r_i3c_i2c_regs_t::CECTL

+0x010 Clock Enable Control (HUM 40.2, p 2453).

Definition at line 92 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_block_bringup(), and ra8_i3c_i2c_deinit().

◆ CNDCTL

volatile uint32_t r_i3c_i2c_regs_t::CNDCTL

+0x140 Condition Control (HUM 40.2, p 2473).

Definition at line 136 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_restart(), priv_i3c_i2c_start(), and priv_i3c_i2c_stop().

◆ DVCT

volatile uint32_t r_i3c_i2c_regs_t::DVCT

+0x044 Device Characteristic Table (HUM 40.2, p 2460).

Definition at line 104 of file ra8_i3c_i2c_regs.h.

◆ EXTBR

volatile uint32_t r_i3c_i2c_regs_t::EXTBR

+0x078 Extended Bit Rate (HUM 40.2, p 2463).

Definition at line 113 of file ra8_i3c_i2c_regs.h.

◆ HCMDQP

volatile uint32_t r_i3c_i2c_regs_t::HCMDQP

+0x184 High Priority Cmd Queue Port (HUM 40.2, p 2478).

Definition at line 145 of file ra8_i3c_i2c_regs.h.

◆ HQTHCTL

volatile uint32_t r_i3c_i2c_regs_t::HQTHCTL

+0x1C4 High Priority Q Threshold (HUM 40.2, p 2481).

Definition at line 153 of file ra8_i3c_i2c_regs.h.

◆ HRSPQP

volatile uint32_t r_i3c_i2c_regs_t::HRSPQP

+0x188 High Priority Resp Queue (HUM 40.2, p 2478).

Definition at line 146 of file ra8_i3c_i2c_regs.h.

◆ HTBTHCTL

volatile uint32_t r_i3c_i2c_regs_t::HTBTHCTL

+0x1C8 High Priority Tx Threshold (HUM 40.2, p 2482).

Definition at line 154 of file ra8_i3c_i2c_regs.h.

◆ HTDTBP

volatile uint32_t r_i3c_i2c_regs_t::HTDTBP

+0x18C High Priority Tx Data Buffer (HUM 40.2, p 2478).

Definition at line 147 of file ra8_i3c_i2c_regs.h.

◆ HTIE

volatile uint32_t r_i3c_i2c_regs_t::HTIE

+0x208 High Priority Xfer Int En (HUM 40.2, p 2490).

Definition at line 167 of file ra8_i3c_i2c_regs.h.

◆ HTST

volatile uint32_t r_i3c_i2c_regs_t::HTST

+0x200 High Priority Xfer Status (HUM 40.2, p 2489).

Definition at line 165 of file ra8_i3c_i2c_regs.h.

◆ HTSTE

volatile uint32_t r_i3c_i2c_regs_t::HTSTE

+0x204 High Priority Xfer St En (HUM 40.2, p 2490).

Definition at line 166 of file ra8_i3c_i2c_regs.h.

◆ HTSTFC

volatile uint32_t r_i3c_i2c_regs_t::HTSTFC

+0x20C High Priority Xfer St Force (HUM 40.2, p 2491).

Definition at line 168 of file ra8_i3c_i2c_regs.h.

◆ IBINCTL

volatile uint32_t r_i3c_i2c_regs_t::IBINCTL

+0x058 IBI Notify Control (HUM 40.2, p 2460).

Definition at line 106 of file ra8_i3c_i2c_regs.h.

◆ INCTL

volatile uint32_t r_i3c_i2c_regs_t::INCTL

+0x08C Input Control (HUM 40.2, p 2466).

Definition at line 118 of file ra8_i3c_i2c_regs.h.

◆ INIE

volatile uint32_t r_i3c_i2c_regs_t::INIE

+0x038 Internal Interrupt Enable (HUM 40.2, p 2460).

Definition at line 101 of file ra8_i3c_i2c_regs.h.

◆ INST

volatile uint32_t r_i3c_i2c_regs_t::INST

+0x030 Internal Status (HUM 40.2, p 2458).

Definition at line 99 of file ra8_i3c_i2c_regs.h.

◆ INSTE

volatile uint32_t r_i3c_i2c_regs_t::INSTE

+0x034 Internal Status Enable (HUM 40.2, p 2459).

Definition at line 100 of file ra8_i3c_i2c_regs.h.

◆ INSTFC

volatile uint32_t r_i3c_i2c_regs_t::INSTFC

+0x03C Internal Status Force (HUM 40.2, p 2460).

Definition at line 102 of file ra8_i3c_i2c_regs.h.

◆ MSDVAD

volatile uint32_t r_i3c_i2c_regs_t::MSDVAD

+0x018 Controller Device Address (HUM 40.2, p 2455).

Definition at line 94 of file ra8_i3c_i2c_regs.h.

Referenced by ra8_i3c_i2c_peripheral_close(), ra8_i3c_i2c_peripheral_open(), and ra8_i3c_i2c_peripheral_status().

◆ NCMDQP

volatile uint32_t r_i3c_i2c_regs_t::NCMDQP

+0x150 Normal Command Queue Port (HUM 40.2, p 2473).

Definition at line 138 of file ra8_i3c_i2c_regs.h.

◆ NIBIQP

volatile uint32_t r_i3c_i2c_regs_t::NIBIQP

+0x17C Normal IBI Queue Port (HUM 40.2, p 2477).

Definition at line 143 of file ra8_i3c_i2c_regs.h.

◆ NQTHCTL

volatile uint32_t r_i3c_i2c_regs_t::NQTHCTL

+0x190 Normal Queue Threshold Ctrl (HUM 40.2, p 2479).

Definition at line 148 of file ra8_i3c_i2c_regs.h.

◆ NRQTHCTL

volatile uint32_t r_i3c_i2c_regs_t::NRQTHCTL

+0x1C0 Normal RxStatus Threshold (HUM 40.2, p 2481).

Definition at line 152 of file ra8_i3c_i2c_regs.h.

◆ NRSPQP

volatile uint32_t r_i3c_i2c_regs_t::NRSPQP

+0x154 Normal Response Queue Port (HUM 40.2, p 2475).

Definition at line 139 of file ra8_i3c_i2c_regs.h.

◆ NRSQP

volatile uint32_t r_i3c_i2c_regs_t::NRSQP

+0x180 Normal Receive Status Queue (HUM 40.2, p 2477).

Definition at line 144 of file ra8_i3c_i2c_regs.h.

◆ NTBTHCTL0

volatile uint32_t r_i3c_i2c_regs_t::NTBTHCTL0

+0x194 Normal Tx/Rx Threshold 0 (HUM 40.2, p 2480).

Definition at line 149 of file ra8_i3c_i2c_regs.h.

◆ NTDTBP0

volatile uint32_t r_i3c_i2c_regs_t::NTDTBP0

+0x158 Normal Tx/Rx Data Buffer 0 (HUM 40.2, p 2476).

Definition at line 140 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_drain_rx(), internal_i3c_i2c_drain_tx(), internal_i3c_i2c_rx_phase(), priv_i3c_i2c_send_address(), ra8_i3c_i2c_peripheral_receive(), and ra8_i3c_i2c_peripheral_send().

◆ NTIE

volatile uint32_t r_i3c_i2c_regs_t::NTIE

+0x1E8 Normal Xfer Interrupt Enable (HUM 40.2, p 2488).

Definition at line 162 of file ra8_i3c_i2c_regs.h.

Referenced by ra8_i3c_i2c_abort(), and ra8_i3c_i2c_attach_handler().

◆ NTST

volatile uint32_t r_i3c_i2c_regs_t::NTST

+0x1E0 Normal Transfer Status (HUM 40.2, p 2486).

Definition at line 160 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_wait_ntst(), internal_wait_ntst(), and ra8_i3c_i2c_peripheral_status().

◆ NTSTE

volatile uint32_t r_i3c_i2c_regs_t::NTSTE

+0x1E4 Normal Xfer Status Enable (HUM 40.2, p 2487).

Definition at line 161 of file ra8_i3c_i2c_regs.h.

◆ NTSTFC

volatile uint32_t r_i3c_i2c_regs_t::NTSTFC

+0x1EC Normal Xfer Status Force (HUM 40.2, p 2489).

Definition at line 163 of file ra8_i3c_i2c_regs.h.

◆ OUTCTL

volatile uint32_t r_i3c_i2c_regs_t::OUTCTL

+0x088 Output Control (HUM 40.2, p 2465).

Definition at line 117 of file ra8_i3c_i2c_regs.h.

◆ PRSST

volatile uint32_t r_i3c_i2c_regs_t::PRSST

+0x024 Present State (HUM 40.2, p 2457).

Definition at line 97 of file ra8_i3c_i2c_regs.h.

◆ PRTS

volatile uint32_t r_i3c_i2c_regs_t::PRTS

+0x000 Protocol Selection (HUM 40.2, p 2452).

Definition at line 90 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_block_bringup().

◆ REFCKCTL

volatile uint32_t r_i3c_i2c_regs_t::REFCKCTL

+0x070 Reference Clock Control (HUM 40.2, p 2462).

Definition at line 111 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_apply_init_regs().

◆ RESERVED0

volatile uint32_t r_i3c_i2c_regs_t::RESERVED0[3]

Reserved.

Definition at line 91 of file ra8_i3c_i2c_regs.h.

◆ RESERVED1

volatile uint32_t r_i3c_i2c_regs_t::RESERVED1

Reserved.

Definition at line 95 of file ra8_i3c_i2c_regs.h.

◆ RESERVED10

volatile uint32_t r_i3c_i2c_regs_t::RESERVED10[3]

Reserved.

Definition at line 127 of file ra8_i3c_i2c_regs.h.

◆ RESERVED11

volatile uint32_t r_i3c_i2c_regs_t::RESERVED11[k_ra8_i3c_i2c_rsv_words_svtdlg_to_stctl]

Reserved.

Definition at line 130 of file ra8_i3c_i2c_regs.h.

◆ RESERVED12

volatile uint32_t r_i3c_i2c_regs_t::RESERVED12[4]

Reserved.

Definition at line 135 of file ra8_i3c_i2c_regs.h.

◆ RESERVED13

volatile uint32_t r_i3c_i2c_regs_t::RESERVED13[3]

Reserved.

Definition at line 137 of file ra8_i3c_i2c_regs.h.

◆ RESERVED14

volatile uint32_t r_i3c_i2c_regs_t::RESERVED14[k_ra8_i3c_i2c_rsv_words_ntdtbp0_to_nibiqp]

Reserved.

Definition at line 142 of file ra8_i3c_i2c_regs.h.

◆ RESERVED15

volatile uint32_t r_i3c_i2c_regs_t::RESERVED15[k_ra8_i3c_i2c_rsv_words_ntbthctl_to_nrqthc]

Reserved.

Definition at line 151 of file ra8_i3c_i2c_regs.h.

◆ RESERVED16

volatile uint32_t r_i3c_i2c_regs_t::RESERVED16

Reserved.

Definition at line 155 of file ra8_i3c_i2c_regs.h.

◆ RESERVED17

volatile uint32_t r_i3c_i2c_regs_t::RESERVED17[4]

Reserved.

Definition at line 164 of file ra8_i3c_i2c_regs.h.

◆ RESERVED2

volatile uint32_t r_i3c_i2c_regs_t::RESERVED2[2]

Reserved.

Definition at line 98 of file ra8_i3c_i2c_regs.h.

◆ RESERVED3

volatile uint32_t r_i3c_i2c_regs_t::RESERVED3

Reserved.

Definition at line 103 of file ra8_i3c_i2c_regs.h.

◆ RESERVED4

volatile uint32_t r_i3c_i2c_regs_t::RESERVED4[4]

Reserved.

Definition at line 105 of file ra8_i3c_i2c_regs.h.

◆ RESERVED5

volatile uint32_t r_i3c_i2c_regs_t::RESERVED5

Reserved.

Definition at line 107 of file ra8_i3c_i2c_regs.h.

◆ RESERVED6

volatile uint32_t r_i3c_i2c_regs_t::RESERVED6[2]

Reserved.

Definition at line 110 of file ra8_i3c_i2c_regs.h.

◆ RESERVED7

volatile uint32_t r_i3c_i2c_regs_t::RESERVED7

Reserved.

Definition at line 120 of file ra8_i3c_i2c_regs.h.

◆ RESERVED8

volatile uint32_t r_i3c_i2c_regs_t::RESERVED8

Reserved.

Definition at line 122 of file ra8_i3c_i2c_regs.h.

◆ RESERVED9

volatile uint32_t r_i3c_i2c_regs_t::RESERVED9[2]

Reserved.

Definition at line 125 of file ra8_i3c_i2c_regs.h.

◆ RSTCTL

volatile uint32_t r_i3c_i2c_regs_t::RSTCTL

+0x020 Reset Control (HUM 40.2, p 2456).

Definition at line 96 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_reset(), and ra8_i3c_i2c_peripheral_open().

◆ SCSTLCTL

volatile uint32_t r_i3c_i2c_regs_t::SCSTLCTL

+0x0B0 SCL Stalling Control (HUM 40.2, p 2470).

Definition at line 126 of file ra8_i3c_i2c_regs.h.

◆ SCSTRCTL

volatile uint32_t r_i3c_i2c_regs_t::SCSTRCTL

+0x0A4 SCL Stretch Control (HUM 40.2, p 2469).

Definition at line 124 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_apply_init_regs().

◆ STCTL

volatile uint32_t r_i3c_i2c_regs_t::STCTL

+0x120 Synchronous Timing Control (HUM 40.2, p 2471).

Definition at line 131 of file ra8_i3c_i2c_regs.h.

◆ STDBR

volatile uint32_t r_i3c_i2c_regs_t::STDBR

+0x074 Standard Bit Rate (HUM 40.2, p 2462).

Definition at line 112 of file ra8_i3c_i2c_regs.h.

Referenced by internal_i3c_i2c_apply_init_regs(), and ra8_i3c_i2c_set_clock().

◆ SVCTL

volatile uint32_t r_i3c_i2c_regs_t::SVCTL

+0x064 Peripheral Control (HUM 40.2, p 2461).

Definition at line 109 of file ra8_i3c_i2c_regs.h.

Referenced by ra8_i3c_i2c_peripheral_close(), and ra8_i3c_i2c_peripheral_open().

◆ SVTDLG0

volatile uint32_t r_i3c_i2c_regs_t::SVTDLG0

+0x0C0 Peripheral Xfer Data Length 0 (HUM 40.2, p 2470).

Definition at line 128 of file ra8_i3c_i2c_regs.h.

◆ TMOCTL

volatile uint32_t r_i3c_i2c_regs_t::TMOCTL

+0x090 Timeout Control (HUM 40.2, p 2466).

Definition at line 119 of file ra8_i3c_i2c_regs.h.

◆ WUCTL

volatile uint32_t r_i3c_i2c_regs_t::WUCTL

+0x098 Wake Up Unit Control (HUM 40.2, p 2467).

Definition at line 121 of file ra8_i3c_i2c_regs.h.

The documentation for this struct was generated from the following file: