ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_i3c_i2c_regs.h
Go to the documentation of this file.
1
28
29#pragma once
30
31#ifdef __cplusplus
32extern "C" {
33#endif
34
35#include <stdint.h>
36
37#include "ra8_attributes.h"
38
49typedef enum : uintptr_t {
50 k_ra8_i3c_i2c0_base_addr = 0x4035F000UL,
52
57typedef enum : uint16_t {
60
76
89typedef struct {
90 volatile uint32_t PRTS;
91 volatile uint32_t RESERVED0[3];
92 volatile uint32_t CECTL;
93 volatile uint32_t BCTL;
94 volatile uint32_t MSDVAD;
95 volatile uint32_t RESERVED1;
96 volatile uint32_t RSTCTL;
97 volatile uint32_t PRSST;
98 volatile uint32_t RESERVED2[2];
99 volatile uint32_t INST;
100 volatile uint32_t INSTE;
101 volatile uint32_t INIE;
102 volatile uint32_t INSTFC;
103 volatile uint32_t RESERVED3;
104 volatile uint32_t DVCT;
105 volatile uint32_t RESERVED4[4];
106 volatile uint32_t IBINCTL;
107 volatile uint32_t RESERVED5;
108 volatile uint32_t BFCTL;
109 volatile uint32_t SVCTL;
110 volatile uint32_t RESERVED6[2];
111 volatile uint32_t REFCKCTL;
112 volatile uint32_t STDBR;
113 volatile uint32_t EXTBR;
114 volatile uint32_t BFRECDT;
115 volatile uint32_t BAVLCDT;
116 volatile uint32_t BIDLCDT;
117 volatile uint32_t OUTCTL;
118 volatile uint32_t INCTL;
119 volatile uint32_t TMOCTL;
120 volatile uint32_t RESERVED7;
121 volatile uint32_t WUCTL;
122 volatile uint32_t RESERVED8;
123 volatile uint32_t ACKCTL;
124 volatile uint32_t SCSTRCTL;
125 volatile uint32_t RESERVED9[2];
126 volatile uint32_t SCSTLCTL;
127 volatile uint32_t RESERVED10[3];
128 volatile uint32_t SVTDLG0;
131 volatile uint32_t STCTL;
132 volatile uint32_t ATCTL;
133 volatile uint32_t ATTRG;
134 volatile uint32_t ATCCNTE;
135 volatile uint32_t RESERVED12[4];
136 volatile uint32_t CNDCTL;
137 volatile uint32_t RESERVED13[3];
138 volatile uint32_t NCMDQP;
139 volatile uint32_t NRSPQP;
140 volatile uint32_t NTDTBP0;
143 volatile uint32_t NIBIQP;
144 volatile uint32_t NRSQP;
145 volatile uint32_t HCMDQP;
146 volatile uint32_t HRSPQP;
147 volatile uint32_t HTDTBP;
148 volatile uint32_t NQTHCTL;
149 volatile uint32_t NTBTHCTL0;
152 volatile uint32_t NRQTHCTL;
153 volatile uint32_t HQTHCTL;
154 volatile uint32_t HTBTHCTL;
155 volatile uint32_t RESERVED16;
156 volatile uint32_t BST;
157 volatile uint32_t BSTE;
158 volatile uint32_t BIE;
159 volatile uint32_t BSTFC;
160 volatile uint32_t NTST;
161 volatile uint32_t NTSTE;
162 volatile uint32_t NTIE;
163 volatile uint32_t NTSTFC;
164 volatile uint32_t RESERVED17[4];
165 volatile uint32_t HTST;
166 volatile uint32_t HTSTE;
167 volatile uint32_t HTIE;
168 volatile uint32_t HTSTFC;
169 volatile uint32_t BCST;
171
172/* =============================================================================
173 * Bit positions and masks for the registers actually programmed by the
174 * polling-mode IIC_B controller driver. Names mirror the FSP CMSIS field
175 * macros (R_I3C0_xxx_yyy_Pos / _Msk) -- HUM Ch 40.2, p 2452..2491.
176 * =============================================================================
177 */
178
191typedef enum : uint8_t {
194
199typedef enum : uint8_t {
202
207typedef enum : uint8_t {
210
218
227
239
248
257
265
275
288
297
306
317
322typedef enum : uint8_t {
325
326/* =============================================================================
327 * Composite masks built from the bit-position enums above. Keeping the
328 * masks as a typed enum (uint32_t) lets callers OR them together
329 * without per-call shift expressions.
330 * =============================================================================
331 */
332
337typedef enum : uint32_t {
338 k_ra8_i3c_i2c_msk_prts_prtmd = (uint32_t)(1U << 0U),
339 k_ra8_i3c_i2c_msk_cectl_clke = (uint32_t)(1U << 0U),
340 k_ra8_i3c_i2c_msk_bctl_buse = (uint32_t)(1U << 31U),
341 k_ra8_i3c_i2c_msk_rstctl_ri3crst = (uint32_t)(1U << 0U),
342 k_ra8_i3c_i2c_msk_bfctl_male = (uint32_t)(1U << 0U),
343 k_ra8_i3c_i2c_msk_bfctl_nale = (uint32_t)(1U << 1U),
344 k_ra8_i3c_i2c_msk_bfctl_scsyne = (uint32_t)(1U << 8U),
345 k_ra8_i3c_i2c_msk_bfctl_fmpe = (uint32_t)(1U << 14U),
346 k_ra8_i3c_i2c_msk_ackctl_ackt = (uint32_t)(1U << 1U),
347 k_ra8_i3c_i2c_msk_ackctl_acktwp = (uint32_t)(1U << 2U),
348 k_ra8_i3c_i2c_msk_scstrctl_rwe = (uint32_t)(1U << 1U),
349 k_ra8_i3c_i2c_msk_cndctl_stcnd = (uint32_t)(1U << 0U),
350 k_ra8_i3c_i2c_msk_cndctl_srcnd = (uint32_t)(1U << 1U),
351 k_ra8_i3c_i2c_msk_cndctl_spcnd = (uint32_t)(1U << 2U),
352 k_ra8_i3c_i2c_msk_bst_stcnddf = (uint32_t)(1U << 0U),
353 k_ra8_i3c_i2c_msk_bst_spcnddf = (uint32_t)(1U << 1U),
354 k_ra8_i3c_i2c_msk_bst_nackdf = (uint32_t)(1U << 4U),
355 k_ra8_i3c_i2c_msk_bst_tendf = (uint32_t)(1U << 8U),
356 k_ra8_i3c_i2c_msk_bst_alf = (uint32_t)(1U << 16U),
357 k_ra8_i3c_i2c_msk_bst_todf = (uint32_t)(1U << 20U),
358 k_ra8_i3c_i2c_msk_ntst_tdbef0 = (uint32_t)(1U << 0U),
359 k_ra8_i3c_i2c_msk_ntst_rdbff0 = (uint32_t)(1U << 1U),
360 k_ra8_i3c_i2c_msk_ntie_tdbeie0 = (uint32_t)(1U << 0U),
361 k_ra8_i3c_i2c_msk_ntie_rdbfie0 = (uint32_t)(1U << 1U),
362 k_ra8_i3c_i2c_msk_bie_nackdie = (uint32_t)(1U << 4U),
363 k_ra8_i3c_i2c_msk_bie_tendie = (uint32_t)(1U << 8U),
364 k_ra8_i3c_i2c_msk_bie_alie = (uint32_t)(1U << 16U),
365 k_ra8_i3c_i2c_msk_bie_todie = (uint32_t)(1U << 20U),
366 k_ra8_i3c_i2c_msk_bcst_bfref = (uint32_t)(1U << 0U),
368
387static inline volatile r_i3c_i2c_regs_t* i3c_i2c_regs(uint8_t channel)
388{
389 if ((uint16_t)channel >= k_ra8_i3c_i2c_channel_count) {
390 return nullptr;
391 }
393}
394
395#ifdef __cplusplus
396}
397#endif
Annotation-attribute framework macros for ra8-firmware.
#define RA8_HW_REGISTER_ACCESS
Mark an MMIO accessor function (returns volatile register pointer).
ra8_i3c_i2c_bfctl_t
BFCTL field positions.
@ k_ra8_i3c_i2c_bfctl_fmpe_pos
HUM 40.2 BFCTL.FMPE, p 2461.
@ k_ra8_i3c_i2c_bfctl_scsyne_pos
HUM 40.2 BFCTL.SCSYNE, p 2461.
@ k_ra8_i3c_i2c_bfctl_male_pos
HUM 40.2 BFCTL.MALE, p 2461.
@ k_ra8_i3c_i2c_bfctl_smbs_pos
HUM 40.2 BFCTL.SMBS, p 2461.
@ k_ra8_i3c_i2c_bfctl_nale_pos
HUM 40.2 BFCTL.NALE, p 2461.
ra8_i3c_i2c_bst_t
BST (Bus Status) field positions.
@ k_ra8_i3c_i2c_bst_spcnddf_pos
HUM 40.2 BST.SPCNDDF, p 2482.
@ k_ra8_i3c_i2c_bst_nackdf_pos
HUM 40.2 BST.NACKDF, p 2482.
@ k_ra8_i3c_i2c_bst_tendf_pos
HUM 40.2 BST.TENDF, p 2482.
@ k_ra8_i3c_i2c_bst_todf_pos
HUM 40.2 BST.TODF, p 2482.
@ k_ra8_i3c_i2c_bst_stcnddf_pos
HUM 40.2 BST.STCNDDF, p 2482.
@ k_ra8_i3c_i2c_bst_alf_pos
HUM 40.2 BST.ALF, p 2482.
ra8_i3c_i2c_bctl_t
BCTL field positions.
@ k_ra8_i3c_i2c_bctl_buse_pos
HUM 40.2 BCTL.BUSE, p 2454.
ra8_i3c_i2c_cectl_t
CECTL field positions.
@ k_ra8_i3c_i2c_cectl_clke_pos
HUM 40.2 CECTL.CLKE, p 2453.
ra8_i3c_i2c_prts_t
PRTS field positions (HUM Ch 40.2.1 "PRTS : Protocol Selection" p 2449).
@ k_ra8_i3c_i2c_prts_prtmd_pos
HUM 40.2.1 PRTS.PRTMD, p 2449.
ra8_i3c_i2c_scstrctl_t
SCSTRCTL field positions.
@ k_ra8_i3c_i2c_scstrctl_rwe_pos
HUM 40.2 SCSTRCTL.RWE, p 2469.
ra8_i3c_i2c_rsv_words_t
Reserved-word array sizes (in 32-bit words) used inside the IIC_B / I3C register block.
@ k_ra8_i3c_i2c_rsv_words_ntdtbp0_to_nibiqp
+0x015C..0x017B gap.
@ k_ra8_i3c_i2c_rsv_words_ntbthctl_to_nrqthc
+0x0198..0x01BF gap.
@ k_ra8_i3c_i2c_rsv_words_svtdlg_to_stctl
+0x00C4..0x011F gap.
ra8_i3c_i2c_ntst_t
NTST (Normal Transfer Status) field positions.
@ k_ra8_i3c_i2c_ntst_tdbef0_pos
HUM 40.2 NTST.TDBEF0, p 2486.
@ k_ra8_i3c_i2c_ntst_rdbff0_pos
HUM 40.2 NTST.RDBFF0, p 2486.
ra8_i3c_i2c_rstctl_t
RSTCTL field positions.
@ k_ra8_i3c_i2c_rstctl_ri3crst_pos
HUM 40.2 RSTCTL.RI3CRST, p 2456.
ra8_i3c_i2c_ntie_t
NTIE (Normal Transfer Interrupt Enable) field positions.
@ k_ra8_i3c_i2c_ntie_rdbfie0_pos
HUM 40.2 NTIE.RDBFIE0, p 2488.
@ k_ra8_i3c_i2c_ntie_tdbeie0_pos
HUM 40.2 NTIE.TDBEIE0, p 2488.
ra8_i3c_i2c_limits_t
Channel-count limits.
@ k_ra8_i3c_i2c_channel_count
HUM Ch 40.1.1, p 2445.
static volatile r_i3c_i2c_regs_t * i3c_i2c_regs(uint8_t channel)
Get a pointer to the IIC_B / I3C channel channel.
ra8_i3c_i2c_mask_t
Composite bit masks used by the polling driver.
@ k_ra8_i3c_i2c_msk_bie_nackdie
HUM 40.2 BIE.NACKDIE, p 2484.
@ k_ra8_i3c_i2c_msk_bie_tendie
HUM 40.2 BIE.TENDIE, p 2484.
@ k_ra8_i3c_i2c_msk_ackctl_ackt
HUM 40.2 ACKCTL.ACKT, p 2468.
@ k_ra8_i3c_i2c_msk_ntie_tdbeie0
HUM 40.2 NTIE.TDBEIE0, p 2488.
@ k_ra8_i3c_i2c_msk_bst_nackdf
HUM 40.2 BST.NACKDF, p 2482.
@ k_ra8_i3c_i2c_msk_bfctl_nale
HUM 40.2 BFCTL.NALE, p 2461.
@ k_ra8_i3c_i2c_msk_rstctl_ri3crst
HUM 40.2 RSTCTL.RI3CRST, p 2456.
@ k_ra8_i3c_i2c_msk_bfctl_scsyne
HUM 40.2 BFCTL.SCSYNE, p 2461.
@ k_ra8_i3c_i2c_msk_cndctl_spcnd
HUM 40.2 CNDCTL.SPCND, p 2473.
@ k_ra8_i3c_i2c_msk_prts_prtmd
HUM 40.2.1 PRTS.PRTMD, p 2449.
@ k_ra8_i3c_i2c_msk_bst_spcnddf
HUM 40.2 BST.SPCNDDF, p 2482.
@ k_ra8_i3c_i2c_msk_scstrctl_rwe
HUM 40.2 SCSTRCTL.RWE, p 2469.
@ k_ra8_i3c_i2c_msk_bst_stcnddf
HUM 40.2 BST.STCNDDF, p 2482.
@ k_ra8_i3c_i2c_msk_bcst_bfref
HUM 40.2 BCST.BFREF, p 2491.
@ k_ra8_i3c_i2c_msk_bie_alie
HUM 40.2 BIE.ALIE, p 2484.
@ k_ra8_i3c_i2c_msk_cndctl_stcnd
HUM 40.2 CNDCTL.STCND, p 2473.
@ k_ra8_i3c_i2c_msk_bst_tendf
HUM 40.2 BST.TENDF, p 2482.
@ k_ra8_i3c_i2c_msk_ntst_tdbef0
HUM 40.2 NTST.TDBEF0, p 2486.
@ k_ra8_i3c_i2c_msk_bst_alf
HUM 40.2 BST.ALF, p 2482.
@ k_ra8_i3c_i2c_msk_bst_todf
HUM 40.2 BST.TODF, p 2482.
@ k_ra8_i3c_i2c_msk_bctl_buse
HUM 40.2 BCTL.BUSE, p 2454.
@ k_ra8_i3c_i2c_msk_bfctl_fmpe
HUM 40.2 BFCTL.FMPE, p 2461.
@ k_ra8_i3c_i2c_msk_cectl_clke
HUM 40.2 CECTL.CLKE, p 2453.
@ k_ra8_i3c_i2c_msk_ntie_rdbfie0
HUM 40.2 NTIE.RDBFIE0, p 2488.
@ k_ra8_i3c_i2c_msk_bie_todie
HUM 40.2 BIE.TODIE, p 2484.
@ k_ra8_i3c_i2c_msk_ntst_rdbff0
HUM 40.2 NTST.RDBFF0, p 2486.
@ k_ra8_i3c_i2c_msk_bfctl_male
HUM 40.2 BFCTL.MALE, p 2461.
@ k_ra8_i3c_i2c_msk_ackctl_acktwp
HUM 40.2 ACKCTL.ACKTWP,p 2468.
@ k_ra8_i3c_i2c_msk_cndctl_srcnd
HUM 40.2 CNDCTL.SRCND, p 2473.
ra8_i3c_i2c_stdbr_t
STDBR field positions.
@ k_ra8_i3c_i2c_stdbr_sbrlo_pos
HUM 40.2 STDBR.SBRLO, p 2462.
@ k_ra8_i3c_i2c_stdbr_sbrho_pos
HUM 40.2 STDBR.SBRHO, p 2462.
ra8_i3c_i2c_addr_t
Hardware base addresses for the I3C / IIC_B block.
@ k_ra8_i3c_i2c0_base_addr
HUM Ch 40.2, p 2452.
ra8_i3c_i2c_cndctl_t
CNDCTL field positions.
@ k_ra8_i3c_i2c_cndctl_srcnd_pos
HUM 40.2 CNDCTL.SRCND, p 2473.
@ k_ra8_i3c_i2c_cndctl_stcnd_pos
HUM 40.2 CNDCTL.STCND, p 2473.
@ k_ra8_i3c_i2c_cndctl_spcnd_pos
HUM 40.2 CNDCTL.SPCND, p 2473.
ra8_i3c_i2c_bie_t
BIE (Bus Interrupt Enable) field positions.
@ k_ra8_i3c_i2c_bie_nackdie_pos
HUM 40.2 BIE.NACKDIE, p 2484.
@ k_ra8_i3c_i2c_bie_todie_pos
HUM 40.2 BIE.TODIE, p 2484.
@ k_ra8_i3c_i2c_bie_alie_pos
HUM 40.2 BIE.ALIE, p 2484.
@ k_ra8_i3c_i2c_bie_tendie_pos
HUM 40.2 BIE.TENDIE, p 2484.
ra8_i3c_i2c_prsst_t
PRSST field positions.
@ k_ra8_i3c_i2c_prsst_crms_pos
HUM 40.2 PRSST.CRMS, p 2457.
@ k_ra8_i3c_i2c_prsst_trmd_pos
HUM 40.2 PRSST.TRMD, p 2457.
ra8_i3c_i2c_ackctl_t
ACKCTL field positions.
@ k_ra8_i3c_i2c_ackctl_ackt_pos
HUM 40.2 ACKCTL.ACKT, p 2468.
@ k_ra8_i3c_i2c_ackctl_acktwp_pos
HUM 40.2 ACKCTL.ACKTWP, p 2468.
ra8_i3c_i2c_bcst_t
BCST (Bus Condition Status) field positions.
@ k_ra8_i3c_i2c_bcst_bfref_pos
HUM 40.2 BCST.BFREF, p 2491.
Memory-mapped register block for one IIC_B / I3C channel.
volatile uint32_t RESERVED4[4]
Reserved.
volatile uint32_t NTST
+0x1E0 Normal Transfer Status (HUM 40.2, p 2486).
volatile uint32_t OUTCTL
+0x088 Output Control (HUM 40.2, p 2465).
volatile uint32_t NRSQP
+0x180 Normal Receive Status Queue (HUM 40.2, p 2477).
volatile uint32_t REFCKCTL
+0x070 Reference Clock Control (HUM 40.2, p 2462).
volatile uint32_t PRSST
+0x024 Present State (HUM 40.2, p 2457).
volatile uint32_t BIDLCDT
+0x084 Bus Idle Cond Detect Time (HUM 40.2, p 2464).
volatile uint32_t INIE
+0x038 Internal Interrupt Enable (HUM 40.2, p 2460).
volatile uint32_t BCST
+0x210 Bus Condition Status (HUM 40.2, p 2491).
volatile uint32_t RESERVED1
Reserved.
volatile uint32_t NTBTHCTL0
+0x194 Normal Tx/Rx Threshold 0 (HUM 40.2, p 2480).
volatile uint32_t CECTL
+0x010 Clock Enable Control (HUM 40.2, p 2453).
volatile uint32_t HTDTBP
+0x18C High Priority Tx Data Buffer (HUM 40.2, p 2478).
volatile uint32_t STDBR
+0x074 Standard Bit Rate (HUM 40.2, p 2462).
volatile uint32_t SCSTLCTL
+0x0B0 SCL Stalling Control (HUM 40.2, p 2470).
volatile uint32_t HTSTE
+0x204 High Priority Xfer St En (HUM 40.2, p 2490).
volatile uint32_t NQTHCTL
+0x190 Normal Queue Threshold Ctrl (HUM 40.2, p 2479).
volatile uint32_t ATCCNTE
+0x12C Async Timing Counter Enable (HUM 40.2, p 2472).
volatile uint32_t NTSTFC
+0x1EC Normal Xfer Status Force (HUM 40.2, p 2489).
volatile uint32_t SVTDLG0
+0x0C0 Peripheral Xfer Data Length 0 (HUM 40.2, p 2470).
volatile uint32_t BST
+0x1D0 Bus Status (HUM 40.2, p 2482).
volatile uint32_t RESERVED11[k_ra8_i3c_i2c_rsv_words_svtdlg_to_stctl]
Reserved.
volatile uint32_t NIBIQP
+0x17C Normal IBI Queue Port (HUM 40.2, p 2477).
volatile uint32_t INSTFC
+0x03C Internal Status Force (HUM 40.2, p 2460).
volatile uint32_t BFRECDT
+0x07C Bus Free Cond Detect Time (HUM 40.2, p 2463).
volatile uint32_t RESERVED10[3]
Reserved.
volatile uint32_t BCTL
+0x014 Bus Control (HUM 40.2, p 2454).
volatile uint32_t INCTL
+0x08C Input Control (HUM 40.2, p 2466).
volatile uint32_t PRTS
+0x000 Protocol Selection (HUM 40.2, p 2452).
volatile uint32_t ATTRG
+0x128 Asynchronous Timing Trigger (HUM 40.2, p 2472).
volatile uint32_t HTIE
+0x208 High Priority Xfer Int En (HUM 40.2, p 2490).
volatile uint32_t RESERVED14[k_ra8_i3c_i2c_rsv_words_ntdtbp0_to_nibiqp]
Reserved.
volatile uint32_t MSDVAD
+0x018 Controller Device Address (HUM 40.2, p 2455).
volatile uint32_t NTIE
+0x1E8 Normal Xfer Interrupt Enable (HUM 40.2, p 2488).
volatile uint32_t BIE
+0x1D8 Bus Interrupt Enable (HUM 40.2, p 2484).
volatile uint32_t EXTBR
+0x078 Extended Bit Rate (HUM 40.2, p 2463).
volatile uint32_t BAVLCDT
+0x080 Bus Available Cond Detect Time (HUM 40.2, p 2464).
volatile uint32_t HTBTHCTL
+0x1C8 High Priority Tx Threshold (HUM 40.2, p 2482).
volatile uint32_t RESERVED5
Reserved.
volatile uint32_t RESERVED7
Reserved.
volatile uint32_t RESERVED15[k_ra8_i3c_i2c_rsv_words_ntbthctl_to_nrqthc]
Reserved.
volatile uint32_t IBINCTL
+0x058 IBI Notify Control (HUM 40.2, p 2460).
volatile uint32_t RESERVED0[3]
Reserved.
volatile uint32_t INSTE
+0x034 Internal Status Enable (HUM 40.2, p 2459).
volatile uint32_t RESERVED13[3]
Reserved.
volatile uint32_t RESERVED9[2]
Reserved.
volatile uint32_t ATCTL
+0x124 Asynchronous Timing Control (HUM 40.2, p 2472).
volatile uint32_t WUCTL
+0x098 Wake Up Unit Control (HUM 40.2, p 2467).
volatile uint32_t NRSPQP
+0x154 Normal Response Queue Port (HUM 40.2, p 2475).
volatile uint32_t RESERVED8
Reserved.
volatile uint32_t RESERVED6[2]
Reserved.
volatile uint32_t SCSTRCTL
+0x0A4 SCL Stretch Control (HUM 40.2, p 2469).
volatile uint32_t NTSTE
+0x1E4 Normal Xfer Status Enable (HUM 40.2, p 2487).
volatile uint32_t STCTL
+0x120 Synchronous Timing Control (HUM 40.2, p 2471).
volatile uint32_t HTSTFC
+0x20C High Priority Xfer St Force (HUM 40.2, p 2491).
volatile uint32_t RESERVED12[4]
Reserved.
volatile uint32_t INST
+0x030 Internal Status (HUM 40.2, p 2458).
volatile uint32_t BSTFC
+0x1DC Bus Status Force (HUM 40.2, p 2485).
volatile uint32_t DVCT
+0x044 Device Characteristic Table (HUM 40.2, p 2460).
volatile uint32_t HQTHCTL
+0x1C4 High Priority Q Threshold (HUM 40.2, p 2481).
volatile uint32_t HCMDQP
+0x184 High Priority Cmd Queue Port (HUM 40.2, p 2478).
volatile uint32_t ACKCTL
+0x0A0 Acknowledge Control (HUM 40.2, p 2468).
volatile uint32_t NRQTHCTL
+0x1C0 Normal RxStatus Threshold (HUM 40.2, p 2481).
volatile uint32_t RESERVED17[4]
Reserved.
volatile uint32_t RESERVED2[2]
Reserved.
volatile uint32_t HTST
+0x200 High Priority Xfer Status (HUM 40.2, p 2489).
volatile uint32_t RSTCTL
+0x020 Reset Control (HUM 40.2, p 2456).
volatile uint32_t SVCTL
+0x064 Peripheral Control (HUM 40.2, p 2461).
volatile uint32_t NCMDQP
+0x150 Normal Command Queue Port (HUM 40.2, p 2473).
volatile uint32_t TMOCTL
+0x090 Timeout Control (HUM 40.2, p 2466).
volatile uint32_t BSTE
+0x1D4 Bus Status Enable (HUM 40.2, p 2483).
volatile uint32_t NTDTBP0
+0x158 Normal Tx/Rx Data Buffer 0 (HUM 40.2, p 2476).
volatile uint32_t BFCTL
+0x060 Bus Function Control (HUM 40.2, p 2461).
volatile uint32_t RESERVED3
Reserved.
volatile uint32_t CNDCTL
+0x140 Condition Control (HUM 40.2, p 2473).
volatile uint32_t HRSPQP
+0x188 High Priority Resp Queue (HUM 40.2, p 2478).
volatile uint32_t RESERVED16
Reserved.