ra8_i3c_i2c_peripheral.c

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#include "ra8_i3c_i2c_peripheral.h"
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_i3c_i2c_regs.h"
#include "ra8_log.h"
#include "ra8_mstp.h"
#include "ra8_mstp_regs.h"
 
static const char* s_tag = "IICBP";

typedef enum : uint32_t {
  k_ra8_i3c_i2c_peripheral_spin_budget = 50000U, 
  k_ra8_i3c_i2c_peripheral_max_addr_7b = 0x7FU,  
} ra8_i3c_i2c_peripheral_internal_t;

typedef enum : uint32_t {
  k_ra8_i3c_i2c_peripheral_msk_ntst_tdbef0   = (uint32_t)(1U << 0U), 
  k_ra8_i3c_i2c_peripheral_msk_ntst_rdbff0   = (uint32_t)(1U << 1U), 
  k_ra8_i3c_i2c_peripheral_msk_svctl_gcae    = (uint32_t)(1U << 0U), 
  k_ra8_i3c_i2c_peripheral_msdvad_shift_dvad = 1U,                   
  k_ra8_i3c_i2c_peripheral_byte_mask         = 0xFFU,                
} ra8_i3c_i2c_peripheral_bits_t;

RA8_INTERNAL static ra8_err_t internal_wait_ntst(volatile const r_i3c_i2c_regs_t* reg,
                                                 uint32_t                         mask)
{
  for (uint32_t i = 0U; i < k_ra8_i3c_i2c_peripheral_spin_budget; ++i) {
    if ((reg->NTST & mask) == mask) {
      return k_ra8_ok;
    }
  }
  return k_ra8_err_hw_timeout;
}
 
ra8_err_t ra8_i3c_i2c_peripheral_open(uint8_t channel, const ra8_i3c_i2c_peripheral_cfg_t* cfg)
{
  RA8_CHECK_NULL_PTR(cfg, s_tag, "ra8_i3c_i2c_peripheral_open: cfg null");
  volatile r_i3c_i2c_regs_t* reg = i3c_i2c_regs(channel);
  if (reg == nullptr) {
    ra8_log_error(s_tag, "ra8_i3c_i2c_peripheral_open: channel out of range");
    return k_ra8_err_invalid_arg;
  }
  if (cfg->peripheral_addr_7b > (uint8_t)k_ra8_i3c_i2c_peripheral_max_addr_7b) {
    return k_ra8_err_invalid_arg;
  }
 
  /* HUM Ch 11.2.7 "MSTPCRB : Module Stop Control Register B", p 445 -- the R_I3C
   * block is clock-gated OFF at reset; cancel its module-stop (MSTPB4) before the
   * first responder register write or the peripheral never sees the bus. Omitting
   * this ran clean in ra8_emulator yet was inert on silicon until #405 modelled the
   * gate, which surfaced the miss here (the controller path already ungated). The
   * writes are guarded so a failed ungate does not touch a still-gated block, and
   * the outcome is returned from the single exit below (no extra return path). */
  const ra8_err_t mst_err = ra8_mstp_enable(k_ra8_mstp_i3c);
  if (mst_err == k_ra8_ok) {
    reg->RSTCTL = 0U;
    reg->MSDVAD = (uint32_t)cfg->peripheral_addr_7b << k_ra8_i3c_i2c_peripheral_msdvad_shift_dvad;
    reg->SVCTL  = (cfg->general_call != 0U) ? k_ra8_i3c_i2c_peripheral_msk_svctl_gcae : 0U;
    reg->BCTL   = k_ra8_i3c_i2c_msk_bctl_buse;
    ra8_log_info_val(s_tag, "ra8_i3c_i2c_peripheral_open ch", (uint32_t)channel);
  }
  return mst_err;
}
 
ra8_err_t ra8_i3c_i2c_peripheral_close(uint8_t channel)
{
  volatile r_i3c_i2c_regs_t* reg = i3c_i2c_regs(channel);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  reg->BCTL   = 0U;
  reg->MSDVAD = 0U;
  reg->SVCTL  = 0U;
  /* Release the I3C module-stop reference taken in peripheral_open (ref-counted;
   * HUM Ch 11.2.7 "MSTPCRB : Module Stop Control Register B", p 445). */
  return ra8_mstp_disable(k_ra8_mstp_i3c);
}
 
ra8_err_t ra8_i3c_i2c_peripheral_send(uint8_t channel, const uint8_t* data, uint32_t len)
{
  volatile r_i3c_i2c_regs_t* reg = i3c_i2c_regs(channel);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if ((len > 0U) && (data == nullptr)) {
    ra8_log_error(s_tag, "ra8_i3c_i2c_peripheral_send: data null");
    return k_ra8_err_null_ptr;
  }
  for (uint32_t i = 0U; i < len; ++i) {
    RA8_RETURN_ON_ERROR(internal_wait_ntst(reg, k_ra8_i3c_i2c_peripheral_msk_ntst_tdbef0),
                        s_tag,
                        "ra8_i3c_i2c_peripheral_send: TDBEF0 wait");
    reg->NTDTBP0 = (uint32_t)data[i];
  }
  return k_ra8_ok;
}
 
ra8_err_t ra8_i3c_i2c_peripheral_receive(uint8_t channel, uint8_t* buf, uint32_t len)
{
  volatile const r_i3c_i2c_regs_t* reg = i3c_i2c_regs(channel);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if ((len > 0U) && (buf == nullptr)) {
    ra8_log_error(s_tag, "ra8_i3c_i2c_peripheral_receive: buf null");
    return k_ra8_err_null_ptr;
  }
  for (uint32_t i = 0U; i < len; ++i) {
    RA8_RETURN_ON_ERROR(internal_wait_ntst(reg, k_ra8_i3c_i2c_peripheral_msk_ntst_rdbff0),
                        s_tag,
                        "ra8_i3c_i2c_peripheral_receive: RDBFF0 wait");
    buf[i] = (uint8_t)(reg->NTDTBP0 & k_ra8_i3c_i2c_peripheral_byte_mask);
  }
  return k_ra8_ok;
}
 
ra8_err_t ra8_i3c_i2c_peripheral_status(uint8_t channel, uint8_t* out_mask)
{
  RA8_CHECK_NULL_PTR(out_mask, s_tag, "ra8_i3c_i2c_peripheral_status: out_mask null");
  volatile const r_i3c_i2c_regs_t* reg = i3c_i2c_regs(channel);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  const uint32_t ntst = reg->NTST;
  const uint32_t bst  = reg->BST;
  uint8_t        mask = 0U;
  if ((ntst & k_ra8_i3c_i2c_peripheral_msk_ntst_rdbff0) != 0U) {
    mask |= k_ra8_i3c_i2c_peripheral_status_rx_full;
  }
  if ((ntst & k_ra8_i3c_i2c_peripheral_msk_ntst_tdbef0) != 0U) {
    mask |= k_ra8_i3c_i2c_peripheral_status_tx_empty;
  }
  if ((bst & k_ra8_i3c_i2c_msk_bst_spcnddf) != 0U) {
    mask |= k_ra8_i3c_i2c_peripheral_status_stop;
  }
  if ((bst & k_ra8_i3c_i2c_msk_bst_nackdf) != 0U) {
    mask |= k_ra8_i3c_i2c_peripheral_status_nack;
  }
  if (reg->MSDVAD != 0U) {
    mask |= k_ra8_i3c_i2c_peripheral_status_aas;
  }
  *out_mask = mask;
  return k_ra8_ok;
}