- Generated by
1.16.1
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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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Video Input Module (VIN) register layout for the RA8D2. More...
Go to the source code of this file.
Enumerations | |
| enum | ra8_vin_addr_t : uintptr_t { k_ra8_vin0_base_addr = 0x40347400UL , k_ra8_vin0_ns_base_addr = 0x50347400UL } |
| Memory-mapped base addresses for the VIN block. More... | |
| enum | ra8_vin_off_t : uint16_t { k_ra8_vin_off_mc = 0x000U , k_ra8_vin_off_ms = 0x004U , k_ra8_vin_off_fc = 0x008U , k_ra8_vin_off_slprc = 0x00CU , k_ra8_vin_off_elprc = 0x010U , k_ra8_vin_off_spprc = 0x014U , k_ra8_vin_off_epprc = 0x018U , k_ra8_vin_off_csi_ifmd = 0x020U , k_ra8_vin_off_csifld = 0x024U , k_ra8_vin_off_is = 0x02CU , k_ra8_vin_off_mb1 = 0x030U , k_ra8_vin_off_mb2 = 0x034U , k_ra8_vin_off_mb3 = 0x038U , k_ra8_vin_off_lc = 0x03CU , k_ra8_vin_off_ie = 0x040U , k_ra8_vin_off_ints = 0x044U , k_ra8_vin_off_si = 0x048U , k_ra8_vin_off_mtcstop = 0x054U , k_ra8_vin_off_dmr = 0x058U , k_ra8_vin_off_uvaof = 0x060U , k_ra8_vin_off_uds_ctrl = 0x080U , k_ra8_vin_off_uds_scale = 0x084U , k_ra8_vin_off_uds_pass_bwidth = 0x090U , k_ra8_vin_off_uds_clip_size = 0x0A4U , k_ra8_vin_off_lutp = 0x100U , k_ra8_vin_off_lutd = 0x104U , k_ra8_vin_off_yccr1 = 0x228U , k_ra8_vin_off_yccr2 = 0x22CU , k_ra8_vin_off_yccr3 = 0x230U , k_ra8_vin_off_cbccr1 = 0x234U , k_ra8_vin_off_cbccr2 = 0x238U , k_ra8_vin_off_cbccr3 = 0x23CU , k_ra8_vin_off_crccr1 = 0x240U , k_ra8_vin_off_crccr2 = 0x244U , k_ra8_vin_off_crccr3 = 0x248U , k_ra8_vin_off_csce1 = 0x300U , k_ra8_vin_off_csce2 = 0x304U , k_ra8_vin_off_csce3 = 0x308U , k_ra8_vin_off_csce4 = 0x30CU } |
| 32-bit register offsets inside the VIN window. More... | |
| enum | ra8_vin_mc_mask_t : uint32_t { k_ra8_vin_mc_me = 0x00000001UL , k_ra8_vin_mc_bps = 0x00000002UL , k_ra8_vin_mc_im = 0x00000018UL , k_ra8_vin_mc_en = 0x00000040UL , k_ra8_vin_mc_dc = 0x0000C000UL , k_ra8_vin_mc_inf = 0x00070000UL , k_ra8_vin_mc_lute = 0x00100000UL , k_ra8_vin_mc_st = 0x00400000UL , k_ra8_vin_mc_dc2 = 0x01000000UL , k_ra8_vin_mc_yuv444 = 0x02000000UL , k_ra8_vin_mc_scle = 0x04000000UL , k_ra8_vin_mc_clp = 0x30000000UL } |
| Bit masks for the MC (Main Control) register. More... | |
| enum | ra8_vin_mc_shift_t : uint8_t { k_ra8_vin_mc_shift_im = 3U , k_ra8_vin_mc_shift_dc = 14U , k_ra8_vin_mc_shift_inf = 16U , k_ra8_vin_mc_shift_clp = 28U } |
| Field shift positions for multi-bit MC fields. More... | |
| enum | ra8_vin_fc_mask_t : uint32_t { k_ra8_vin_fc_cc = 0x00000002UL } |
| Bit masks for the FC (Frame Capture) register. More... | |
| enum | ra8_vin_ms_mask_t : uint32_t { k_ra8_vin_ms_ca = 0x00000001UL , k_ra8_vin_ms_av = 0x00000002UL , k_ra8_vin_ms_fs = 0x00000004UL , k_ra8_vin_ms_fbs = 0x00000018UL , k_ra8_vin_ms_ma = 0x00010000UL , k_ra8_vin_ms_fms = 0x00180000UL } |
| Bit masks for the MS (Module Status) register. More... | |
| enum | ra8_vin_ms_shift_t : uint8_t { k_ra8_vin_ms_shift_fbs = 3U , k_ra8_vin_ms_shift_fms = 19U } |
| Field shift positions for multi-bit MS fields. More... | |
| enum | ra8_vin_ms_fbs_t : uint8_t { k_ra8_vin_fbs_mb1 = 0U , k_ra8_vin_fbs_mb2 = 1U , k_ra8_vin_fbs_mb3 = 2U , k_ra8_vin_fbs_invalid = 3U } |
| Decoded values of MS.FBS / MS.FMS. More... | |
| enum | ra8_vin_int_mask_t : uint32_t { k_ra8_vin_int_fos = 0x00000001UL , k_ra8_vin_int_eof = 0x00000002UL , k_ra8_vin_int_scanline = 0x00000004UL , k_ra8_vin_int_field = 0x00000010UL , k_ra8_vin_int_fme = 0x00000020UL , k_ra8_vin_int_prcliph = 0x00000100UL , k_ra8_vin_int_prclipv = 0x00000200UL , k_ra8_vin_int_resp_ovf = 0x00004000UL , k_ra8_vin_int_axi_err = 0x00008000UL , k_ra8_vin_int_vsync_d = 0x00010000UL , k_ra8_vin_int_vsync_a = 0x00020000UL , k_ra8_vin_int_field2 = 0x80000000UL } |
| Bit masks for the IE (Interrupt Enable) and INTS (Interrupt Status) registers. More... | |
| enum | ra8_vin_int_w1c_mask_t : uint32_t { k_ra8_vin_int_w1c_mask = 0x80008001UL } |
| Subset of INTS bits that are write-1-to-clear. More... | |
| enum | ra8_vin_int_all_mask_t : uint32_t { k_ra8_vin_int_all_mask = 0x8003C737UL } |
| Union of every documented IE/INTS bit (FOS through FIS2). More... | |
| enum | ra8_vin_mtcstop_mask_t : uint32_t { k_ra8_vin_mtcstop_req = 0x00000001UL , k_ra8_vin_mtcstop_ack = 0x00000002UL , k_ra8_vin_mtcstop_outstand = 0x003F0000UL } |
| Bit masks for the MTCSTOP (AXI transfer stop) register. More... | |
| enum | ra8_vin_mtcstop_shift_t : uint8_t { k_ra8_vin_mtcstop_shift_outstand = 16U } |
| Field shift positions for MTCSTOP. More... | |
| enum | ra8_vin_dmr_mask_t : uint32_t { k_ra8_vin_dmr_dtmd = 0x00000003UL , k_ra8_vin_dmr_abit = 0x00000004UL , k_ra8_vin_dmr_bpsm = 0x00000010UL , k_ra8_vin_dmr_exrgb = 0x00000100UL , k_ra8_vin_dmr_yc_thr = 0x00000800UL , k_ra8_vin_dmr_ymode = 0x00007000UL , k_ra8_vin_dmr_a8bit = 0xFF000000UL } |
| Bit masks for the DMR (Data Mode) register. More... | |
| enum | ra8_vin_dmr_shift_t : uint8_t { k_ra8_vin_dmr_shift_dtmd = 0U , k_ra8_vin_dmr_shift_ymode = 12U , k_ra8_vin_dmr_shift_a8bit = 24U } |
| Field shift positions for DMR. More... | |
| enum | ra8_vin_csi_ifmd_mask_t : uint32_t { k_ra8_vin_csi_ifmd_vc_sel = 0x0000000FUL , k_ra8_vin_csi_ifmd_dt = 0x00003F00UL , k_ra8_vin_csi_ifmd_des0 = 0x02000000UL } |
| Bit masks for the CSI_IFMD (CSI-2 Interface Mode) register. More... | |
| enum | ra8_vin_csi_ifmd_shift_t : uint8_t { k_ra8_vin_csi_ifmd_shift_vc_sel = 0U , k_ra8_vin_csi_ifmd_shift_dt = 8U } |
| Field shift positions for CSI_IFMD. More... | |
| enum | ra8_vin_csifld_mask_t : uint32_t { k_ra8_vin_csifld_fld_en = 0x00000001UL , k_ra8_vin_csifld_fld_sel = 0x00000030UL , k_ra8_vin_csifld_fld_num = 0x00010000UL } |
| Bit masks for the CSIFLD (Field Detect Control) register. More... | |
| enum | ra8_vin_csifld_shift_t : uint8_t { k_ra8_vin_csifld_shift_fld_sel = 4U } |
| Field shift positions for CSIFLD. More... | |
| enum | ra8_vin_field_mask_t : uint32_t { k_ra8_vin_preclip_mask = 0x00000FFFUL } |
| Bit masks for SLPRC / ELPRC / SPPRC / EPPRC pre-clip registers. More... | |
| enum | ra8_vin_is_mask_t : uint32_t { k_ra8_vin_is_mask = 0x00001FFFUL } |
| Bit masks for the IS (Image Stride) register. More... | |
| enum | ra8_vin_lc_mask_t : uint32_t { k_ra8_vin_lc_mask = 0x00000FFFUL } |
| Bit masks for the LC (Line Count) register. More... | |
| enum | ra8_vin_si_mask_t : uint32_t { k_ra8_vin_si_mask = 0x00000FFFUL } |
| Bit masks for the SI (Scanline Interrupt) register. More... | |
| enum | ra8_vin_mb_addr_mask_t : uint32_t { k_ra8_vin_mb_addr_mask = 0xFFFFFF80UL , k_ra8_vin_mb_align_mask = 0x0000007FUL } |
| Bit masks for the MB1/MB2/MB3 frame-buffer base registers. More... | |
| enum | ra8_vin_uvaof_mask_t : uint32_t { k_ra8_vin_uvaof_mask = 0xFFFFFF80UL } |
| Bit masks for the UVAOF (UV Address Offset) register. More... | |
| enum | ra8_vin_uds_ctrl_mask_t : uint32_t { k_ra8_vin_uds_ctrl_ne_bcb = 0x00010000UL , k_ra8_vin_uds_ctrl_ne_gy = 0x00020000UL , k_ra8_vin_uds_ctrl_ne_rcr = 0x00040000UL , k_ra8_vin_uds_ctrl_bc = 0x00100000UL , k_ra8_vin_uds_ctrl_bladv = 0x10000000UL , k_ra8_vin_uds_ctrl_amd = 0x40000000UL } |
| Bit masks for the UDS_CTRL register. More... | |
| enum | ra8_vin_uds_scale_mask_t : uint32_t { k_ra8_vin_uds_scale_vfrac = 0x00000FFFUL , k_ra8_vin_uds_scale_vmant = 0x0000F000UL , k_ra8_vin_uds_scale_hfrac = 0x0FFF0000UL , k_ra8_vin_uds_scale_hmant = 0xF0000000UL } |
| Bit masks for the UDS_SCALE register. More... | |
| enum | ra8_vin_uds_scale_shift_t : uint8_t { k_ra8_vin_uds_scale_shift_vfrac = 0U , k_ra8_vin_uds_scale_shift_vmant = 12U , k_ra8_vin_uds_scale_shift_hfrac = 16U , k_ra8_vin_uds_scale_shift_hmant = 28U } |
| Field shift positions for UDS_SCALE. More... | |
| enum | ra8_vin_uds_bwidth_mask_t : uint32_t { k_ra8_vin_uds_bwidth_v = 0x0000007FUL , k_ra8_vin_uds_bwidth_h = 0x007F0000UL } |
| Bit masks for the UDS_PASS_BWIDTH register. More... | |
| enum | ra8_vin_uds_bwidth_shift_t : uint8_t { k_ra8_vin_uds_bwidth_shift_v = 0U , k_ra8_vin_uds_bwidth_shift_h = 16U } |
| Field shift positions for UDS_PASS_BWIDTH. More... | |
| enum | ra8_vin_uds_clip_size_mask_t : uint32_t { k_ra8_vin_uds_clip_v = 0x00000FFFUL , k_ra8_vin_uds_clip_h = 0x0FFF0000UL } |
| Bit masks for the UDS_CLIP_SIZE register. More... | |
| enum | ra8_vin_uds_clip_shift_t : uint8_t { k_ra8_vin_uds_clip_shift_v = 0U , k_ra8_vin_uds_clip_shift_h = 16U } |
| Field shift positions for UDS_CLIP_SIZE. More... | |
| enum | ra8_vin_lutp_mask_t : uint32_t { k_ra8_vin_lutp_ltcrpr = 0x000003FFUL , k_ra8_vin_lutp_ltcbpr = 0x000FFC00UL , k_ra8_vin_lutp_ltypr = 0x3FF00000UL } |
| Bit masks for the LUTP (LUT Pointer) register. More... | |
| enum | ra8_vin_lutp_shift_t : uint8_t { k_ra8_vin_lutp_shift_ltcrpr = 0U , k_ra8_vin_lutp_shift_ltcbpr = 10U , k_ra8_vin_lutp_shift_ltypr = 20U } |
| Field shift positions for LUTP. More... | |
| enum | ra8_vin_lutd_mask_t : uint32_t { k_ra8_vin_lutd_ltcrdt = 0x000000FFUL , k_ra8_vin_lutd_ltcbdt = 0x0000FF00UL , k_ra8_vin_lutd_ltydt = 0x00FF0000UL } |
| Bit masks for the LUTD (LUT Data) register. More... | |
| enum | ra8_vin_lutd_shift_t : uint8_t { k_ra8_vin_lutd_shift_ltcrdt = 0U , k_ra8_vin_lutd_shift_ltcbdt = 8U , k_ra8_vin_lutd_shift_ltydt = 16U } |
| Field shift positions for LUTD. More... | |
| enum | ra8_vin_yccr_mask_t : uint32_t { k_ra8_vin_yc1_rp = 0x00001FFFUL , k_ra8_vin_yc2_gp = 0x00001FFFUL , k_ra8_vin_yc2_bp = 0x1FFF0000UL , k_ra8_vin_yc3_ap = 0x00000FFFUL , k_ra8_vin_yc3_hen = 0x00800000UL , k_ra8_vin_yc3_sft = 0x1F000000UL } |
| Bit masks for the RGB-to-YUV coefficient registers. More... | |
| enum | ra8_vin_yccr_shift_t : uint8_t { k_ra8_vin_yccr_shift_rp = 0U , k_ra8_vin_yccr_shift_gp = 0U , k_ra8_vin_yccr_shift_bp = 16U , k_ra8_vin_yccr_shift_ap = 0U , k_ra8_vin_yccr_shift_sft = 24U } |
| Field shift positions for the RGB-to-YUV coefficient registers. More... | |
| enum | ra8_vin_csce1_mask_t : uint32_t { k_ra8_vin_csce1_ymul2 = 0x00003FFFUL , k_ra8_vin_csce1_round = 0x00010000UL } |
| Bit masks for the CSCE1 (YC-to-RGB Y multiply) register. More... | |
| enum | ra8_vin_csce2_mask_t : uint32_t { k_ra8_vin_csce2_csub2 = 0x00000FFFUL , k_ra8_vin_csce2_ysub2 = 0x0FFF0000UL } |
| Bit masks for the CSCE2 (YC-to-RGB subtract) register. More... | |
| enum | ra8_vin_csce2_shift_t : uint8_t { k_ra8_vin_csce2_shift_ysub2 = 16U } |
| Field shift positions for CSCE2. More... | |
| enum | ra8_vin_csce34_mask_t : uint32_t { k_ra8_vin_csce_mul_lo = 0x00003FFFUL , k_ra8_vin_csce_mul_hi = 0x3FFF0000UL } |
| Bit masks for the CSCE3 / CSCE4 multiply-pair registers. More... | |
| enum | ra8_vin_csce_shift_t : uint8_t { k_ra8_vin_csce_shift_mul_hi = 16U } |
| Field shift positions for CSCE3 / CSCE4. More... | |
| enum | ra8_vin_lut_t : uint16_t { k_ra8_vin_lut_entries = 256U } |
| LUT geometry constants. More... | |
| enum | ra8_vin_st_settle_t : uint8_t { k_ra8_vin_st_settle_reads = 10U } |
| Number of MC.ST read-back cycles required before MC.ME = 1. More... | |
| enum | ra8_vin_stop_drain_t : uint16_t { k_ra8_vin_stop_drain_max = 1024U } |
| Number of MTCSTOP poll iterations before declaring timeout. More... | |
| enum | ra8_vin_im_value_t : uint8_t { k_ra8_vin_im_odd_only = 0U , k_ra8_vin_im_odd_even = 1U , k_ra8_vin_im_even_only = 2U } |
| Decoded values of MC.IM (Interlace Mode field). More... | |
| enum | ra8_vin_dc_value_t : uint8_t { k_ra8_vin_dc_addition = 0U , k_ra8_vin_dc_ordered_1 = 1U , k_ra8_vin_dc_ordered_2 = 2U } |
| Decoded values of MC.DC (Dithering Mode field). More... | |
| enum | ra8_vin_clp_value_t : uint8_t { k_ra8_vin_clp_default = 0U , k_ra8_vin_clp_nibble = 1U , k_ra8_vin_clp_disabled = 3U } |
| Decoded values of MC.CLP (Pixel data clipping field). More... | |
| enum | ra8_vin_dtmd_value_t : uint8_t { k_ra8_vin_dtmd_none = 0U , k_ra8_vin_dtmd_rgb_to_argb = 1U , k_ra8_vin_dtmd_yc_separated = 2U } |
| Decoded values of DMR.DTMD (Data conversion mode). More... | |
| enum | ra8_vin_ymode_value_t : uint8_t { k_ra8_vin_ymode_y_cbcr = 0U , k_ra8_vin_ymode_y_only = 1U , k_ra8_vin_ymode_y10_cbcr = 2U , k_ra8_vin_ymode_y10_only = 3U } |
| Decoded values of DMR.YMODE (YC transfer mode). More... | |
| enum | ra8_vin_yuv444_value_t : uint8_t { k_ra8_vin_yuv444_data_extend = 0U , k_ra8_vin_yuv444_interpolate = 1U } |
| Decoded values of MC.YUV444 (YUV-444 conversion). More... | |
| enum | ra8_vin_uds_interp_value_t : uint8_t { k_ra8_vin_uds_bilinear = 0U , k_ra8_vin_uds_nearest = 1U } |
| Decoded values for the UDS_CTRL NE_* / BC interpolation flags. More... | |
| enum | ra8_vin_csi_dt_value_t : uint8_t { k_ra8_vin_csi_dt_yuv422_8 = 0x1EU , k_ra8_vin_csi_dt_yuv422_10 = 0x1FU , k_ra8_vin_csi_dt_rgb888 = 0x24U , k_ra8_vin_csi_dt_raw8 = 0x2AU } |
| Common values for the CSI_IFMD.DT field. More... | |
| enum | ra8_vin_field_polarity_t : uint8_t { k_ra8_vin_field_even_is_zero = 0U , k_ra8_vin_field_even_is_one = 1U } |
| Decoded values for the CSIFLD.FLD_NUM bit. More... | |
| enum | ra8_vin_lut_geometry_t : uint16_t { k_ra8_vin_lut_max_pointer = 0x3FFU , k_ra8_vin_lut_max_byte = 0xFFU } |
| Geometric / range constants for the LUT plane. More... | |
| enum | ra8_vin_uds_scale_geometry_t : uint16_t { k_ra8_vin_uds_max_mant = 0xFU , k_ra8_vin_uds_max_frac = 0xFFFU , k_ra8_vin_uds_max_clip = 0xFFFU , k_ra8_vin_uds_max_bw = 0x7FU } |
| Range / step limits for UDS scaling factor and clipping. More... | |
| enum | ra8_vin_yccr_init_t : uint32_t { k_ra8_vin_yccr_y_setting1_init = 0x00000000UL , k_ra8_vin_yccr_y_setting2_init = 0x00000000UL , k_ra8_vin_yccr_y_setting3_init = 0x00800000UL , k_ra8_vin_csce1_init = 0x0001129FUL , k_ra8_vin_csce2_init = 0x01000800UL } |
| Reset / suggested-initial values for YCCRn / CBCCRn / CRCCRn. More... | |
Functions | |
| static volatile uint32_t * | ra8_vin_reg32 (ra8_vin_off_t off) |
| Pointer to a 32-bit register inside the VIN block. | |
Video Input Module (VIN) register layout for the RA8D2.
The Video Input Module sits at the AXI/PCLKA boundary between the MIPI CSI-2 receiver and SDRAM. It receives image data from the camera, applies optional pre-clip / colour-space / scaling / dither conversions, and writes the resulting frames into one of three memory-base buffers (MB1, MB2, MB3) for consumption by GLCDC, DRW2D, or DMA.
On the RA8D2 there is a single VIN0 instance at base 0x40347400. All registers are 32-bit-only access (HUM Ch 67.2 "Register Description" p 3974, "Access the following registers only in units of 32 bits"). The driver exposes a typed-enum offset table plus an inline accessor that returns a volatile uint32_t* so the host-side ra8_fake_mmap shim can intercept every read/write.
| Offset | Name | Purpose |
|---|---|---|
| 0x000 | MC | Main control |
| 0x004 | MS | Module status (R) |
| 0x008 | FC | Frame capture |
| 0x00C | SLPRC | Pre-clip start line |
| 0x010 | ELPRC | Pre-clip end line |
| 0x014 | SPPRC | Pre-clip start pixel |
| 0x018 | EPPRC | Pre-clip end pixel |
| 0x020 | CSI_IFMD | CSI-2 interface mode |
| 0x024 | CSIFLD | Field detect control |
| 0x02C | IS | Image stride |
| 0x030 | MB1 | Memory base 1 (frame buffer 1 address) |
| 0x034 | MB2 | Memory base 2 (frame buffer 2 address) |
| 0x038 | MB3 | Memory base 3 (frame buffer 3 address) |
| 0x03C | LC | Line count (R) |
| 0x040 | IE | Interrupt enable |
| 0x044 | INTS | Interrupt status (W1C subset) |
| 0x048 | SI | Scanline interrupt compare |
| 0x054 | MTCSTOP | AXI transfer stop control |
| 0x058 | DMR | Data mode register |
| 0x060 | UVAOF | UV data address offset |
| 0x080 | UDS_CTRL | UDS scaling interpolation control |
| 0x084 | UDS_SCALE | UDS scaling factors (V/H mantissa+frac) |
| 0x090 | UDS_PASS_BWIDTH | UDS passband filter bandwidth |
| 0x0A4 | UDS_CLIP_SIZE | UDS output clipping size |
| 0x100 | LUTP | LUT pointer (Y/Cb/Cr) |
| 0x104 | LUTD | LUT data (Y/Cb/Cr) |
| 0x228 | YCCR1 | RGB-to-Y coefficient R |
| 0x22C | YCCR2 | RGB-to-Y coefficient G+B |
| 0x230 | YCCR3 | RGB-to-Y normalisation/shift |
| 0x234 | CBCCR1 | RGB-to-Cb coefficient R |
| 0x238 | CBCCR2 | RGB-to-Cb coefficient G+B |
| 0x23C | CBCCR3 | RGB-to-Cb normalisation/shift |
| 0x240 | CRCCR1 | RGB-to-Cr coefficient R |
| 0x244 | CRCCR2 | RGB-to-Cr coefficient G+B |
| 0x248 | CRCCR3 | RGB-to-Cr normalisation/shift |
| 0x300 | CSCE1 | YC-to-RGB Y multiplication |
| 0x304 | CSCE2 | YC-to-RGB Y/CbCr subtraction |
| 0x308 | CSCE3 | YC-to-RGB Cr multiplication |
| 0x30C | CSCE4 | YC-to-RGB Cb multiplication |
Total window size: 0x310 bytes (HUM Ch 67.2 "Register Description" p 3974, FSP R_VIN_Type size = 0x310).
Definition in file ra8_vin_regs.h.
| enum ra8_vin_addr_t : uintptr_t |
Memory-mapped base addresses for the VIN block.
VIN0 is the only instance on the RA8D2 package. The non-secure alias VIN0_NS lives at 0x50347400 but the driver only uses the secure base for now.
| Enumerator | |
|---|---|
| k_ra8_vin0_base_addr | VIN0 secure base (HUM Ch 67.2 p 3974). |
| k_ra8_vin0_ns_base_addr | VIN0 non-secure alias (HUM Ch 67.2 p 3974). |
Definition at line 91 of file ra8_vin_regs.h.
| enum ra8_vin_clp_value_t : uint8_t |
Decoded values of MC.CLP (Pixel data clipping field).
HUM Ch 67.2.1 p 3975. CLP[29:28] truncates the input pixel sample before downstream processing.
| Enumerator | |
|---|---|
| k_ra8_vin_clp_default | 00 – default clipping mode. |
| k_ra8_vin_clp_nibble | 01 – lower 4-bit clipping mode. |
| k_ra8_vin_clp_disabled | 11 – clipping disabled (pass through). |
Definition at line 779 of file ra8_vin_regs.h.
| enum ra8_vin_csce1_mask_t : uint32_t |
Bit masks for the CSCE1 (YC-to-RGB Y multiply) register.
HUM Ch 67.2.36 "CSCE1" p 3995 (numbering note: CSCE bank lives at offset 0x300 even though section number is 67.2.36). YMUL2 is a 14-bit unsigned multiplier (initial value 1.164 = 4767 / 4096); ROUND enables rounding of the result.
| Enumerator | |
|---|---|
| k_ra8_vin_csce1_ymul2 | YMUL2 [13:0]. |
| k_ra8_vin_csce1_round | ROUND [16]. |
Definition at line 652 of file ra8_vin_regs.h.
| enum ra8_vin_csce2_mask_t : uint32_t |
Bit masks for the CSCE2 (YC-to-RGB subtract) register.
HUM Ch 67.2.37 "CSCE2" p 3995. CSUB2 must remain at the reset value (2048 = 0x800); YSUB2 carries the Y subtraction term (initial value 256 = 0x100).
| Enumerator | |
|---|---|
| k_ra8_vin_csce2_csub2 | CSUB2 [11:0]. |
| k_ra8_vin_csce2_ysub2 | YSUB2 [27:16]. |
Definition at line 666 of file ra8_vin_regs.h.
| enum ra8_vin_csce2_shift_t : uint8_t |
Field shift positions for CSCE2.
| Enumerator | |
|---|---|
| k_ra8_vin_csce2_shift_ysub2 | YSUB2[27:16] shift. |
Definition at line 675 of file ra8_vin_regs.h.
| enum ra8_vin_csce34_mask_t : uint32_t |
Bit masks for the CSCE3 / CSCE4 multiply-pair registers.
HUM Ch 67.2.38 "CSCE3" and 67.2.39 "CSCE4". Each carries two unsigned 14-bit multiplier coefficients packed low/high.
| Enumerator | |
|---|---|
| k_ra8_vin_csce_mul_lo | Low multiplier [13:0]. |
| k_ra8_vin_csce_mul_hi | High multiplier [29:16]. |
Definition at line 687 of file ra8_vin_regs.h.
| enum ra8_vin_csce_shift_t : uint8_t |
Field shift positions for CSCE3 / CSCE4.
| Enumerator | |
|---|---|
| k_ra8_vin_csce_shift_mul_hi | High multiplier shift. |
Definition at line 696 of file ra8_vin_regs.h.
| enum ra8_vin_csi_dt_value_t : uint8_t |
Common values for the CSI_IFMD.DT field.
HUM Ch 67.2.8 p 3982. Mirrors the MIPI CSI-2 short-packet data type values used by the camera; the driver does not validate that the chosen DT matches MC.INF (the user is expected to keep them coherent).
| Enumerator | |
|---|---|
| k_ra8_vin_csi_dt_yuv422_8 | YUV 4:2:2 8-bit. |
| k_ra8_vin_csi_dt_yuv422_10 | YUV 4:2:2 10-bit. |
| k_ra8_vin_csi_dt_rgb888 | RGB-888. |
| k_ra8_vin_csi_dt_raw8 | RAW-8. |
Definition at line 851 of file ra8_vin_regs.h.
| enum ra8_vin_csi_ifmd_mask_t : uint32_t |
Bit masks for the CSI_IFMD (CSI-2 Interface Mode) register.
HUM Ch 67.2.8 "CSI_IFMD : CSI2 Interface Mode Register" p 3982. VC_SEL picks the virtual channel; DT picks the data type; DES0 controls sign-extend (0) vs zero-extend (1).
| Enumerator | |
|---|---|
| k_ra8_vin_csi_ifmd_vc_sel | VC_SEL [3:0] Virtual channel. |
| k_ra8_vin_csi_ifmd_dt | DT [13:8] Data type. |
| k_ra8_vin_csi_ifmd_des0 | DES0 [25] Data extension. |
Definition at line 362 of file ra8_vin_regs.h.
| enum ra8_vin_csi_ifmd_shift_t : uint8_t |
Field shift positions for CSI_IFMD.
| Enumerator | |
|---|---|
| k_ra8_vin_csi_ifmd_shift_vc_sel | VC_SEL[3:0] shift. |
| k_ra8_vin_csi_ifmd_shift_dt | DT[13:8] shift. |
Definition at line 372 of file ra8_vin_regs.h.
| enum ra8_vin_csifld_mask_t : uint32_t |
Bit masks for the CSIFLD (Field Detect Control) register.
HUM Ch 67.2.9 "CSIFLD : Field Detection Control Register" p 3983.
| Enumerator | |
|---|---|
| k_ra8_vin_csifld_fld_en | FLD_EN [0] Field detect. |
| k_ra8_vin_csifld_fld_sel | FLD_SEL [5:4] Even-field select. |
| k_ra8_vin_csifld_fld_num | FLD_NUM [16] Even-field number. |
Definition at line 384 of file ra8_vin_regs.h.
| enum ra8_vin_csifld_shift_t : uint8_t |
Field shift positions for CSIFLD.
| Enumerator | |
|---|---|
| k_ra8_vin_csifld_shift_fld_sel | FLD_SEL[5:4] shift. |
Definition at line 394 of file ra8_vin_regs.h.
| enum ra8_vin_dc_value_t : uint8_t |
Decoded values of MC.DC (Dithering Mode field).
HUM Ch 67.2.1 p 3975. DC[15:14] selects between cumulative addition and one of two ordered-dither patterns; the DC2 bit (separate, see k_ra8_vin_mc_dc2) flips the direction of the ordered patterns.
| Enumerator | |
|---|---|
| k_ra8_vin_dc_addition | 00 – dithering with cumulative addition. |
| k_ra8_vin_dc_ordered_1 | 01 – ordered dithering pattern 1. |
| k_ra8_vin_dc_ordered_2 | 10 – ordered dithering pattern 2. |
Definition at line 765 of file ra8_vin_regs.h.
| enum ra8_vin_dmr_mask_t : uint32_t |
Bit masks for the DMR (Data Mode) register.
HUM Ch 67.2.19 "DMR : Data Mode Register" p 3992. Selects YC vs RGB output, alpha-bit value, byte-swap, RGB extension to 32 bits, YC through-mode, and the 8-bit alpha for ARGB-8888.
Definition at line 333 of file ra8_vin_regs.h.
| enum ra8_vin_dmr_shift_t : uint8_t |
Field shift positions for DMR.
| Enumerator | |
|---|---|
| k_ra8_vin_dmr_shift_dtmd | DTMD[1:0] shift. |
| k_ra8_vin_dmr_shift_ymode | YMODE[14:12] shift. |
| k_ra8_vin_dmr_shift_a8bit | A8BIT[31:24] shift. |
Definition at line 347 of file ra8_vin_regs.h.
| enum ra8_vin_dtmd_value_t : uint8_t |
Decoded values of DMR.DTMD (Data conversion mode).
HUM Ch 67.2.19 p 3992. Selects how the YC / RGB pipeline emits pixels into memory.
| Enumerator | |
|---|---|
| k_ra8_vin_dtmd_none | Pass-through (no conversion). |
| k_ra8_vin_dtmd_rgb_to_argb | RGB input rendered as ARGB. |
| k_ra8_vin_dtmd_yc_separated | Y/CbCr separated to two planes. |
Definition at line 793 of file ra8_vin_regs.h.
| enum ra8_vin_fc_mask_t : uint32_t |
Bit masks for the FC (Frame Capture) register.
HUM Ch 67.2.3 "FC : Frame Capture Register" p 3979. CC at bit 1 selects continuous (rolling MB1->MB2->MB3->...) capture mode.
| Enumerator | |
|---|---|
| k_ra8_vin_fc_cc | CC [1] Continuous frame capture mode. |
Definition at line 195 of file ra8_vin_regs.h.
| enum ra8_vin_field_mask_t : uint32_t |
Bit masks for SLPRC / ELPRC / SPPRC / EPPRC pre-clip registers.
HUM Ch 67.2.4..67.2.7 p 3980-3981. All four registers carry one 12-bit pixel/line index (max 4095).
| Enumerator | |
|---|---|
| k_ra8_vin_preclip_mask | 12-bit pre-clip count. |
Definition at line 406 of file ra8_vin_regs.h.
| enum ra8_vin_field_polarity_t : uint8_t |
Decoded values for the CSIFLD.FLD_NUM bit.
HUM Ch 67.2.9 p 3983. Picks which field-number ordering counts as the "even" field for interlaced capture.
| Enumerator | |
|---|---|
| k_ra8_vin_field_even_is_zero | field-number 0 -> even. |
| k_ra8_vin_field_even_is_one | field-number 1 -> even. |
Definition at line 866 of file ra8_vin_regs.h.
| enum ra8_vin_im_value_t : uint8_t |
Decoded values of MC.IM (Interlace Mode field).
HUM Ch 67.2.1 p 3975. The IM field [4:3] selects which incoming field(s) are written to memory. Encodings match Table 67.4 "Interlace Mode" in the manual.
| Enumerator | |
|---|---|
| k_ra8_vin_im_odd_only | 00 – odd-field (field 1) capture. |
| k_ra8_vin_im_odd_even | 01 – both odd and even fields captured. |
| k_ra8_vin_im_even_only | 10 – even-field only capture. |
Definition at line 750 of file ra8_vin_regs.h.
| enum ra8_vin_int_all_mask_t : uint32_t |
Union of every documented IE/INTS bit (FOS through FIS2).
Used by ra8_vin_get_status and the deinit path to reason about the full surface without hard-coding repeated OR expressions.
| Enumerator | |
|---|---|
| k_ra8_vin_int_all_mask | All defined IE/INTS bits. |
Definition at line 296 of file ra8_vin_regs.h.
| enum ra8_vin_int_mask_t : uint32_t |
Bit masks for the IE (Interrupt Enable) and INTS (Interrupt Status) registers.
Both registers share an identical bit layout. Status bits FOS, ARES and FIS2 are W1C; the remaining bits are state and are cleared by the hardware when their condition resolves. See HUM Ch 67.2.15 "IE" p 3987 and HUM Ch 67.2.16 "INTS" p 3989.
Naming uses INTS-side names for the status bits and the same positions for IE so a single mask works for both registers.
Definition at line 258 of file ra8_vin_regs.h.
| enum ra8_vin_int_w1c_mask_t : uint32_t |
Subset of INTS bits that are write-1-to-clear.
From HUM Ch 67.2.16 "INTS" p 3989 the bits FOS [0], ARES [15] and FIS2 [31] are described as "After being set to 1, this bit is cleared to 0 by writing 1." Other bits track hardware state and ignore writes. The driver writes this mask back to INTS at the end of an interrupt to clear the latched conditions.
| Enumerator | |
|---|---|
| k_ra8_vin_int_w1c_mask | FOS | ARES | FIS2. |
Definition at line 284 of file ra8_vin_regs.h.
| enum ra8_vin_is_mask_t : uint32_t |
Bit masks for the IS (Image Stride) register.
HUM Ch 67.2.13 "IS : Image Stride Register" p 3984. 13-bit field (max 8191 pixels per line).
| Enumerator | |
|---|---|
| k_ra8_vin_is_mask | IS[12:0] image stride in pixels. |
Definition at line 418 of file ra8_vin_regs.h.
| enum ra8_vin_lc_mask_t : uint32_t |
Bit masks for the LC (Line Count) register.
HUM Ch 67.2.14 "LC : Line Count Register" p 3987. Read-only count of received scanlines (0..4095), updated every line.
| Enumerator | |
|---|---|
| k_ra8_vin_lc_mask | LC[11:0] line count. |
Definition at line 430 of file ra8_vin_regs.h.
| enum ra8_vin_lut_geometry_t : uint16_t |
Geometric / range constants for the LUT plane.
HUM Ch 67.2.25 p 4000 / 67.2.26 p 4001. Each LUT byte is 8-bit unsigned and the pointer field is 10-bit (0..1023) but only indices 0..255 select real entries.
| Enumerator | |
|---|---|
| k_ra8_vin_lut_max_pointer | LUTP pointer field width. |
| k_ra8_vin_lut_max_byte | LUTD byte field width. |
Definition at line 880 of file ra8_vin_regs.h.
| enum ra8_vin_lut_t : uint16_t |
LUT geometry constants.
HUM Ch 67.2.25 "LUTP" p 4000. The LUT has 256 entries (0..255); each LUTD write requires a matching LUTP pointer update.
| Enumerator | |
|---|---|
| k_ra8_vin_lut_entries | LUT entry count for Y, Cb, and Cr. |
Definition at line 708 of file ra8_vin_regs.h.
| enum ra8_vin_lutd_mask_t : uint32_t |
Bit masks for the LUTD (LUT Data) register.
HUM Ch 67.2.26 "LUTD : Look Up Table Data Register" p 4001. Three 8-bit values written into the LUT entry pointed to by LUTP. The driver writes 256 entries by stepping LTYPR / LTCBPR / LTCRPR.
| Enumerator | |
|---|---|
| k_ra8_vin_lutd_ltcrdt | LTCRDT [7:0] Cr data byte. |
| k_ra8_vin_lutd_ltcbdt | LTCBDT [15:8] Cb data byte. |
| k_ra8_vin_lutd_ltydt | LTYDT [23:16] Y data byte. |
Definition at line 595 of file ra8_vin_regs.h.
| enum ra8_vin_lutd_shift_t : uint8_t |
Field shift positions for LUTD.
| Enumerator | |
|---|---|
| k_ra8_vin_lutd_shift_ltcrdt | Cr data byte shift. |
| k_ra8_vin_lutd_shift_ltcbdt | Cb data byte shift. |
| k_ra8_vin_lutd_shift_ltydt | Y data byte shift. |
Definition at line 605 of file ra8_vin_regs.h.
| enum ra8_vin_lutp_mask_t : uint32_t |
Bit masks for the LUTP (LUT Pointer) register.
HUM Ch 67.2.25 "LUTP : Look Up Table Pointer Register" p 4000. Three 10-bit pointers (Y / Cb / Cr) into the 256-entry LUT used to convert 10-bit input to 8-bit output samples.
| Enumerator | |
|---|---|
| k_ra8_vin_lutp_ltcrpr | LTCRPR [9:0] Cr pointer. |
| k_ra8_vin_lutp_ltcbpr | LTCBPR [19:10] Cb pointer. |
| k_ra8_vin_lutp_ltypr | LTYPR [29:20] Y pointer. |
Definition at line 570 of file ra8_vin_regs.h.
| enum ra8_vin_lutp_shift_t : uint8_t |
Field shift positions for LUTP.
| Enumerator | |
|---|---|
| k_ra8_vin_lutp_shift_ltcrpr | Cr pointer shift. |
| k_ra8_vin_lutp_shift_ltcbpr | Cb pointer shift. |
| k_ra8_vin_lutp_shift_ltypr | Y pointer shift. |
Definition at line 580 of file ra8_vin_regs.h.
| enum ra8_vin_mb_addr_mask_t : uint32_t |
Bit masks for the MB1/MB2/MB3 frame-buffer base registers.
HUM Ch 67.2.10..67.2.12 p 3985-3987. Lower 7 bits are reserved (zero) which forces 64-byte alignment for the frame buffer.
| Enumerator | |
|---|---|
| k_ra8_vin_mb_addr_mask | MBn[31:7] base address. |
| k_ra8_vin_mb_align_mask | Reserved low bits (must be zero). |
Definition at line 454 of file ra8_vin_regs.h.
| enum ra8_vin_mc_mask_t : uint32_t |
Bit masks for the MC (Main Control) register.
Layout from HUM Ch 67.2.1 "MC : Main Control Register" p 3975. ME is the main enable; ST is a write-only "init at startup" pulse; SCLE turns on the UDS scaler.
Definition at line 157 of file ra8_vin_regs.h.
| enum ra8_vin_mc_shift_t : uint8_t |
Field shift positions for multi-bit MC fields.
HUM Ch 67.2.1 p 3975. Used to compose multi-bit fields without scattered magic numbers.
| Enumerator | |
|---|---|
| k_ra8_vin_mc_shift_im | IM[4:3] shift. |
| k_ra8_vin_mc_shift_dc | DC[15:14] shift. |
| k_ra8_vin_mc_shift_inf | INF[18:16] shift. |
| k_ra8_vin_mc_shift_clp | CLP[29:28] shift. |
Definition at line 180 of file ra8_vin_regs.h.
| enum ra8_vin_ms_fbs_t : uint8_t |
Decoded values of MS.FBS / MS.FMS.
HUM Ch 67.2.2 p 3978: 0..2 select the corresponding MBn buffer, 3 means "no valid frame buffer / invalid".
| Enumerator | |
|---|---|
| k_ra8_vin_fbs_mb1 | Latest frame in MB1. |
| k_ra8_vin_fbs_mb2 | Latest frame in MB2. |
| k_ra8_vin_fbs_mb3 | Latest frame in MB3. |
| k_ra8_vin_fbs_invalid | No valid frame buffer. |
Definition at line 237 of file ra8_vin_regs.h.
| enum ra8_vin_ms_mask_t : uint32_t |
Bit masks for the MS (Module Status) register.
HUM Ch 67.2.2 "MS : Module Status Register" p 3978. CA / MA indicate active capture; FBS / FMS report which MBn buffer the latest valid frame landed in.
Definition at line 208 of file ra8_vin_regs.h.
| enum ra8_vin_ms_shift_t : uint8_t |
Field shift positions for multi-bit MS fields.
HUM Ch 67.2.2 p 3978.
| Enumerator | |
|---|---|
| k_ra8_vin_ms_shift_fbs | FBS[4:3] shift. |
| k_ra8_vin_ms_shift_fms | FMS[20:19] shift. |
Definition at line 224 of file ra8_vin_regs.h.
| enum ra8_vin_mtcstop_mask_t : uint32_t |
Bit masks for the MTCSTOP (AXI transfer stop) register.
HUM Ch 67.2.18 "MTCSTOP : AXI Transfer Stop Control Register" p 3991. Setting STOPREQ blocks new AXI requests; STOPACK reads back 1 once outstanding responses have drained. OUTSTAND[5:0] reports the in-flight request count.
| Enumerator | |
|---|---|
| k_ra8_vin_mtcstop_req | STOPREQ [0]. |
| k_ra8_vin_mtcstop_ack | STOPACK [1] (R). |
| k_ra8_vin_mtcstop_outstand | OUTSTAND[21:16] (R). |
Definition at line 310 of file ra8_vin_regs.h.
| enum ra8_vin_mtcstop_shift_t : uint8_t |
Field shift positions for MTCSTOP.
| Enumerator | |
|---|---|
| k_ra8_vin_mtcstop_shift_outstand | OUTSTAND[21:16] shift. |
Definition at line 320 of file ra8_vin_regs.h.
| enum ra8_vin_off_t : uint16_t |
32-bit register offsets inside the VIN window.
Names mirror FSP's R_VIN_Type field names so a reader can cross-reference directly. Offsets verified against FSP R_VIN_Type in R7KA8D2KF_core0.h lines 18682-19248 and against HUM Ch 67.2 register tables p 3974-4003.
Definition at line 106 of file ra8_vin_regs.h.
| enum ra8_vin_si_mask_t : uint32_t |
Bit masks for the SI (Scanline Interrupt) register.
HUM Ch 67.2.17 "SI : Scanline Interrupt Register" p 3990. 12-bit compare value; 0 disables the scanline interrupt.
| Enumerator | |
|---|---|
| k_ra8_vin_si_mask | SI[11:0] scanline match value. |
Definition at line 442 of file ra8_vin_regs.h.
| enum ra8_vin_st_settle_t : uint8_t |
Number of MC.ST read-back cycles required before MC.ME = 1.
FSP R_VIN_CaptureStart reads MC.ST ten times immediately after writing it, to absorb the "wait at least 10 cycles of aclk (ICLK)" requirement called out in HUM Ch 67.3.1 "Initialization Procedure" p 4015. The driver replays the same loop count.
| Enumerator | |
|---|---|
| k_ra8_vin_st_settle_reads | MC.ST settle read-backs. |
Definition at line 722 of file ra8_vin_regs.h.
| enum ra8_vin_stop_drain_t : uint16_t |
Number of MTCSTOP poll iterations before declaring timeout.
HUM Ch 67.3.6 "Stopping the capture operation" p 4022. There is no documented worst-case latency, but the FSP reference simply checks MTCSTOP.OUTSTAND once. The driver polls a bounded number of times (NASA Rule 2: every loop has a fixed upper bound) and reports k_ra8_err_hw_timeout if AXI traffic does not drain.
| Enumerator | |
|---|---|
| k_ra8_vin_stop_drain_max | Max OUTSTAND poll iterations. |
Definition at line 737 of file ra8_vin_regs.h.
| enum ra8_vin_uds_bwidth_mask_t : uint32_t |
Bit masks for the UDS_PASS_BWIDTH register.
HUM Ch 67.2.23 "UDS_PASS_BWIDTH : Passband Register" p 3998. 7-bit V and H passband bandwidths used by the UDS filter.
| Enumerator | |
|---|---|
| k_ra8_vin_uds_bwidth_v | BWIDTH_V [6:0]. |
| k_ra8_vin_uds_bwidth_h | BWIDTH_H [22:16]. |
Definition at line 525 of file ra8_vin_regs.h.
| enum ra8_vin_uds_bwidth_shift_t : uint8_t |
Field shift positions for UDS_PASS_BWIDTH.
| Enumerator | |
|---|---|
| k_ra8_vin_uds_bwidth_shift_v | BWIDTH_V[6:0] shift. |
| k_ra8_vin_uds_bwidth_shift_h | BWIDTH_H[22:16] shift. |
Definition at line 534 of file ra8_vin_regs.h.
| enum ra8_vin_uds_clip_shift_t : uint8_t |
Field shift positions for UDS_CLIP_SIZE.
| Enumerator | |
|---|---|
| k_ra8_vin_uds_clip_shift_v | CL_VSIZE shift. |
| k_ra8_vin_uds_clip_shift_h | CL_HSIZE shift. |
Definition at line 556 of file ra8_vin_regs.h.
| enum ra8_vin_uds_clip_size_mask_t : uint32_t |
Bit masks for the UDS_CLIP_SIZE register.
HUM Ch 67.2.24 "UDS_CLIP_SIZE : UDS Output Size Clipping Register" p 3999. 12-bit V and H clip sizes after scaling.
| Enumerator | |
|---|---|
| k_ra8_vin_uds_clip_v | CL_VSIZE [11:0] . |
| k_ra8_vin_uds_clip_h | CL_HSIZE [27:16]. |
Definition at line 547 of file ra8_vin_regs.h.
| enum ra8_vin_uds_ctrl_mask_t : uint32_t |
Bit masks for the UDS_CTRL register.
HUM Ch 67.2.21 "UDS_CTRL : UDS Scaling Control Register" p 3996. NE_BCB, NE_GY, NE_RCR pick bilinear (0) vs nearest neighbour (1) per channel; BC selects multi-tap mode; BLADV / AMD enable two advanced-mode tweaks for the bilinear/nearest filter.
Definition at line 481 of file ra8_vin_regs.h.
| enum ra8_vin_uds_interp_value_t : uint8_t |
Decoded values for the UDS_CTRL NE_* / BC interpolation flags.
HUM Ch 67.2.21 p 3996. Each NE_* bit picks bilinear (0) vs nearest neighbour (1) for one of the colour channels. BC picks bilinear vs multi-tap mode.
| Enumerator | |
|---|---|
| k_ra8_vin_uds_bilinear | Bilinear interpolation. |
| k_ra8_vin_uds_nearest | Nearest-neighbour interpolation. |
Definition at line 836 of file ra8_vin_regs.h.
| enum ra8_vin_uds_scale_geometry_t : uint16_t |
Range / step limits for UDS scaling factor and clipping.
HUM Ch 67.2.22 p 3997 / 67.2.24 p 3999. Mantissa is 4 bits, fraction is 12 bits, clip output is 12-bit pixel count.
Definition at line 893 of file ra8_vin_regs.h.
| enum ra8_vin_uds_scale_mask_t : uint32_t |
Bit masks for the UDS_SCALE register.
HUM Ch 67.2.22 "UDS_SCALE : Scaling Factor Register" p 3997. Each axis carries a 4-bit integer + 12-bit fractional multiplier (Q4.12 fixed-point scaling factor).
Definition at line 499 of file ra8_vin_regs.h.
| enum ra8_vin_uds_scale_shift_t : uint8_t |
Field shift positions for UDS_SCALE.
Definition at line 510 of file ra8_vin_regs.h.
| enum ra8_vin_uvaof_mask_t : uint32_t |
Bit masks for the UVAOF (UV Address Offset) register.
HUM Ch 67.2.20 "UVAOF : UV Address Offset Register" p 3994. Same 64-byte-aligned 25-bit field as the MBn registers.
| Enumerator | |
|---|---|
| k_ra8_vin_uvaof_mask | UVAOF[31:7] UV data offset. |
Definition at line 467 of file ra8_vin_regs.h.
| enum ra8_vin_yccr_init_t : uint32_t |
Reset / suggested-initial values for YCCRn / CBCCRn / CRCCRn.
HUM Ch 67.2.27..67.2.35 p 4002-4011. The driver does not force these values on init; they are exposed so the test harness can assert on the stock identity matrix.
Definition at line 909 of file ra8_vin_regs.h.
| enum ra8_vin_yccr_mask_t : uint32_t |
Bit masks for the RGB-to-YUV coefficient registers.
HUM Ch 67.2.27..67.2.35 p 4002-4011. Layout is identical for the three colour-component triples (YCCRn / CBCCRn / CRCCRn). Settings 1 carries the R coefficient; 2 carries G+B; 3 carries the additive offset, the rounding-enable, and the shift-down volume.
Definition at line 621 of file ra8_vin_regs.h.
| enum ra8_vin_yccr_shift_t : uint8_t |
Field shift positions for the RGB-to-YUV coefficient registers.
Definition at line 634 of file ra8_vin_regs.h.
| enum ra8_vin_ymode_value_t : uint8_t |
Decoded values of DMR.YMODE (YC transfer mode).
HUM Ch 67.2.19 p 3992. Picks how the Y / CbCr planes are layered into memory in YC-separated mode.
Definition at line 807 of file ra8_vin_regs.h.
| enum ra8_vin_yuv444_value_t : uint8_t |
Decoded values of MC.YUV444 (YUV-444 conversion).
HUM Ch 67.2.1 p 3975. Selects how the missing CbCr samples in 4:2:2 input are interpolated up to 4:4:4.
| Enumerator | |
|---|---|
| k_ra8_vin_yuv444_data_extend | Repeat the previous CbCr sample. |
| k_ra8_vin_yuv444_interpolate | Linearly interpolate CbCr samples. |
Definition at line 822 of file ra8_vin_regs.h.
|
inlinestatic |
Pointer to a 32-bit register inside the VIN block.
| [in] | off | Register offset (one of k_ra8_vin_off_*). |
Definition at line 933 of file ra8_vin_regs.h.
References k_ra8_vin0_base_addr.
Referenced by internal_mc_rmw(), internal_pulse_st(), ra8_vin_capture_arm(), ra8_vin_capture_disarm(), ra8_vin_capture_start(), ra8_vin_clear_status(), ra8_vin_deinit(), ra8_vin_dispatch(), ra8_vin_enter_stop(), ra8_vin_get_active_buffer(), ra8_vin_get_line_count(), ra8_vin_get_module_status(), ra8_vin_get_status(), ra8_vin_init(), ra8_vin_lut_program(), ra8_vin_reset(), ra8_vin_set_csi_input(), ra8_vin_set_data_mode(), ra8_vin_set_field_detect(), ra8_vin_set_framebuffers(), ra8_vin_set_interrupt_enable(), ra8_vin_set_preclip(), ra8_vin_set_rgb_to_yc(), ra8_vin_set_scanline_compare(), ra8_vin_set_uds_clip(), ra8_vin_set_uds_ctrl(), ra8_vin_set_uds_passband(), ra8_vin_set_uds_scale(), ra8_vin_set_uv_offset(), and ra8_vin_set_yc_to_rgb().
1.16.1