ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_vin_regs.h
Go to the documentation of this file.
1
71
72#pragma once
73
74#ifdef __cplusplus
75extern "C" {
76#endif
77
78#include <stdint.h>
79
80#include "ra8_attributes.h"
81
91typedef enum : uintptr_t {
92 k_ra8_vin0_base_addr = 0x40347400UL,
93 k_ra8_vin0_ns_base_addr = 0x50347400UL,
95
147
157typedef enum : uint32_t {
158 k_ra8_vin_mc_me = 0x00000001UL,
159 k_ra8_vin_mc_bps = 0x00000002UL,
160 k_ra8_vin_mc_im = 0x00000018UL,
161 k_ra8_vin_mc_en = 0x00000040UL,
162 k_ra8_vin_mc_dc = 0x0000C000UL,
163 k_ra8_vin_mc_inf = 0x00070000UL,
164 k_ra8_vin_mc_lute = 0x00100000UL,
165 k_ra8_vin_mc_st = 0x00400000UL,
166 k_ra8_vin_mc_dc2 = 0x01000000UL,
167 k_ra8_vin_mc_yuv444 = 0x02000000UL,
168 k_ra8_vin_mc_scle = 0x04000000UL,
169 k_ra8_vin_mc_clp = 0x30000000UL,
171
186
195typedef enum : uint32_t {
196 k_ra8_vin_fc_cc = 0x00000002UL,
198
208typedef enum : uint32_t {
209 k_ra8_vin_ms_ca = 0x00000001UL,
210 k_ra8_vin_ms_av = 0x00000002UL,
211 k_ra8_vin_ms_fs = 0x00000004UL,
212 k_ra8_vin_ms_fbs = 0x00000018UL,
213 k_ra8_vin_ms_ma = 0x00010000UL,
214 k_ra8_vin_ms_fms = 0x00180000UL,
216
228
243
258typedef enum : uint32_t {
259 k_ra8_vin_int_fos = 0x00000001UL,
260 k_ra8_vin_int_eof = 0x00000002UL,
261 k_ra8_vin_int_scanline = 0x00000004UL,
262 k_ra8_vin_int_field = 0x00000010UL,
263 k_ra8_vin_int_fme = 0x00000020UL,
264 k_ra8_vin_int_prcliph = 0x00000100UL,
265 k_ra8_vin_int_prclipv = 0x00000200UL,
266 k_ra8_vin_int_resp_ovf = 0x00004000UL,
267 k_ra8_vin_int_axi_err = 0x00008000UL,
268 k_ra8_vin_int_vsync_d = 0x00010000UL,
269 k_ra8_vin_int_vsync_a = 0x00020000UL,
270 k_ra8_vin_int_field2 = 0x80000000UL,
272
284typedef enum : uint32_t {
285 k_ra8_vin_int_w1c_mask = 0x80008001UL,
287
296typedef enum : uint32_t {
297 k_ra8_vin_int_all_mask = 0x8003C737UL,
299
310typedef enum : uint32_t {
311 k_ra8_vin_mtcstop_req = 0x00000001UL,
312 k_ra8_vin_mtcstop_ack = 0x00000002UL,
315
323
333typedef enum : uint32_t {
334 k_ra8_vin_dmr_dtmd = 0x00000003UL,
335 k_ra8_vin_dmr_abit = 0x00000004UL,
336 k_ra8_vin_dmr_bpsm = 0x00000010UL,
337 k_ra8_vin_dmr_exrgb = 0x00000100UL,
338 k_ra8_vin_dmr_yc_thr = 0x00000800UL,
339 k_ra8_vin_dmr_ymode = 0x00007000UL,
340 k_ra8_vin_dmr_a8bit = 0xFF000000UL,
342
352
362typedef enum : uint32_t {
364 k_ra8_vin_csi_ifmd_dt = 0x00003F00UL,
365 k_ra8_vin_csi_ifmd_des0 = 0x02000000UL,
367
376
384typedef enum : uint32_t {
385 k_ra8_vin_csifld_fld_en = 0x00000001UL,
389
397
406typedef enum : uint32_t {
407 k_ra8_vin_preclip_mask = 0x00000FFFUL,
409
418typedef enum : uint32_t {
419 k_ra8_vin_is_mask = 0x00001FFFUL,
421
430typedef enum : uint32_t {
431 k_ra8_vin_lc_mask = 0x00000FFFUL,
433
442typedef enum : uint32_t {
443 k_ra8_vin_si_mask = 0x00000FFFUL,
445
454typedef enum : uint32_t {
455 k_ra8_vin_mb_addr_mask = 0xFFFFFF80UL,
456 k_ra8_vin_mb_align_mask = 0x0000007FUL,
458
467typedef enum : uint32_t {
468 k_ra8_vin_uvaof_mask = 0xFFFFFF80UL,
470
481typedef enum : uint32_t {
485 k_ra8_vin_uds_ctrl_bc = 0x00100000UL,
487 k_ra8_vin_uds_ctrl_amd = 0x40000000UL,
489
499typedef enum : uint32_t {
505
516
525typedef enum : uint32_t {
526 k_ra8_vin_uds_bwidth_v = 0x0000007FUL,
527 k_ra8_vin_uds_bwidth_h = 0x007F0000UL,
529
538
547typedef enum : uint32_t {
548 k_ra8_vin_uds_clip_v = 0x00000FFFUL,
549 k_ra8_vin_uds_clip_h = 0x0FFF0000UL,
551
560
570typedef enum : uint32_t {
571 k_ra8_vin_lutp_ltcrpr = 0x000003FFUL,
572 k_ra8_vin_lutp_ltcbpr = 0x000FFC00UL,
573 k_ra8_vin_lutp_ltypr = 0x3FF00000UL,
575
585
595typedef enum : uint32_t {
596 k_ra8_vin_lutd_ltcrdt = 0x000000FFUL,
597 k_ra8_vin_lutd_ltcbdt = 0x0000FF00UL,
598 k_ra8_vin_lutd_ltydt = 0x00FF0000UL,
600
610
621typedef enum : uint32_t {
622 k_ra8_vin_yc1_rp = 0x00001FFFUL,
623 k_ra8_vin_yc2_gp = 0x00001FFFUL,
624 k_ra8_vin_yc2_bp = 0x1FFF0000UL,
625 k_ra8_vin_yc3_ap = 0x00000FFFUL,
626 k_ra8_vin_yc3_hen = 0x00800000UL,
627 k_ra8_vin_yc3_sft = 0x1F000000UL,
629
641
652typedef enum : uint32_t {
653 k_ra8_vin_csce1_ymul2 = 0x00003FFFUL,
654 k_ra8_vin_csce1_round = 0x00010000UL,
656
666typedef enum : uint32_t {
667 k_ra8_vin_csce2_csub2 = 0x00000FFFUL,
668 k_ra8_vin_csce2_ysub2 = 0x0FFF0000UL,
670
675typedef enum : uint8_t {
678
687typedef enum : uint32_t {
688 k_ra8_vin_csce_mul_lo = 0x00003FFFUL,
689 k_ra8_vin_csce_mul_hi = 0x3FFF0000UL,
691
696typedef enum : uint8_t {
699
708typedef enum : uint16_t {
711
722typedef enum : uint8_t {
725
737typedef enum : uint16_t {
740
755
770
784
798
813
826
840
857
870
880typedef enum : uint16_t {
884
899
909typedef enum : uint32_t {
913 k_ra8_vin_csce1_init = 0x0001129FUL,
914 k_ra8_vin_csce2_init = 0x01000800UL,
916
933static inline volatile uint32_t* ra8_vin_reg32(ra8_vin_off_t off)
934{
935 return (volatile uint32_t*)(k_ra8_vin0_base_addr + (uintptr_t)(uint16_t)off);
936}
937
938#ifdef __cplusplus
939}
940#endif
Annotation-attribute framework macros for ra8-firmware.
#define RA8_HW_REGISTER_ACCESS
Mark an MMIO accessor function (returns volatile register pointer).
ra8_vin_is_mask_t
Bit masks for the IS (Image Stride) register.
@ k_ra8_vin_is_mask
IS[12:0] image stride in pixels.
ra8_vin_st_settle_t
Number of MC.ST read-back cycles required before MC.ME = 1.
@ k_ra8_vin_st_settle_reads
MC.ST settle read-backs.
ra8_vin_fc_mask_t
Bit masks for the FC (Frame Capture) register.
@ k_ra8_vin_fc_cc
CC [1] Continuous frame capture mode.
ra8_vin_lutd_shift_t
Field shift positions for LUTD.
@ k_ra8_vin_lutd_shift_ltydt
Y data byte shift.
@ k_ra8_vin_lutd_shift_ltcbdt
Cb data byte shift.
@ k_ra8_vin_lutd_shift_ltcrdt
Cr data byte shift.
ra8_vin_mtcstop_mask_t
Bit masks for the MTCSTOP (AXI transfer stop) register.
@ k_ra8_vin_mtcstop_ack
STOPACK [1] (R).
@ k_ra8_vin_mtcstop_outstand
OUTSTAND[21:16] (R).
@ k_ra8_vin_mtcstop_req
STOPREQ [0].
ra8_vin_clp_value_t
Decoded values of MC.CLP (Pixel data clipping field).
@ k_ra8_vin_clp_disabled
11 – clipping disabled (pass through).
@ k_ra8_vin_clp_nibble
01 – lower 4-bit clipping mode.
@ k_ra8_vin_clp_default
00 – default clipping mode.
ra8_vin_csce34_mask_t
Bit masks for the CSCE3 / CSCE4 multiply-pair registers.
@ k_ra8_vin_csce_mul_hi
High multiplier [29:16].
@ k_ra8_vin_csce_mul_lo
Low multiplier [13:0].
ra8_vin_dmr_shift_t
Field shift positions for DMR.
@ k_ra8_vin_dmr_shift_dtmd
DTMD[1:0] shift.
@ k_ra8_vin_dmr_shift_a8bit
A8BIT[31:24] shift.
@ k_ra8_vin_dmr_shift_ymode
YMODE[14:12] shift.
ra8_vin_uds_ctrl_mask_t
Bit masks for the UDS_CTRL register.
@ k_ra8_vin_uds_ctrl_amd
AMD [30] Advanced pixel cnt.
@ k_ra8_vin_uds_ctrl_bladv
BLADV [28] Advanced bilinear.
@ k_ra8_vin_uds_ctrl_bc
BC [20] Bilinear vs multi.
@ k_ra8_vin_uds_ctrl_ne_bcb
NE_BCB [16] B/Cb interp method.
@ k_ra8_vin_uds_ctrl_ne_gy
NE_GY [17] G/Y interp method.
@ k_ra8_vin_uds_ctrl_ne_rcr
NE_RCR [18] R/Cr interp method.
ra8_vin_yccr_init_t
Reset / suggested-initial values for YCCRn / CBCCRn / CRCCRn.
@ k_ra8_vin_yccr_y_setting1_init
YCCR1 reset.
@ k_ra8_vin_csce1_init
CSCE1 reset (YMUL2/ROUND).
@ k_ra8_vin_yccr_y_setting3_init
YCCR3 reset (HEN = 1).
@ k_ra8_vin_yccr_y_setting2_init
YCCR2 reset.
@ k_ra8_vin_csce2_init
CSCE2 reset (YSUB2/CSUB2).
ra8_vin_csi_ifmd_shift_t
Field shift positions for CSI_IFMD.
@ k_ra8_vin_csi_ifmd_shift_vc_sel
VC_SEL[3:0] shift.
@ k_ra8_vin_csi_ifmd_shift_dt
DT[13:8] shift.
ra8_vin_uds_scale_shift_t
Field shift positions for UDS_SCALE.
@ k_ra8_vin_uds_scale_shift_vmant
VMANT[15:12] shift.
@ k_ra8_vin_uds_scale_shift_hmant
HMANT[31:28] shift.
@ k_ra8_vin_uds_scale_shift_hfrac
HFRAC[27:16] shift.
@ k_ra8_vin_uds_scale_shift_vfrac
VFRAC[11:0] shift.
ra8_vin_si_mask_t
Bit masks for the SI (Scanline Interrupt) register.
@ k_ra8_vin_si_mask
SI[11:0] scanline match value.
ra8_vin_csifld_shift_t
Field shift positions for CSIFLD.
@ k_ra8_vin_csifld_shift_fld_sel
FLD_SEL[5:4] shift.
ra8_vin_lc_mask_t
Bit masks for the LC (Line Count) register.
@ k_ra8_vin_lc_mask
LC[11:0] line count.
ra8_vin_addr_t
Memory-mapped base addresses for the VIN block.
@ k_ra8_vin0_ns_base_addr
VIN0 non-secure alias (HUM Ch 67.2 p 3974).
@ k_ra8_vin0_base_addr
VIN0 secure base (HUM Ch 67.2 p 3974).
ra8_vin_uds_bwidth_mask_t
Bit masks for the UDS_PASS_BWIDTH register.
@ k_ra8_vin_uds_bwidth_h
BWIDTH_H [22:16].
@ k_ra8_vin_uds_bwidth_v
BWIDTH_V [6:0].
ra8_vin_off_t
32-bit register offsets inside the VIN window.
@ k_ra8_vin_off_csifld
CSIFLD Field detect control.
@ k_ra8_vin_off_uvaof
UVAOF UV data address offset.
@ k_ra8_vin_off_lutp
LUTP LUT pointer (Y/Cb/Cr).
@ k_ra8_vin_off_csi_ifmd
CSI_IFMD CSI-2 interface mode.
@ k_ra8_vin_off_slprc
SLPRC Pre-clip start line.
@ k_ra8_vin_off_csce2
CSCE2 YC-to-RGB Y/CbCr subtraction.
@ k_ra8_vin_off_mb1
MB1 Memory base 1 (frame addr).
@ k_ra8_vin_off_crccr2
CRCCR2 RGB-to-Cr coeff G+B.
@ k_ra8_vin_off_lutd
LUTD LUT data (Y/Cb/Cr).
@ k_ra8_vin_off_fc
FC Frame capture register.
@ k_ra8_vin_off_cbccr2
CBCCR2 RGB-to-Cb coeff G+B.
@ k_ra8_vin_off_ints
INTS Interrupt status (W1C).
@ k_ra8_vin_off_uds_pass_bwidth
UDS_PASS_BWIDTH passband bandwidth.
@ k_ra8_vin_off_ie
IE Interrupt enable.
@ k_ra8_vin_off_epprc
EPPRC Pre-clip end pixel.
@ k_ra8_vin_off_csce4
CSCE4 YC-to-RGB Cb multiplication.
@ k_ra8_vin_off_mtcstop
MTCSTOP AXI transfer stop control.
@ k_ra8_vin_off_lc
LC Line count (R).
@ k_ra8_vin_off_mb2
MB2 Memory base 2 (frame addr).
@ k_ra8_vin_off_elprc
ELPRC Pre-clip end line.
@ k_ra8_vin_off_cbccr1
CBCCR1 RGB-to-Cb coeff R.
@ k_ra8_vin_off_mb3
MB3 Memory base 3 (frame addr).
@ k_ra8_vin_off_mc
MC Main control register.
@ k_ra8_vin_off_crccr1
CRCCR1 RGB-to-Cr coeff R.
@ k_ra8_vin_off_si
SI Scanline interrupt compare.
@ k_ra8_vin_off_ms
MS Module status (R).
@ k_ra8_vin_off_dmr
DMR Data mode register.
@ k_ra8_vin_off_uds_clip_size
UDS_CLIP_SIZE output clip size.
@ k_ra8_vin_off_yccr1
YCCR1 RGB-to-Y coeff R.
@ k_ra8_vin_off_yccr2
YCCR2 RGB-to-Y coeff G+B.
@ k_ra8_vin_off_is
IS Image stride.
@ k_ra8_vin_off_cbccr3
CBCCR3 RGB-to-Cb norm/shift.
@ k_ra8_vin_off_yccr3
YCCR3 RGB-to-Y norm/shift.
@ k_ra8_vin_off_csce1
CSCE1 YC-to-RGB Y multiplication.
@ k_ra8_vin_off_spprc
SPPRC Pre-clip start pixel.
@ k_ra8_vin_off_uds_ctrl
UDS_CTRL Scaling interpolation ctrl.
@ k_ra8_vin_off_csce3
CSCE3 YC-to-RGB Cr multiplication.
@ k_ra8_vin_off_crccr3
CRCCR3 RGB-to-Cr norm/shift.
@ k_ra8_vin_off_uds_scale
UDS_SCALE Scaling factor V/H.
ra8_vin_mb_addr_mask_t
Bit masks for the MB1/MB2/MB3 frame-buffer base registers.
@ k_ra8_vin_mb_addr_mask
MBn[31:7] base address.
@ k_ra8_vin_mb_align_mask
Reserved low bits (must be zero).
ra8_vin_lutd_mask_t
Bit masks for the LUTD (LUT Data) register.
@ k_ra8_vin_lutd_ltydt
LTYDT [23:16] Y data byte.
@ k_ra8_vin_lutd_ltcbdt
LTCBDT [15:8] Cb data byte.
@ k_ra8_vin_lutd_ltcrdt
LTCRDT [7:0] Cr data byte.
ra8_vin_csce2_shift_t
Field shift positions for CSCE2.
@ k_ra8_vin_csce2_shift_ysub2
YSUB2[27:16] shift.
ra8_vin_dtmd_value_t
Decoded values of DMR.DTMD (Data conversion mode).
@ k_ra8_vin_dtmd_rgb_to_argb
RGB input rendered as ARGB.
@ k_ra8_vin_dtmd_yc_separated
Y/CbCr separated to two planes.
@ k_ra8_vin_dtmd_none
Pass-through (no conversion).
ra8_vin_dc_value_t
Decoded values of MC.DC (Dithering Mode field).
@ k_ra8_vin_dc_ordered_1
01 – ordered dithering pattern 1.
@ k_ra8_vin_dc_addition
00 – dithering with cumulative addition.
@ k_ra8_vin_dc_ordered_2
10 – ordered dithering pattern 2.
ra8_vin_lut_t
LUT geometry constants.
@ k_ra8_vin_lut_entries
LUT entry count for Y, Cb, and Cr.
ra8_vin_field_polarity_t
Decoded values for the CSIFLD.FLD_NUM bit.
@ k_ra8_vin_field_even_is_zero
field-number 0 -> even.
@ k_ra8_vin_field_even_is_one
field-number 1 -> even.
ra8_vin_yccr_mask_t
Bit masks for the RGB-to-YUV coefficient registers.
@ k_ra8_vin_yc2_gp
Setting 2: G coeff [12:0].
@ k_ra8_vin_yc3_sft
Setting 3: shift-down volume [28:24].
@ k_ra8_vin_yc1_rp
Setting 1: R coeff [12:0].
@ k_ra8_vin_yc3_ap
Setting 3: additive offset [11:0].
@ k_ra8_vin_yc2_bp
Setting 2: B coeff [28:16].
@ k_ra8_vin_yc3_hen
Setting 3: round-off enable [23].
ra8_vin_csce2_mask_t
Bit masks for the CSCE2 (YC-to-RGB subtract) register.
@ k_ra8_vin_csce2_csub2
CSUB2 [11:0].
@ k_ra8_vin_csce2_ysub2
YSUB2 [27:16].
ra8_vin_ms_fbs_t
Decoded values of MS.FBS / MS.FMS.
@ k_ra8_vin_fbs_invalid
No valid frame buffer.
@ k_ra8_vin_fbs_mb2
Latest frame in MB2.
@ k_ra8_vin_fbs_mb1
Latest frame in MB1.
@ k_ra8_vin_fbs_mb3
Latest frame in MB3.
ra8_vin_dmr_mask_t
Bit masks for the DMR (Data Mode) register.
@ k_ra8_vin_dmr_a8bit
A8BIT [31:24] ARGB-8888 alpha.
@ k_ra8_vin_dmr_bpsm
BPSM [4] Byte-swap mode.
@ k_ra8_vin_dmr_exrgb
EXRGB [8] Extend RGB to 32-bit.
@ k_ra8_vin_dmr_abit
ABIT [2] ARGB-1555 alpha bit.
@ k_ra8_vin_dmr_ymode
YMODE [14:12] YC transfer mode.
@ k_ra8_vin_dmr_dtmd
DTMD [1:0] Data conversion mode.
@ k_ra8_vin_dmr_yc_thr
YC_THR [11] YC data through mode.
ra8_vin_yccr_shift_t
Field shift positions for the RGB-to-YUV coefficient registers.
@ k_ra8_vin_yccr_shift_sft
Setting 3 shift-down shift.
@ k_ra8_vin_yccr_shift_ap
Setting 3 offset shift.
@ k_ra8_vin_yccr_shift_rp
Setting 1 R coeff shift.
@ k_ra8_vin_yccr_shift_gp
Setting 2 G coeff shift.
@ k_ra8_vin_yccr_shift_bp
Setting 2 B coeff shift.
ra8_vin_yuv444_value_t
Decoded values of MC.YUV444 (YUV-444 conversion).
@ k_ra8_vin_yuv444_interpolate
Linearly interpolate CbCr samples.
@ k_ra8_vin_yuv444_data_extend
Repeat the previous CbCr sample.
ra8_vin_csi_dt_value_t
Common values for the CSI_IFMD.DT field.
@ k_ra8_vin_csi_dt_yuv422_8
YUV 4:2:2 8-bit.
@ k_ra8_vin_csi_dt_raw8
RAW-8.
@ k_ra8_vin_csi_dt_yuv422_10
YUV 4:2:2 10-bit.
@ k_ra8_vin_csi_dt_rgb888
RGB-888.
ra8_vin_lut_geometry_t
Geometric / range constants for the LUT plane.
@ k_ra8_vin_lut_max_byte
LUTD byte field width.
@ k_ra8_vin_lut_max_pointer
LUTP pointer field width.
ra8_vin_csi_ifmd_mask_t
Bit masks for the CSI_IFMD (CSI-2 Interface Mode) register.
@ k_ra8_vin_csi_ifmd_dt
DT [13:8] Data type.
@ k_ra8_vin_csi_ifmd_vc_sel
VC_SEL [3:0] Virtual channel.
@ k_ra8_vin_csi_ifmd_des0
DES0 [25] Data extension.
ra8_vin_uds_scale_geometry_t
Range / step limits for UDS scaling factor and clipping.
@ k_ra8_vin_uds_max_clip
12-bit clip-size max.
@ k_ra8_vin_uds_max_bw
7-bit pass-band width max.
@ k_ra8_vin_uds_max_mant
4-bit mantissa max value.
@ k_ra8_vin_uds_max_frac
12-bit fractional max value.
ra8_vin_field_mask_t
Bit masks for SLPRC / ELPRC / SPPRC / EPPRC pre-clip registers.
@ k_ra8_vin_preclip_mask
12-bit pre-clip count.
ra8_vin_mtcstop_shift_t
Field shift positions for MTCSTOP.
@ k_ra8_vin_mtcstop_shift_outstand
OUTSTAND[21:16] shift.
ra8_vin_uds_scale_mask_t
Bit masks for the UDS_SCALE register.
@ k_ra8_vin_uds_scale_hfrac
HFRAC [27:16] H scale frac.
@ k_ra8_vin_uds_scale_hmant
HMANT [31:28] H scale int.
@ k_ra8_vin_uds_scale_vfrac
VFRAC [11:0] V scale frac.
@ k_ra8_vin_uds_scale_vmant
VMANT [15:12] V scale int.
ra8_vin_lutp_mask_t
Bit masks for the LUTP (LUT Pointer) register.
@ k_ra8_vin_lutp_ltypr
LTYPR [29:20] Y pointer.
@ k_ra8_vin_lutp_ltcrpr
LTCRPR [9:0] Cr pointer.
@ k_ra8_vin_lutp_ltcbpr
LTCBPR [19:10] Cb pointer.
ra8_vin_int_w1c_mask_t
Subset of INTS bits that are write-1-to-clear.
@ k_ra8_vin_int_w1c_mask
FOS | ARES | FIS2.
ra8_vin_ms_mask_t
Bit masks for the MS (Module Status) register.
@ k_ra8_vin_ms_ma
MA [16] Memory capture active.
@ k_ra8_vin_ms_av
AV [1] Active video.
@ k_ra8_vin_ms_fs
FS [2] Field status (0=odd,1=even).
@ k_ra8_vin_ms_ca
CA [0] Capture active.
@ k_ra8_vin_ms_fbs
FBS [4:3] Latest frame buffer id.
@ k_ra8_vin_ms_fms
FMS [20:19] External MB buffer status.
static volatile uint32_t * ra8_vin_reg32(ra8_vin_off_t off)
Pointer to a 32-bit register inside the VIN block.
ra8_vin_im_value_t
Decoded values of MC.IM (Interlace Mode field).
@ k_ra8_vin_im_odd_even
01 – both odd and even fields captured.
@ k_ra8_vin_im_odd_only
00 – odd-field (field 1) capture.
@ k_ra8_vin_im_even_only
10 – even-field only capture.
ra8_vin_mc_shift_t
Field shift positions for multi-bit MC fields.
@ k_ra8_vin_mc_shift_inf
INF[18:16] shift.
@ k_ra8_vin_mc_shift_im
IM[4:3] shift.
@ k_ra8_vin_mc_shift_clp
CLP[29:28] shift.
@ k_ra8_vin_mc_shift_dc
DC[15:14] shift.
ra8_vin_uds_bwidth_shift_t
Field shift positions for UDS_PASS_BWIDTH.
@ k_ra8_vin_uds_bwidth_shift_v
BWIDTH_V[6:0] shift.
@ k_ra8_vin_uds_bwidth_shift_h
BWIDTH_H[22:16] shift.
ra8_vin_csce_shift_t
Field shift positions for CSCE3 / CSCE4.
@ k_ra8_vin_csce_shift_mul_hi
High multiplier shift.
ra8_vin_int_mask_t
Bit masks for the IE (Interrupt Enable) and INTS (Interrupt Status) registers.
@ k_ra8_vin_int_fme
[5] Frame memory write complete.
@ k_ra8_vin_int_prclipv
[9] Vertical preclip error.
@ k_ra8_vin_int_resp_ovf
[14] Response overflow (ROS / ROE).
@ k_ra8_vin_int_field2
[31] Field detect 2 (W1C).
@ k_ra8_vin_int_vsync_a
[17] VSYNC assert (VFS / VFE).
@ k_ra8_vin_int_field
[4] Field switch (FIS / FIE).
@ k_ra8_vin_int_fos
[0] FIFO overflow (W1C).
@ k_ra8_vin_int_scanline
[2] Scanline match (SIS / SIE).
@ k_ra8_vin_int_prcliph
[8] Horizontal preclip error.
@ k_ra8_vin_int_eof
[1] End of frame (EFS / EFE).
@ k_ra8_vin_int_axi_err
[15] AXI response error (W1C).
@ k_ra8_vin_int_vsync_d
[16] VSYNC deassert (VRS / VRE).
ra8_vin_uvaof_mask_t
Bit masks for the UVAOF (UV Address Offset) register.
@ k_ra8_vin_uvaof_mask
UVAOF[31:7] UV data offset.
ra8_vin_ms_shift_t
Field shift positions for multi-bit MS fields.
@ k_ra8_vin_ms_shift_fbs
FBS[4:3] shift.
@ k_ra8_vin_ms_shift_fms
FMS[20:19] shift.
ra8_vin_ymode_value_t
Decoded values of DMR.YMODE (YC transfer mode).
@ k_ra8_vin_ymode_y_cbcr
Y + CbCr 8-bit interleaved planes.
@ k_ra8_vin_ymode_y10_only
Y plane 10-bit only.
@ k_ra8_vin_ymode_y10_cbcr
Y plane 10-bit + CbCr 8-bit.
@ k_ra8_vin_ymode_y_only
Y plane only, 8-bit.
ra8_vin_uds_clip_size_mask_t
Bit masks for the UDS_CLIP_SIZE register.
@ k_ra8_vin_uds_clip_v
CL_VSIZE [11:0] .
@ k_ra8_vin_uds_clip_h
CL_HSIZE [27:16].
ra8_vin_int_all_mask_t
Union of every documented IE/INTS bit (FOS through FIS2).
@ k_ra8_vin_int_all_mask
All defined IE/INTS bits.
ra8_vin_csce1_mask_t
Bit masks for the CSCE1 (YC-to-RGB Y multiply) register.
@ k_ra8_vin_csce1_ymul2
YMUL2 [13:0].
@ k_ra8_vin_csce1_round
ROUND [16].
ra8_vin_uds_clip_shift_t
Field shift positions for UDS_CLIP_SIZE.
@ k_ra8_vin_uds_clip_shift_v
CL_VSIZE shift.
@ k_ra8_vin_uds_clip_shift_h
CL_HSIZE shift.
ra8_vin_uds_interp_value_t
Decoded values for the UDS_CTRL NE_* / BC interpolation flags.
@ k_ra8_vin_uds_bilinear
Bilinear interpolation.
@ k_ra8_vin_uds_nearest
Nearest-neighbour interpolation.
ra8_vin_mc_mask_t
Bit masks for the MC (Main Control) register.
@ k_ra8_vin_mc_lute
LUTE [20] LUT enable.
@ k_ra8_vin_mc_clp
CLP [29:28] Pixel data clipping.
@ k_ra8_vin_mc_dc2
DC2 [24] Dithering direction.
@ k_ra8_vin_mc_im
IM [4:3] Interlace mode.
@ k_ra8_vin_mc_yuv444
YUV444[25] YUV444 conversion.
@ k_ra8_vin_mc_bps
BPS [1] Colour-space bypass.
@ k_ra8_vin_mc_en
EN [6] Endian (1 = big).
@ k_ra8_vin_mc_st
ST [22] Init at startup (W).
@ k_ra8_vin_mc_scle
SCLE [26] UDS scaling enable.
@ k_ra8_vin_mc_inf
INF [18:16] Input interface format.
@ k_ra8_vin_mc_dc
DC [15:14] Dithering mode.
@ k_ra8_vin_mc_me
ME [0] Module Enable.
ra8_vin_stop_drain_t
Number of MTCSTOP poll iterations before declaring timeout.
@ k_ra8_vin_stop_drain_max
Max OUTSTAND poll iterations.
ra8_vin_csifld_mask_t
Bit masks for the CSIFLD (Field Detect Control) register.
@ k_ra8_vin_csifld_fld_num
FLD_NUM [16] Even-field number.
@ k_ra8_vin_csifld_fld_sel
FLD_SEL [5:4] Even-field select.
@ k_ra8_vin_csifld_fld_en
FLD_EN [0] Field detect.
ra8_vin_lutp_shift_t
Field shift positions for LUTP.
@ k_ra8_vin_lutp_shift_ltcbpr
Cb pointer shift.
@ k_ra8_vin_lutp_shift_ltcrpr
Cr pointer shift.
@ k_ra8_vin_lutp_shift_ltypr
Y pointer shift.