ra8_usb_host_bulk.c

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#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_usb.h"
#include "ra8_usb_internal.h"
#include "ra8_usb_regs.h"
 
static const char* s_tag = "USB";
 
/* =============================================================================
 * Host-mode bulk-transfer engine (polled, synchronous)
 *
 * Built on the same host signals the control engine validated on hardware:
 * BRDY (a packet landed in the pipe buffer), BEMP (the pipe buffer emptied
 * onto the wire), and PIPECTR.PID for STALL detection. Pipes reuse the CFIFO
 * port (CFIFOSEL.CURPIPE selects the pipe; the data direction is fixed by
 * PIPECFG.DIR, so ISEL stays clear for non-DCP pipes).
 * =============================================================================
 */

typedef enum : uint32_t {
  /* Each spin performs two peripheral-bus reads (~150 ns/read on the FS
   * block), so 10M spins is roughly a 3 s ceiling -- enough for flash
   * media latency while keeping a failed phase visibly bounded. */
  k_ra8_usb_bulk_poll_limit = 10000000UL, 
} ra8_usb_host_bulk_lim_t;

RA8_INTERNAL
static ra8_err_t internal_host_wait_pipe(volatile const r_usb_regs_t* reg,
                                         volatile const uint16_t*     sts,
                                         uint8_t                      pipe_num)
{
  const uint16_t bit = (uint16_t)(1U << pipe_num);
  const uint8_t  idx = (uint8_t)(pipe_num - 1U);
  for (uint32_t i = 0U; i < (uint32_t)k_ra8_usb_bulk_poll_limit; ++i) {
    if ((*sts & bit) != 0U) {
      return k_ra8_ok;
    }
    if ((reg->PIPECTR[idx] & (uint16_t)k_ra8_usb_pid_stall_bit) != 0U) {
      /* STALL bit is SIE-async; callers force PID=BUF before this spin, the fake cannot raise it. */
      return k_ra8_err_hw_error; /* GCOVR_EXCL_LINE -- async SIE STALL absent from host fake */
    }
  }
  return k_ra8_err_hw_timeout;
}

ra8_err_t ra8_usb_host_set_target(ra8_usb_speed_t speed, uint8_t dev_addr)
{
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if (dev_addr > (uint8_t)k_ra8_usb_dev_addr_max) {
    return k_ra8_err_invalid_arg;
  }
  priv_host_program_devadd(reg, dev_addr);
  const uint16_t mxps = (uint16_t)(reg->DCPMAXP & (uint16_t)k_ra8_usb_dcpmaxp_mxps);
  reg->DCPMAXP =
    (uint16_t)((uint16_t)((uint16_t)dev_addr << (uint16_t)k_ra8_usb_devsel_shift) | mxps);
  return k_ra8_ok;
}

RA8_INTERNAL
static ra8_err_t
internal_host_pipe_args_ok(uint8_t pipe_num, uint8_t dev_addr, uint8_t ep_num, uint16_t max_packet)
{
  if (pipe_num == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (pipe_num > (uint8_t)k_ra8_usb_max_pipe_num) {
    return k_ra8_err_invalid_arg;
  }
  if (dev_addr > (uint8_t)k_ra8_usb_dev_addr_max) {
    return k_ra8_err_invalid_arg;
  }
  if (ep_num == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (ep_num > (uint8_t)k_ra8_pipecfg_epnum_mask) {
    return k_ra8_err_invalid_arg;
  }
  if (max_packet == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (max_packet > (uint16_t)k_ra8_usb_pipemaxp_mxps) {
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

ra8_err_t ra8_usb_host_pipe_setup(ra8_usb_speed_t speed,
                                  uint8_t         pipe_num,
                                  uint8_t         dev_addr,
                                  uint8_t         ep_num,
                                  bool            device_to_host,
                                  uint16_t        max_packet)
{
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  const ra8_err_t arg_err = internal_host_pipe_args_ok(pipe_num, dev_addr, ep_num, max_packet);
  if (arg_err != k_ra8_ok) {
    return arg_err;
  }
  priv_pipe_quiesce(reg, pipe_num);
  const ra8_usb_ep_dir_t cfg_dir = device_to_host ? k_ra8_usb_ep_dir_out : k_ra8_usb_ep_dir_in;
  reg->PIPESEL                   = pipe_num;
  reg->PIPECFG                   = priv_pipecfg_word(ep_num, cfg_dir, k_ra8_usb_ep_type_bulk, true);
  reg->PIPEBUF                   = priv_pipebuf_word(pipe_num, max_packet);
  reg->PIPEMAXP = (uint16_t)((uint16_t)((uint16_t)dev_addr << (uint16_t)k_ra8_usb_devsel_shift) |
                             (uint16_t)(max_packet & (uint16_t)k_ra8_usb_pipemaxp_mxps));
  reg->PIPEPERI = 0U;
  reg->PIPESEL  = 0U;
  priv_rmw16(&reg->PIPECTR[(uint8_t)(pipe_num - 1U)], (uint16_t)(1U << k_ra8_dcpctr_bit_sqclr), 0U);
  const uint16_t pipe_bit = (uint16_t)(1U << pipe_num);
  reg->BRDYSTS            = (uint16_t)~pipe_bit;
  reg->NRDYSTS            = (uint16_t)~pipe_bit;
  reg->BEMPSTS            = (uint16_t)~pipe_bit;
  return k_ra8_ok;
}

ra8_err_t
ra8_usb_host_bulk_out(ra8_usb_speed_t speed, uint8_t pipe_num, const uint8_t* data, uint16_t len)
{
  RA8_CHECK_NULL_PTR(data, s_tag, "host_bulk_out: data");
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if (pipe_num == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (pipe_num > (uint8_t)k_ra8_usb_max_pipe_num) {
    return k_ra8_err_invalid_arg;
  }
  const uint16_t pipe_bit = (uint16_t)(1U << pipe_num);
  reg->BEMPSTS            = (uint16_t)~pipe_bit;
  reg->BEMPENB            = (uint16_t)(reg->BEMPENB | pipe_bit);
  const ra8_err_t qerr    = ra8_usb_queue_in(speed, pipe_num, data, len);
  if (qerr != k_ra8_ok) {
    return qerr;
  }
  const ra8_err_t werr = internal_host_wait_pipe(reg, &reg->BEMPSTS, pipe_num);
  priv_pipe_pid(reg, pipe_num, k_ra8_pid_nak);
  reg->BEMPSTS = (uint16_t)~pipe_bit;
  return werr;
}

RA8_INTERNAL
static ra8_err_t internal_host_bulk_rx_packet(volatile r_usb_regs_t* reg,
                                              uint8_t                pipe_num,
                                              uint8_t*               dst,
                                              uint16_t               room,
                                              uint16_t*              out_dtln,
                                              uint16_t*              out_copied)
{
  const ra8_err_t werr = internal_host_wait_pipe(reg, &reg->BRDYSTS, pipe_num);
  if (werr != k_ra8_ok) {
    return werr;
  }
  /* Acknowledge the BRDY edge BEFORE draining the buffer: at high speed
   * the device's next packet (e.g. the CSW right behind a full data
   * packet) lands while the FIFO is being read, and clearing the status
   * afterwards wipes that new edge (observed as the follow-up packet
   * stuck with BSTS=1 while the wait times out). */
  reg->BRDYSTS = (uint16_t)~(uint16_t)(1U << pipe_num);
  priv_select_cfifo(reg, (uint16_t)pipe_num, false);
  const ra8_err_t ferr = priv_wait_frdy(reg);
  if (ferr != k_ra8_ok) {
    return ferr;
  }
  const uint16_t dtln = (uint16_t)(reg->CFIFOCTR & (uint16_t)k_ra8_fifoctr_dtln);
  uint16_t       copy = dtln;
  if (copy > room) {
    copy = room;
  }
  if (copy > 0U) {
    priv_fifo_read(reg, dst, copy);
  }
  if (copy < dtln) {
    reg->CFIFOCTR = (uint16_t)k_ra8_fifoctr_bclr;
  }
  if (dtln == 0U) {
    reg->CFIFOCTR = (uint16_t)k_ra8_fifoctr_bclr;
  }
  *out_dtln   = dtln;
  *out_copied = copy;
  return k_ra8_ok;
}

RA8_INTERNAL
static ra8_err_t internal_host_bulk_rx_loop(volatile r_usb_regs_t* reg,
                                            uint8_t                pipe_num,
                                            uint8_t*               buf,
                                            uint16_t               max_len,
                                            uint16_t               mps,
                                            uint16_t*              out_rx)
{
  uint16_t  rx   = 0U;
  ra8_err_t err  = k_ra8_ok;
  bool      done = false;
  while (!done) {
    uint16_t dtln   = 0U;
    uint16_t copied = 0U;
    err             = internal_host_bulk_rx_packet(reg,
                                                   pipe_num,
                                                   &buf[rx],
                                                   (uint16_t)(max_len - rx),
                                                   &dtln,
                                                   &copied);
    if (err != k_ra8_ok) {
      done = true;
    } else {
      rx = (uint16_t)(rx + copied);
      if (dtln < mps) {
        done = true;
      }
      if (rx >= max_len) {
        done = true;
      }
    }
  }
  *out_rx = rx;
  return err;
}

ra8_err_t ra8_usb_host_bulk_in(ra8_usb_speed_t speed,
                               uint8_t         pipe_num,
                               uint8_t*        buf,
                               uint16_t        max_len,
                               uint16_t*       out_received)
{
  RA8_CHECK_NULL_PTR(buf, s_tag, "host_bulk_in: buf");
  RA8_CHECK_NULL_PTR(out_received, s_tag, "host_bulk_in: out_received");
  volatile r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return k_ra8_err_invalid_arg;
  }
  if (pipe_num == 0U) {
    return k_ra8_err_invalid_arg;
  }
  if (pipe_num > (uint8_t)k_ra8_usb_max_pipe_num) {
    return k_ra8_err_invalid_arg;
  }
  reg->PIPESEL       = pipe_num;
  const uint16_t mps = (uint16_t)(reg->PIPEMAXP & (uint16_t)k_ra8_usb_pipemaxp_mxps);
  reg->PIPESEL       = 0U;
  if (mps == 0U) {
    return k_ra8_err_invalid_state;
  }
  const uint16_t pipe_bit = (uint16_t)(1U << pipe_num);
  /* Do NOT clear a pending BRDY here: at high speed the device can push
   * the next packet (e.g. the CSW right behind a full data packet) into
   * the pipe buffer while the previous transfer is winding down, and its
   * BRDY is already latched -- clearing it would strand that packet in
   * the buffer (observed as BSTS=1 with the wait timing out). */
  reg->BRDYENB = (uint16_t)(reg->BRDYENB | pipe_bit);
  priv_pipe_pid(reg, pipe_num, k_ra8_pid_buf);
  uint16_t        rx  = 0U;
  const ra8_err_t err = internal_host_bulk_rx_loop(reg, pipe_num, buf, max_len, mps, &rx);
  priv_pipe_pid(reg, pipe_num, k_ra8_pid_nak);
  *out_received = rx;
  return err;
}

uint16_t ra8_usb_host_line_state(ra8_usb_speed_t speed)
{
  volatile const r_usb_regs_t* reg = priv_pick(speed);
  if (reg == nullptr) {
    return 0U;
  }
  return (uint16_t)(reg->SYSSTS0 & (uint16_t)k_ra8_usb_lnst_mask);
}