ra8_ssie_regs.h File Reference

Serial Sound Interface Enhanced (SSIE) register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

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Data Structures
struct	r_ssie_regs_t
	Per-channel SSIE register window. More...

Enumerations
enum	ra8_ssie_addr_t : uintptr_t {   k_ra8_ssie0_base_addr = 0x4025D000UL ,   k_ra8_ssie1_base_addr = 0x4025D100UL }
	Memory-mapped base addresses for SSIE channels. More...
enum	ra8_ssie_limits_t : uint16_t {   k_ra8_ssie_channel_count = 2U ,   k_ra8_ssie_channel_stride = 0x100U ,   k_ra8_ssie_fifo_depth = 32U ,   k_ra8_ssie_fifo_half_water = 15U ,   k_ra8_ssie_fifo_block_size = 2U ,   k_ra8_ssie_reset_poll_max = 32U }
	Channel-count, FIFO depth and stride constants. More...
enum	ra8_ssicr_bit_t : uint8_t {   k_ra8_ssie_bit_ren = 0U ,   k_ra8_ssie_bit_ten = 1U ,   k_ra8_ssie_bit_muen = 3U ,   k_ra8_ssie_bit_ckdv0 = 4U ,   k_ra8_ssie_bit_del = 8U ,   k_ra8_ssie_bit_pdta = 9U ,   k_ra8_ssie_bit_sdta = 10U ,   k_ra8_ssie_bit_spdp = 11U ,   k_ra8_ssie_bit_lrckp = 12U ,   k_ra8_ssie_bit_bckp = 13U ,   k_ra8_ssie_bit_mst = 14U ,   k_ra8_ssie_bit_swl0 = 16U ,   k_ra8_ssie_bit_dwl0 = 19U ,   k_ra8_ssie_bit_frm0 = 22U ,   k_ra8_ssie_bit_iien = 25U ,   k_ra8_ssie_bit_roien = 26U ,   k_ra8_ssie_bit_ruien = 27U ,   k_ra8_ssie_bit_toien = 28U ,   k_ra8_ssie_bit_tuien = 29U ,   k_ra8_ssie_bit_cks = 30U }
	SSICR control-bit positions. More...
enum	ra8_ssicr_mask_t : uint32_t {   k_ra8_ssie_mask_ren = 0x00000001UL ,   k_ra8_ssie_mask_ten = 0x00000002UL ,   k_ra8_ssie_mask_ren_ten = 0x00000003UL ,   k_ra8_ssie_mask_muen = 0x00000008UL ,   k_ra8_ssie_mask_ckdv = 0x000000F0UL ,   k_ra8_ssie_mask_del = 0x00000100UL ,   k_ra8_ssie_mask_pdta = 0x00000200UL ,   k_ra8_ssie_mask_sdta = 0x00000400UL ,   k_ra8_ssie_mask_spdp = 0x00000800UL ,   k_ra8_ssie_mask_lrckp = 0x00001000UL ,   k_ra8_ssie_mask_bckp = 0x00002000UL ,   k_ra8_ssie_mask_mst = 0x00004000UL ,   k_ra8_ssie_mask_swl = 0x00070000UL ,   k_ra8_ssie_mask_dwl = 0x00380000UL ,   k_ra8_ssie_mask_frm = 0x00C00000UL ,   k_ra8_ssie_mask_iien = 0x02000000UL ,   k_ra8_ssie_mask_roien = 0x04000000UL ,   k_ra8_ssie_mask_ruien = 0x08000000UL ,   k_ra8_ssie_mask_toien = 0x10000000UL ,   k_ra8_ssie_mask_tuien = 0x20000000UL ,   k_ra8_ssie_mask_cks = 0x40000000UL ,   k_ra8_ssie_mask_irq_all = 0x3E000000UL ,   k_ra8_ssie_mask_err_ien = 0x3C000000UL }
	SSICR field masks (32-bit register). More...
enum	ra8_ssisr_mask_t : uint32_t {   k_ra8_ssie_mask_idst = 0x00000001UL ,   k_ra8_ssie_mask_iirq = 0x02000000UL ,   k_ra8_ssie_mask_roirq = 0x04000000UL ,   k_ra8_ssie_mask_ruirq = 0x08000000UL ,   k_ra8_ssie_mask_toirq = 0x10000000UL ,   k_ra8_ssie_mask_tuirq = 0x20000000UL ,   k_ra8_ssie_mask_err_all = 0x3C000000UL ,   k_ra8_ssie_mask_evt_all = 0x3E000000UL }
	SSISR status flags (HUM Ch 46.2.2, p 3066-3067). More...
enum	ra8_ssifcr_mask_t : uint32_t {   k_ra8_ssie_mask_rfrst = 0x00000001UL ,   k_ra8_ssie_mask_tfrst = 0x00000002UL ,   k_ra8_ssie_mask_rfrst_tfrst = 0x00000003UL ,   k_ra8_ssie_mask_rie = 0x00000004UL ,   k_ra8_ssie_mask_tie = 0x00000008UL ,   k_ra8_ssie_mask_rie_tie = 0x0000000CUL ,   k_ra8_ssie_mask_rtrg = 0x00000030UL ,   k_ra8_ssie_mask_ttrg = 0x000000C0UL ,   k_ra8_ssie_mask_bsw = 0x00000800UL ,   k_ra8_ssie_mask_ssirst = 0x00010000UL ,   k_ra8_ssie_mask_aucke = 0x80000000UL }
	SSIFCR FIFO control bits (HUM Ch 46.2.3, p 3077). More...
enum	ra8_ssifcr_shift_t : uint8_t {   k_ra8_ssie_shift_rtrg = 4U ,   k_ra8_ssie_shift_ttrg = 6U }
	SSIFCR field bit positions for RTRG / TTRG. More...
enum	ra8_ssifsr_mask_t : uint32_t {   k_ra8_ssie_mask_rdf = 0x00000001UL ,   k_ra8_ssie_mask_rdc = 0x00003F00UL ,   k_ra8_ssie_mask_tde = 0x00010000UL ,   k_ra8_ssie_mask_tdc = 0x3F000000UL ,   k_ra8_ssie_mask_rdf_clear = 0x00010000UL ,   k_ra8_ssie_mask_tde_clear = 0x00000001UL }
	SSIFSR FIFO status bits (HUM Ch 46.2.4, p 3083-3084). More...
enum	ra8_ssifsr_shift_t : uint8_t {   k_ra8_ssie_shift_rdc = 8U ,   k_ra8_ssie_shift_tdc = 24U }
	SSIFSR field bit positions for extraction. More...
enum	ra8_ssiofr_mask_t : uint32_t {   k_ra8_ssie_mask_omod = 0x00000003UL ,   k_ra8_ssie_mask_lrcont = 0x00000100UL ,   k_ra8_ssie_mask_bckastp = 0x00000200UL }
	SSIOFR audio format bits (HUM Ch 46.2.7, p 3091). More...
enum	ra8_ssiscr_mask_t : uint32_t {   k_ra8_ssie_mask_rdfs = 0x0000001FUL ,   k_ra8_ssie_mask_tdes = 0x00001F00UL }
	SSISCR FIFO trigger thresholds (HUM Ch 46.2.8, p 3094). More...
enum	ra8_ssiscr_shift_t : uint8_t {   k_ra8_ssie_shift_rdfs = 0U ,   k_ra8_ssie_shift_tdes = 8U }
	SSISCR field bit positions. More...
enum	ra8_ssie_omod_t : uint8_t {   k_ra8_ssie_omod_i2s = 0U ,   k_ra8_ssie_omod_tdm = 1U ,   k_ra8_ssie_omod_monaural = 2U }
	OMOD[1:0] encoding from HUM Ch 46.2.7 table p 3091. More...
enum	ra8_ssie_frm_t : uint8_t {   k_ra8_ssie_frm_default = 0U ,   k_ra8_ssie_frm_alt1 = 1U ,   k_ra8_ssie_frm_alt2 = 2U ,   k_ra8_ssie_frm_alt3 = 3U }
	FRM[1:0] encoding from HUM Ch 46.2.1 table p 3057. More...

Functions
static volatile r_ssie_regs_t *	ra8_ssie (uint8_t channel)
	Get pointer to an SSIE channel block.

Detailed Description

Serial Sound Interface Enhanced (SSIE) register layout for the RA8D2.

The RA8D2 exposes two SSIE channels (SSIE0 and SSIE1). Each channel has an independent register window at base 0x4025_D000 with a 0x100 stride (HUM Ch 46.2.1, p 3056). The same offset map is reused by both channels and is shown by HUM Table 46.9 "Bits subject to software reset by the SSIRST bit", p 3081.

Per-channel registers:

Offset	Name	Width	Purpose
0x00	SSICR	32	Control (TEN/REN, MST, DWL, SWL ...)
0x04	SSISR	32	Status (IIRQ + over/underflow flags)
0x10	SSIFCR	32	FIFO Control (RIE, TIE, AUCKE ...)
0x14	SSIFSR	32	FIFO Status (RDF, TDE, RDC, TDC)
0x18	SSIFTDR	32	Transmit FIFO Data Register
0x1C	SSIFRDR	32	Receive FIFO Data Register
0x20	SSIOFR	32	Audio Format (OMOD, LRCONT, BCKASTP)
0x24	SSISCR	32	Status Control (TDES, RDFS)

Field bit positions are sourced from HUM Ch 46.2 register description tables (p 3056-3094) and cross-checked against the ra/fsp/src/r_ssi/r_ssi.c shift macros in the Renesas FSP sources (FSP is reference only – no code copied).

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_ssie_regs.h.

Enumeration Type Documentation

ra8_ssicr_bit_t

enum ra8_ssicr_bit_t : uint8_t

SSICR control-bit positions.

Verified against HUM Ch 46.2.1 "SSICR : Control Register" p 3056-3058 and FSP r_ssi.c SSI_PRV_SSICR_* macros.

Enumerator
k_ra8_ssie_bit_ren	REN: reception enable.
k_ra8_ssie_bit_ten	TEN: transmission enable.
k_ra8_ssie_bit_muen	MUEN: mute enable.
k_ra8_ssie_bit_ckdv0	CKDV[3:0] @ [7:4] bit clock div.
k_ra8_ssie_bit_del	DEL: serial data delay select.
k_ra8_ssie_bit_pdta	PDTA: placement data alignment.
k_ra8_ssie_bit_sdta	SDTA: serial data alignment.
k_ra8_ssie_bit_spdp	SPDP: padding polarity.
k_ra8_ssie_bit_lrckp	LRCKP: LR/FS init level + polarity.
k_ra8_ssie_bit_bckp	BCKP: bit clock polarity.
k_ra8_ssie_bit_mst	MST: controller-mode enable.
k_ra8_ssie_bit_swl0	SWL[2:0] @ [18:16] system word.
k_ra8_ssie_bit_dwl0	DWL[2:0] @ [21:19] data word.
k_ra8_ssie_bit_frm0	FRM[1:0] @ [23:22] frame words.
k_ra8_ssie_bit_iien	IIEN: idle mode IRQ enable.
k_ra8_ssie_bit_roien	ROIEN: receive overflow IRQ en.
k_ra8_ssie_bit_ruien	RUIEN: receive underflow IRQ en.
k_ra8_ssie_bit_toien	TOIEN: transmit overflow IRQ en.
k_ra8_ssie_bit_tuien	TUIEN: transmit underflow IRQ en.
k_ra8_ssie_bit_cks	CKS: controller audio-clock select.

Definition at line 80 of file ra8_ssie_regs.h.

ra8_ssicr_mask_t

enum ra8_ssicr_mask_t : uint32_t

SSICR field masks (32-bit register).

Enumerator
k_ra8_ssie_mask_ren	REN.
k_ra8_ssie_mask_ten	TEN.
k_ra8_ssie_mask_ren_ten	REN | TEN.
k_ra8_ssie_mask_muen	MUEN.
k_ra8_ssie_mask_ckdv	CKDV[3:0] @ [7:4].
k_ra8_ssie_mask_del	DEL.
k_ra8_ssie_mask_pdta	PDTA.
k_ra8_ssie_mask_sdta	SDTA.
k_ra8_ssie_mask_spdp	SPDP.
k_ra8_ssie_mask_lrckp	LRCKP.
k_ra8_ssie_mask_bckp	BCKP.
k_ra8_ssie_mask_mst	MST.
k_ra8_ssie_mask_swl	SWL[2:0] @ [18:16].
k_ra8_ssie_mask_dwl	DWL[2:0] @ [21:19].
k_ra8_ssie_mask_frm	FRM[1:0] @ [23:22].
k_ra8_ssie_mask_iien	IIEN.
k_ra8_ssie_mask_roien	ROIEN.
k_ra8_ssie_mask_ruien	RUIEN.
k_ra8_ssie_mask_toien	TOIEN.
k_ra8_ssie_mask_tuien	TUIEN.
k_ra8_ssie_mask_cks	CKS audio clock select.
k_ra8_ssie_mask_irq_all	IIEN..TUIEN aggregate IRQ.
k_ra8_ssie_mask_err_ien	ROIEN..TUIEN tx/rx err IRQs.

Definition at line 107 of file ra8_ssie_regs.h.

ra8_ssie_addr_t

enum ra8_ssie_addr_t : uintptr_t

Memory-mapped base addresses for SSIE channels.

HUM Ch 46.2.1 "SSICR : Control Register", p 3056 defines the base as SSIEn = 0x4025_D000 + 0x0100 * n (n = 0, 1).

Enumerator
k_ra8_ssie0_base_addr	SSIE0 base (full duplex).
k_ra8_ssie1_base_addr	SSIE1 base (half duplex).

Definition at line 54 of file ra8_ssie_regs.h.

ra8_ssie_frm_t

enum ra8_ssie_frm_t : uint8_t

FRM[1:0] encoding from HUM Ch 46.2.1 table p 3057.

The number of words per frame depends on OMOD; see the cross-table for valid combinations.

Enumerator
k_ra8_ssie_frm_default	2 (I2S) / 1 (Mon) / – (TDM)
k_ra8_ssie_frm_alt1	– / – / 4 (TDM-4)
k_ra8_ssie_frm_alt2	– / – / 6 (TDM-6)
k_ra8_ssie_frm_alt3	– / – / 8 (TDM-8)

Definition at line 268 of file ra8_ssie_regs.h.

ra8_ssie_limits_t

enum ra8_ssie_limits_t : uint16_t

Channel-count, FIFO depth and stride constants.

Enumerator
k_ra8_ssie_channel_count	SSIE0 + SSIE1.
k_ra8_ssie_channel_stride	Bytes between channels.
k_ra8_ssie_fifo_depth	32-stage FIFO per dir.
k_ra8_ssie_fifo_half_water	Default TX watermark.
k_ra8_ssie_fifo_block_size	DMA block stages.
k_ra8_ssie_reset_poll_max	Bounded reset poll loops.

Definition at line 63 of file ra8_ssie_regs.h.

ra8_ssie_omod_t

enum ra8_ssie_omod_t : uint8_t

OMOD[1:0] encoding from HUM Ch 46.2.7 table p 3091.

• 00b – I2S format
• 01b – TDM format
• 10b – Monaural format
• 11b – Setting prohibited

Enumerator
k_ra8_ssie_omod_i2s	RA8 ssie omod i2s.
k_ra8_ssie_omod_tdm	RA8 ssie omod tdm.
k_ra8_ssie_omod_monaural	RA8 ssie omod monaural.

Definition at line 254 of file ra8_ssie_regs.h.

ra8_ssifcr_mask_t

enum ra8_ssifcr_mask_t : uint32_t

SSIFCR FIFO control bits (HUM Ch 46.2.3, p 3077).

RTRG[5:4] and TTRG[7:6] are the FIFO request trigger thresholds used to drive RXI/TXI to the DMAC/DTC; see HUM Table 46.5 and FSP R_SSI0_SSIFCR_b.RTRG / TTRG field definitions.

Enumerator
k_ra8_ssie_mask_rfrst	RFRST receive FIFO reset.
k_ra8_ssie_mask_tfrst	TFRST transmit FIFO reset.
k_ra8_ssie_mask_rfrst_tfrst	Both FIFO reset bits.
k_ra8_ssie_mask_rie	RIE receive full IRQ.
k_ra8_ssie_mask_tie	TIE transmit empty IRQ.
k_ra8_ssie_mask_rie_tie	RIE | TIE.
k_ra8_ssie_mask_rtrg	RTRG[1:0] @ [5:4].
k_ra8_ssie_mask_ttrg	TTRG[1:0] @ [7:6].
k_ra8_ssie_mask_bsw	BSW byte-swap enable.
k_ra8_ssie_mask_ssirst	SSIRST software reset.
k_ra8_ssie_mask_aucke	AUCKE AUDIO_MCK enable.

Definition at line 163 of file ra8_ssie_regs.h.

ra8_ssifcr_shift_t

enum ra8_ssifcr_shift_t : uint8_t

SSIFCR field bit positions for RTRG / TTRG.

See HUM Ch 46.2.3 "SSIFCR : FIFO Control Register" p 3077 and FSP R_SSI0_SSIFCR_b.RTRG / TTRG (BSP header).

Enumerator
k_ra8_ssie_shift_rtrg	RTRG[1:0] starts at bit 4.
k_ra8_ssie_shift_ttrg	TTRG[1:0] starts at bit 6.

Definition at line 184 of file ra8_ssie_regs.h.

ra8_ssifsr_mask_t

enum ra8_ssifsr_mask_t : uint32_t

SSIFSR FIFO status bits (HUM Ch 46.2.4, p 3083-3084).

RDF and TDE are write-1-to-1-keep / write-0-to-clear; FSP code at p 3084 maps the only-keep encodings to the rdf_clear / tde_clear constants below.

Enumerator
k_ra8_ssie_mask_rdf	RDF receive data full.
k_ra8_ssie_mask_rdc	RDC[5:0] @ [13:8].
k_ra8_ssie_mask_tde	TDE transmit data empty.
k_ra8_ssie_mask_tdc	TDC[5:0] @ [29:24].
k_ra8_ssie_mask_rdf_clear	Keep TDE while clearing RDF.
k_ra8_ssie_mask_tde_clear	Keep RDF while clearing TDE.

Definition at line 198 of file ra8_ssie_regs.h.

ra8_ssifsr_shift_t

enum ra8_ssifsr_shift_t : uint8_t

SSIFSR field bit positions for extraction.

Enumerator
k_ra8_ssie_shift_rdc	RDC[5:0] starts at bit 8.
k_ra8_ssie_shift_tdc	TDC[5:0] starts at bit 24.

Definition at line 211 of file ra8_ssie_regs.h.

ra8_ssiofr_mask_t

enum ra8_ssiofr_mask_t : uint32_t

SSIOFR audio format bits (HUM Ch 46.2.7, p 3091).

Enumerator
k_ra8_ssie_mask_omod	OMOD[1:0] @ [1:0].
k_ra8_ssie_mask_lrcont	LRCONT continuation.
k_ra8_ssie_mask_bckastp	BCKASTP idle-stop BCK.

Definition at line 220 of file ra8_ssie_regs.h.

ra8_ssiscr_mask_t

enum ra8_ssiscr_mask_t : uint32_t

SSISCR FIFO trigger thresholds (HUM Ch 46.2.8, p 3094).

Enumerator
k_ra8_ssie_mask_rdfs	RDFS[4:0] @ [4:0].
k_ra8_ssie_mask_tdes	TDES[4:0] @ [12:8].

Definition at line 230 of file ra8_ssie_regs.h.

ra8_ssiscr_shift_t

enum ra8_ssiscr_shift_t : uint8_t

SSISCR field bit positions.

Enumerator
k_ra8_ssie_shift_rdfs	RDFS[4:0] starts at bit 0.
k_ra8_ssie_shift_tdes	TDES[4:0] starts at bit 8.

Definition at line 239 of file ra8_ssie_regs.h.

ra8_ssisr_mask_t

enum ra8_ssisr_mask_t : uint32_t

SSISR status flags (HUM Ch 46.2.2, p 3066-3067).

IDST is the live idle-status flag at bit 0 (FSP R_SSI0_SSISR_b.IDST). It is read-only and reflects the SSIE core state machine, not an interrupt latch; the latched IIRQ at bit 25 is what fires the idle interrupt.

Enumerator
k_ra8_ssie_mask_idst	IDST live idle flag (RO).
k_ra8_ssie_mask_iirq	IIRQ idle-mode flag (RO).
k_ra8_ssie_mask_roirq	ROIRQ receive overflow.
k_ra8_ssie_mask_ruirq	RUIRQ receive underflow.
k_ra8_ssie_mask_toirq	TOIRQ transmit overflow.
k_ra8_ssie_mask_tuirq	TUIRQ transmit underflow.
k_ra8_ssie_mask_err_all	ROIRQ|RUIRQ|TOIRQ|TUIRQ.
k_ra8_ssie_mask_evt_all	IIRQ + four error flags.

Definition at line 143 of file ra8_ssie_regs.h.

Function Documentation

ra8_ssie()

volatile r_ssie_regs_t * ra8_ssie ( uint8_t channel )

inlinestatic

Get pointer to an SSIE channel block.

Parameters

[in]

channel

Channel index (0 = SSIE0, 1 = SSIE1).

Returns

Volatile pointer to the channel register block, or nullptr if channel is out of range.

Definition at line 311 of file ra8_ssie_regs.h.

References k_ra8_ssie0_base_addr, k_ra8_ssie_channel_count, and k_ra8_ssie_channel_stride.

Referenced by priv_ra8_ssie_internal_regs().