ra8_ssie_regs.h

Go to the documentation of this file.

 
#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"

typedef enum : uintptr_t {
  k_ra8_ssie0_base_addr = 0x4025D000UL, 
  k_ra8_ssie1_base_addr = 0x4025D100UL, 
} ra8_ssie_addr_t;

typedef enum : uint16_t {
  k_ra8_ssie_channel_count   = 2U,     
  k_ra8_ssie_channel_stride  = 0x100U, 
  k_ra8_ssie_fifo_depth      = 32U,    
  k_ra8_ssie_fifo_half_water = 15U,    
  k_ra8_ssie_fifo_block_size = 2U,     
  k_ra8_ssie_reset_poll_max  = 32U,    
} ra8_ssie_limits_t;

typedef enum : uint8_t {
  k_ra8_ssie_bit_ren   = 0U,  
  k_ra8_ssie_bit_ten   = 1U,  
  k_ra8_ssie_bit_muen  = 3U,  
  k_ra8_ssie_bit_ckdv0 = 4U,  
  k_ra8_ssie_bit_del   = 8U,  
  k_ra8_ssie_bit_pdta  = 9U,  
  k_ra8_ssie_bit_sdta  = 10U, 
  k_ra8_ssie_bit_spdp  = 11U, 
  k_ra8_ssie_bit_lrckp = 12U, 
  k_ra8_ssie_bit_bckp  = 13U, 
  k_ra8_ssie_bit_mst   = 14U, 
  k_ra8_ssie_bit_swl0  = 16U, 
  k_ra8_ssie_bit_dwl0  = 19U, 
  k_ra8_ssie_bit_frm0  = 22U, 
  k_ra8_ssie_bit_iien  = 25U, 
  k_ra8_ssie_bit_roien = 26U, 
  k_ra8_ssie_bit_ruien = 27U, 
  k_ra8_ssie_bit_toien = 28U, 
  k_ra8_ssie_bit_tuien = 29U, 
  k_ra8_ssie_bit_cks   = 30U, 
} ra8_ssicr_bit_t;

typedef enum : uint32_t {
  k_ra8_ssie_mask_ren     = 0x00000001UL, 
  k_ra8_ssie_mask_ten     = 0x00000002UL, 
  k_ra8_ssie_mask_ren_ten = 0x00000003UL, 
  k_ra8_ssie_mask_muen    = 0x00000008UL, 
  k_ra8_ssie_mask_ckdv    = 0x000000F0UL, 
  k_ra8_ssie_mask_del     = 0x00000100UL, 
  k_ra8_ssie_mask_pdta    = 0x00000200UL, 
  k_ra8_ssie_mask_sdta    = 0x00000400UL, 
  k_ra8_ssie_mask_spdp    = 0x00000800UL, 
  k_ra8_ssie_mask_lrckp   = 0x00001000UL, 
  k_ra8_ssie_mask_bckp    = 0x00002000UL, 
  k_ra8_ssie_mask_mst     = 0x00004000UL, 
  k_ra8_ssie_mask_swl     = 0x00070000UL, 
  k_ra8_ssie_mask_dwl     = 0x00380000UL, 
  k_ra8_ssie_mask_frm     = 0x00C00000UL, 
  k_ra8_ssie_mask_iien    = 0x02000000UL, 
  k_ra8_ssie_mask_roien   = 0x04000000UL, 
  k_ra8_ssie_mask_ruien   = 0x08000000UL, 
  k_ra8_ssie_mask_toien   = 0x10000000UL, 
  k_ra8_ssie_mask_tuien   = 0x20000000UL, 
  k_ra8_ssie_mask_cks     = 0x40000000UL, 
  k_ra8_ssie_mask_irq_all = 0x3E000000UL, 
  k_ra8_ssie_mask_err_ien = 0x3C000000UL, 
} ra8_ssicr_mask_t;

typedef enum : uint32_t {
  k_ra8_ssie_mask_idst    = 0x00000001UL, 
  k_ra8_ssie_mask_iirq    = 0x02000000UL, 
  k_ra8_ssie_mask_roirq   = 0x04000000UL, 
  k_ra8_ssie_mask_ruirq   = 0x08000000UL, 
  k_ra8_ssie_mask_toirq   = 0x10000000UL, 
  k_ra8_ssie_mask_tuirq   = 0x20000000UL, 
  k_ra8_ssie_mask_err_all = 0x3C000000UL, 
  k_ra8_ssie_mask_evt_all = 0x3E000000UL, 
} ra8_ssisr_mask_t;

typedef enum : uint32_t {
  k_ra8_ssie_mask_rfrst       = 0x00000001UL, 
  k_ra8_ssie_mask_tfrst       = 0x00000002UL, 
  k_ra8_ssie_mask_rfrst_tfrst = 0x00000003UL, 
  k_ra8_ssie_mask_rie         = 0x00000004UL, 
  k_ra8_ssie_mask_tie         = 0x00000008UL, 
  k_ra8_ssie_mask_rie_tie     = 0x0000000CUL, 
  k_ra8_ssie_mask_rtrg        = 0x00000030UL, 
  k_ra8_ssie_mask_ttrg        = 0x000000C0UL, 
  k_ra8_ssie_mask_bsw         = 0x00000800UL, 
  k_ra8_ssie_mask_ssirst      = 0x00010000UL, 
  k_ra8_ssie_mask_aucke       = 0x80000000UL, 
} ra8_ssifcr_mask_t;

typedef enum : uint8_t {
  k_ra8_ssie_shift_rtrg = 4U, 
  k_ra8_ssie_shift_ttrg = 6U, 
} ra8_ssifcr_shift_t;

typedef enum : uint32_t {
  k_ra8_ssie_mask_rdf       = 0x00000001UL, 
  k_ra8_ssie_mask_rdc       = 0x00003F00UL, 
  k_ra8_ssie_mask_tde       = 0x00010000UL, 
  k_ra8_ssie_mask_tdc       = 0x3F000000UL, 
  k_ra8_ssie_mask_rdf_clear = 0x00010000UL, 
  k_ra8_ssie_mask_tde_clear = 0x00000001UL, 
} ra8_ssifsr_mask_t;

typedef enum : uint8_t {
  k_ra8_ssie_shift_rdc = 8U,  
  k_ra8_ssie_shift_tdc = 24U, 
} ra8_ssifsr_shift_t;

typedef enum : uint32_t {
  k_ra8_ssie_mask_omod    = 0x00000003UL, 
  k_ra8_ssie_mask_lrcont  = 0x00000100UL, 
  k_ra8_ssie_mask_bckastp = 0x00000200UL, 
} ra8_ssiofr_mask_t;

typedef enum : uint32_t {
  k_ra8_ssie_mask_rdfs = 0x0000001FUL, 
  k_ra8_ssie_mask_tdes = 0x00001F00UL, 
} ra8_ssiscr_mask_t;

typedef enum : uint8_t {
  k_ra8_ssie_shift_rdfs = 0U, 
  k_ra8_ssie_shift_tdes = 8U, 
} ra8_ssiscr_shift_t;

typedef enum : uint8_t {
  k_ra8_ssie_omod_i2s      = 0U, 
  k_ra8_ssie_omod_tdm      = 1U, 
  k_ra8_ssie_omod_monaural = 2U, 
} ra8_ssie_omod_t;

typedef enum : uint8_t {
  k_ra8_ssie_frm_default = 0U, 
  k_ra8_ssie_frm_alt1    = 1U, 
  k_ra8_ssie_frm_alt2    = 2U, 
  k_ra8_ssie_frm_alt3    = 3U, 
} ra8_ssie_frm_t;

typedef struct {
  volatile uint32_t SSICR;   
  volatile uint32_t SSISR;   
  volatile uint8_t  _r0[8];  
  volatile uint32_t SSIFCR;  
  volatile uint32_t SSIFSR;  
  volatile uint32_t SSIFTDR; 
  volatile uint32_t SSIFRDR; 
  volatile uint32_t SSIOFR;  
  volatile uint32_t SSISCR;  
} r_ssie_regs_t;

RA8_HW_REGISTER_ACCESS
static inline volatile r_ssie_regs_t* ra8_ssie(uint8_t channel)
{
  if ((uint16_t)channel >= k_ra8_ssie_channel_count) {
    return nullptr;
  }
  return (volatile r_ssie_regs_t*)(k_ra8_ssie0_base_addr +
                                   ((uintptr_t)channel * (uintptr_t)k_ra8_ssie_channel_stride));
}
 
#ifdef __cplusplus
}
#endif