ra8_mipi_csi_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_glcdc_regs.h" /* for k_ra8_mipi_csi_base_addr */

typedef enum : uint16_t {
  /* ---- Module info / control ----------------------------------------- */
  k_ra8_mipi_csi_off_mcg  = 0x000U, 
  k_ra8_mipi_csi_off_mct0 = 0x010U, 
  k_ra8_mipi_csi_off_mct2 = 0x018U, 
  k_ra8_mipi_csi_off_mct3 = 0x01CU, 
 
  /* ---- Reset --------------------------------------------------------- */
  k_ra8_mipi_csi_off_rtct = 0x028U, 
  k_ra8_mipi_csi_off_rtst = 0x02CU, 
 
  /* ---- EPD options --------------------------------------------------- */
  k_ra8_mipi_csi_off_epct = 0x040U, 
  k_ra8_mipi_csi_off_emct = 0x044U, 
 
  /* ---- Module-level interrupt status -------------------------------- */
  k_ra8_mipi_csi_off_mist = 0x050U, 
 
  /* ---- Receive data-type enable ------------------------------------- */
  k_ra8_mipi_csi_off_dtel = 0x060U, 
  k_ra8_mipi_csi_off_dteh = 0x064U, 
 
  /* ---- Receive status / clear / IE ---------------------------------- */
  k_ra8_mipi_csi_off_rxst = 0x070U, 
  k_ra8_mipi_csi_off_rxsc = 0x074U, 
  k_ra8_mipi_csi_off_rxie = 0x078U, 
 
  /* ---- Data lane 0 status / clear / IE ------------------------------ */
  k_ra8_mipi_csi_off_dlst0 = 0x080U, 
  k_ra8_mipi_csi_off_dlsc0 = 0x084U, 
  k_ra8_mipi_csi_off_dlie0 = 0x088U, 
 
  /* ---- Data lane 1 status / clear / IE ------------------------------ */
  k_ra8_mipi_csi_off_dlst1 = 0x090U, 
  k_ra8_mipi_csi_off_dlsc1 = 0x094U, 
  k_ra8_mipi_csi_off_dlie1 = 0x098U, 
 
  /* ---- Virtual channel 0 (others at +0x10 stride) ------------------- */
  k_ra8_mipi_csi_off_vcst0 = 0x100U, 
  k_ra8_mipi_csi_off_vcsc0 = 0x104U, 
  k_ra8_mipi_csi_off_vcie0 = 0x108U, 
 
  /* ---- Power management --------------------------------------------- */
  k_ra8_mipi_csi_off_pmst = 0x200U, 
  k_ra8_mipi_csi_off_pmsc = 0x204U, 
  k_ra8_mipi_csi_off_pmie = 0x208U, 
 
  /* ---- Generic short packet ----------------------------------------- */
  k_ra8_mipi_csi_off_gsct = 0x280U, 
  k_ra8_mipi_csi_off_gsst = 0x284U, 
  k_ra8_mipi_csi_off_gssc = 0x288U, 
  k_ra8_mipi_csi_off_gsie = 0x28CU, 
  k_ra8_mipi_csi_off_gsht = 0x290U, 
  k_ra8_mipi_csi_off_gsiu = 0x294U, 
} ra8_mipi_csi_off_t;

typedef enum : uint16_t {
  k_ra8_mipi_csi_vc_count    = 16U,    
  k_ra8_mipi_csi_vc_max      = 15U,    
  k_ra8_mipi_csi_vc_stride   = 0x10U,  
  k_ra8_mipi_csi_dl_count    = 2U,     
  k_ra8_mipi_csi_dl_max      = 1U,     
  k_ra8_mipi_csi_dl_stride   = 0x10U,  
  k_ra8_mipi_csi_data_lanes  = 2U,     
  k_ra8_mipi_csi_short_fifo  = 16U,    
  k_ra8_mipi_csi_window_size = 0x298U, 
} ra8_mipi_csi_limits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_mcg_ver_mask   = 0x0000000FUL, 
  k_ra8_mipi_csi_mcg_sdln_mask  = 0x00000F00UL, 
  k_ra8_mipi_csi_mcg_sdln_shift = 8U,           
  k_ra8_mipi_csi_mcg_gsnm_mask  = 0x00FF0000UL, 
  k_ra8_mipi_csi_mcg_gsnm_shift = 16U,          
} ra8_mipi_csi_mcg_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_mct0_vdln_mask   = 0x0000000FUL, 
  k_ra8_mipi_csi_mct0_zlmd_mask   = 0x00010000UL, 
  k_ra8_mipi_csi_mct0_edmd_mask   = 0x00020000UL, 
  k_ra8_mipi_csi_mct0_rvmd_mask   = 0x00080000UL, 
  k_ra8_mipi_csi_mct0_grmd_mask   = 0x00100000UL, 
  k_ra8_mipi_csi_mct0_eccv13_mask = 0x01000000UL, 
  k_ra8_mipi_csi_mct0_lfsren_mask = 0x02000000UL, 
} ra8_mipi_csi_mct0_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_mct2_frrclk_mask  = 0x000001FFUL, 
  k_ra8_mipi_csi_mct2_frrclk_shift = 0U,           
  k_ra8_mipi_csi_mct2_frrskw_mask  = 0x01FF0000UL, 
  k_ra8_mipi_csi_mct2_frrskw_shift = 16U,          
} ra8_mipi_csi_mct2_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_mct3_rxen_mask = 0x00000001UL, 
} ra8_mipi_csi_mct3_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_rtct_vsrst_mask = 0x00000001UL, 
} ra8_mipi_csi_rtct_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_rtst_vsrsts_mask = 0x00000001UL, 
} ra8_mipi_csi_rtst_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_epct_slp_mask   = 0x00007FFFUL, 
  k_ra8_mipi_csi_epct_slp_shift  = 0U,           
  k_ra8_mipi_csi_epct_epdop_mask = 0x00008000UL, 
  k_ra8_mipi_csi_epct_ssp_mask   = 0x7FFF0000UL, 
  k_ra8_mipi_csi_epct_ssp_shift  = 16U,          
  k_ra8_mipi_csi_epct_epden_mask = 0x80000000UL, 
} ra8_mipi_csi_epct_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_emct_vlsien_mask  = 0x00000030UL, 
  k_ra8_mipi_csi_emct_vlsien_shift = 4U,           
  k_ra8_mipi_csi_emct_eotpen_mask  = 0x00000040UL, 
} ra8_mipi_csi_emct_bits_t;

typedef enum : uint8_t {
  k_ra8_mipi_csi_vlsien_fixed = 0U, 
  k_ra8_mipi_csi_vlsien_x1    = 1U, 
  k_ra8_mipi_csi_vlsien_x2    = 2U, 
  k_ra8_mipi_csi_vlsien_x4    = 3U, 
} ra8_mipi_csi_vlsien_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_mist_dl0s_mask = 0x00000001UL, 
  k_ra8_mipi_csi_mist_dl1s_mask = 0x00000002UL, 
  k_ra8_mipi_csi_mist_pms_mask  = 0x00000100UL, 
  k_ra8_mipi_csi_mist_gsts_mask = 0x00000200UL, 
  k_ra8_mipi_csi_mist_rxs_mask  = 0x00000400UL, 
  k_ra8_mipi_csi_mist_vc_mask   = 0xFFFF0000UL, 
  k_ra8_mipi_csi_mist_vc_shift  = 16U,          
} ra8_mipi_csi_mist_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_dtel_reserved_low_mask = 0x0000000FUL, 
  k_ra8_mipi_csi_dtel_eot_mask          = 0x00000010UL, 
  k_ra8_mipi_csi_dtel_gsp1_mask         = 0x00000100UL, 
  k_ra8_mipi_csi_dtel_gsp2_mask         = 0x00000200UL, 
  k_ra8_mipi_csi_dtel_gsp3_mask         = 0x00000400UL, 
  k_ra8_mipi_csi_dtel_gsp4_mask         = 0x00000800UL, 
  k_ra8_mipi_csi_dtel_gsp5_mask         = 0x00001000UL, 
  k_ra8_mipi_csi_dtel_gsp6_mask         = 0x00002000UL, 
  k_ra8_mipi_csi_dtel_gsp7_mask         = 0x00004000UL, 
  k_ra8_mipi_csi_dtel_gsp8_mask         = 0x00008000UL, 
  k_ra8_mipi_csi_dtel_gsp_all_mask      = 0x0000FF00UL, 
  k_ra8_mipi_csi_dtel_yuv422_8_mask     = 0x40000000UL, 
  k_ra8_mipi_csi_dtel_yuv422_10_mask    = 0x80000000UL, 
} ra8_mipi_csi_dt_low_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_dteh_rgb888_mask = 0x00000010UL, 
  k_ra8_mipi_csi_dteh_raw8_mask   = 0x00000400UL, 
} ra8_mipi_csi_dt_high_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_rxst_frm_mask     = 0x0000FFFFUL, 
  k_ra8_mipi_csi_rxst_ract_mask    = 0x00010000UL, 
  k_ra8_mipi_csi_rxst_ractdet_mask = 0x00020000UL, 
} ra8_mipi_csi_rxst_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_rxsc_ractdetc_mask = 0x00020000UL, 
} ra8_mipi_csi_rxsc_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_rxie_ractdete_mask = 0x00020000UL, 
} ra8_mipi_csi_rxie_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_dlst_esh_mask = 0x00000001UL, 
  k_ra8_mipi_csi_dlst_ess_mask = 0x00000002UL, 
  k_ra8_mipi_csi_dlst_ect_mask = 0x00000004UL, 
  k_ra8_mipi_csi_dlst_ees_mask = 0x00000008UL, 
  k_ra8_mipi_csi_dlst_eul_mask = 0x00010000UL, 
  k_ra8_mipi_csi_dlst_rul_mask = 0x00020000UL, 
  k_ra8_mipi_csi_dlst_ulp_mask = 0x01000000UL, 
  k_ra8_mipi_csi_dlst_w1c_mask = 0x0003000FUL, 
} ra8_mipi_csi_dlst_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_dlsc_eshc_mask = 0x00000001UL, 
  k_ra8_mipi_csi_dlsc_essc_mask = 0x00000002UL, 
  k_ra8_mipi_csi_dlsc_ectc_mask = 0x00000004UL, 
  k_ra8_mipi_csi_dlsc_eesc_mask = 0x00000008UL, 
  k_ra8_mipi_csi_dlsc_eulc_mask = 0x00010000UL, 
  k_ra8_mipi_csi_dlsc_rulc_mask = 0x00020000UL, 
  k_ra8_mipi_csi_dlsc_all_mask  = 0x0003000FUL, 
} ra8_mipi_csi_dlsc_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_dlie_eshe_mask = 0x00000001UL, 
  k_ra8_mipi_csi_dlie_esse_mask = 0x00000002UL, 
  k_ra8_mipi_csi_dlie_ecte_mask = 0x00000004UL, 
  k_ra8_mipi_csi_dlie_eese_mask = 0x00000008UL, 
  k_ra8_mipi_csi_dlie_eule_mask = 0x00010000UL, 
  k_ra8_mipi_csi_dlie_rule_mask = 0x00020000UL, 
  k_ra8_mipi_csi_dlie_all_mask  = 0x0003000FUL, 
} ra8_mipi_csi_dlie_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_vcst_mlf_mask = 0x00000001UL, 
  k_ra8_mipi_csi_vcst_ecd_mask = 0x00000002UL, 
  k_ra8_mipi_csi_vcst_crc_mask = 0x00000004UL, 
  k_ra8_mipi_csi_vcst_ide_mask = 0x00000008UL, 
  k_ra8_mipi_csi_vcst_wce_mask = 0x00000010UL, 
  k_ra8_mipi_csi_vcst_ecc_mask = 0x00000020UL, 
  k_ra8_mipi_csi_vcst_ecn_mask = 0x00000040UL, 
  k_ra8_mipi_csi_vcst_frs_mask = 0x00000100UL, 
  k_ra8_mipi_csi_vcst_frd_mask = 0x00000200UL, 
  k_ra8_mipi_csi_vcst_ovf_mask = 0x00010000UL, 
  k_ra8_mipi_csi_vcst_fsr_mask = 0x01000000UL, 
  k_ra8_mipi_csi_vcst_fer_mask = 0x02000000UL, 
  k_ra8_mipi_csi_vcst_lsr_mask = 0x04000000UL, 
  k_ra8_mipi_csi_vcst_ler_mask = 0x08000000UL, 
  k_ra8_mipi_csi_vcst_etr_mask = 0x10000000UL, 
  k_ra8_mipi_csi_vcst_generic_err_mask = 0x00000003UL,
} ra8_mipi_csi_vcst_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_vcsc_mlfc_mask   = 0x00000001UL, 
  k_ra8_mipi_csi_vcsc_ecdc_mask   = 0x00000002UL, 
  k_ra8_mipi_csi_vcsc_crcc_mask   = 0x00000004UL, 
  k_ra8_mipi_csi_vcsc_idec_mask   = 0x00000008UL, 
  k_ra8_mipi_csi_vcsc_wcec_mask   = 0x00000010UL, 
  k_ra8_mipi_csi_vcsc_eccc_mask   = 0x00000020UL, 
  k_ra8_mipi_csi_vcsc_ecnc_mask   = 0x00000040UL, 
  k_ra8_mipi_csi_vcsc_frsc_mask   = 0x00000100UL, 
  k_ra8_mipi_csi_vcsc_frdc_mask   = 0x00000200UL, 
  k_ra8_mipi_csi_vcsc_amlfc_mask  = 0x00004000UL, 
  k_ra8_mipi_csi_vcsc_aecdc_mask  = 0x00008000UL, 
  k_ra8_mipi_csi_vcsc_ovfc_mask   = 0x00010000UL, 
  k_ra8_mipi_csi_vcsc_fsrc_mask   = 0x01000000UL, 
  k_ra8_mipi_csi_vcsc_ferc_mask   = 0x02000000UL, 
  k_ra8_mipi_csi_vcsc_lsrc_mask   = 0x04000000UL, 
  k_ra8_mipi_csi_vcsc_lerc_mask   = 0x08000000UL, 
  k_ra8_mipi_csi_vcsc_etrc_mask   = 0x10000000UL, 
  k_ra8_mipi_csi_vcsc_per_vc_mask = 0x1F01037FUL, 
} ra8_mipi_csi_vcsc_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_vcie_mlfe_mask = 0x00000001UL, 
  k_ra8_mipi_csi_vcie_ecde_mask = 0x00000002UL, 
  k_ra8_mipi_csi_vcie_crce_mask = 0x00000004UL, 
  k_ra8_mipi_csi_vcie_idee_mask = 0x00000008UL, 
  k_ra8_mipi_csi_vcie_wcee_mask = 0x00000010UL, 
  k_ra8_mipi_csi_vcie_ecce_mask = 0x00000020UL, 
  k_ra8_mipi_csi_vcie_ecne_mask = 0x00000040UL, 
  k_ra8_mipi_csi_vcie_frse_mask = 0x00000100UL, 
  k_ra8_mipi_csi_vcie_frde_mask = 0x00000200UL, 
  k_ra8_mipi_csi_vcie_ovfe_mask = 0x00010000UL, 
  k_ra8_mipi_csi_vcie_fsre_mask = 0x01000000UL, 
  k_ra8_mipi_csi_vcie_fere_mask = 0x02000000UL, 
  k_ra8_mipi_csi_vcie_lsre_mask = 0x04000000UL, 
  k_ra8_mipi_csi_vcie_lere_mask = 0x08000000UL, 
  k_ra8_mipi_csi_vcie_etre_mask = 0x10000000UL, 
  k_ra8_mipi_csi_vcie_all_mask  = 0x1F01037FUL, 
} ra8_mipi_csi_vcie_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_pmst_dsx_mask  = 0x00000001UL, 
  k_ra8_mipi_csi_pmst_dsn_mask  = 0x00000002UL, 
  k_ra8_mipi_csi_pmst_csx_mask  = 0x00000004UL, 
  k_ra8_mipi_csi_pmst_csn_mask  = 0x00000008UL, 
  k_ra8_mipi_csi_pmst_dux_mask  = 0x00000010UL, 
  k_ra8_mipi_csi_pmst_dun_mask  = 0x00000020UL, 
  k_ra8_mipi_csi_pmst_cux_mask  = 0x00000040UL, 
  k_ra8_mipi_csi_pmst_cun_mask  = 0x00000080UL, 
  k_ra8_mipi_csi_pmst_clss_mask = 0x00004000UL, 
  k_ra8_mipi_csi_pmst_clul_mask = 0x00008000UL, 
  k_ra8_mipi_csi_pmst_dlss_mask = 0x00030000UL, 
  k_ra8_mipi_csi_pmst_dlul_mask = 0x03000000UL, 
  k_ra8_mipi_csi_pmst_w1c_mask  = 0x000000FFUL, 
} ra8_mipi_csi_pmst_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_pmsc_dsxc_mask = 0x00000001UL, 
  k_ra8_mipi_csi_pmsc_dsnc_mask = 0x00000002UL, 
  k_ra8_mipi_csi_pmsc_csxc_mask = 0x00000004UL, 
  k_ra8_mipi_csi_pmsc_csnc_mask = 0x00000008UL, 
  k_ra8_mipi_csi_pmsc_duxc_mask = 0x00000010UL, 
  k_ra8_mipi_csi_pmsc_dunc_mask = 0x00000020UL, 
  k_ra8_mipi_csi_pmsc_cuxc_mask = 0x00000040UL, 
  k_ra8_mipi_csi_pmsc_cunc_mask = 0x00000080UL, 
  k_ra8_mipi_csi_pmsc_all_mask  = 0x000000FFUL, 
} ra8_mipi_csi_pmsc_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_pmie_dsxe_mask = 0x00000001UL, 
  k_ra8_mipi_csi_pmie_dsne_mask = 0x00000002UL, 
  k_ra8_mipi_csi_pmie_csxe_mask = 0x00000004UL, 
  k_ra8_mipi_csi_pmie_csne_mask = 0x00000008UL, 
  k_ra8_mipi_csi_pmie_duxe_mask = 0x00000010UL, 
  k_ra8_mipi_csi_pmie_dune_mask = 0x00000020UL, 
  k_ra8_mipi_csi_pmie_cuxe_mask = 0x00000040UL, 
  k_ra8_mipi_csi_pmie_cune_mask = 0x00000080UL, 
  k_ra8_mipi_csi_pmie_all_mask  = 0x000000FFUL, 
} ra8_mipi_csi_pmie_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_gsct_shth_mask  = 0x0000007FUL, 
  k_ra8_mipi_csi_gsct_shth_shift = 0U,           
  k_ra8_mipi_csi_gsct_gfif_mask  = 0x00010000UL, 
  k_ra8_mipi_csi_gsct_shth_max   = 0x0FUL,       
} ra8_mipi_csi_gsct_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_gsst_gne_mask   = 0x00000001UL, 
  k_ra8_mipi_csi_gsst_gth_mask   = 0x00000002UL, 
  k_ra8_mipi_csi_gsst_gov_mask   = 0x00000010UL, 
  k_ra8_mipi_csi_gsst_pnum_mask  = 0x0000FF00UL, 
  k_ra8_mipi_csi_gsst_pnum_shift = 8U,           
  k_ra8_mipi_csi_gsst_gcd_mask   = 0x00010000UL, 
  k_ra8_mipi_csi_gsst_strds_mask = 0x00020000UL, 
} ra8_mipi_csi_gsst_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_gssc_govc_mask = 0x00000010UL, 
} ra8_mipi_csi_gssc_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_gsie_gnee_mask = 0x00000001UL, 
  k_ra8_mipi_csi_gsie_gthe_mask = 0x00000002UL, 
  k_ra8_mipi_csi_gsie_gove_mask = 0x00000010UL, 
  k_ra8_mipi_csi_gsie_all_mask  = 0x00000013UL, 
} ra8_mipi_csi_gsie_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_gsht_spdt_mask  = 0x0000FFFFUL, 
  k_ra8_mipi_csi_gsht_spdt_shift = 0U,           
  k_ra8_mipi_csi_gsht_dtyp_mask  = 0x003F0000UL, 
  k_ra8_mipi_csi_gsht_dtyp_shift = 16U,          
  k_ra8_mipi_csi_gsht_spvc_mask  = 0x0F000000UL, 
  k_ra8_mipi_csi_gsht_spvc_shift = 24U,          
} ra8_mipi_csi_gsht_bits_t;

typedef enum : uint32_t {
  k_ra8_mipi_csi_gsiu_finc_mask  = 0x00000001UL, 
  k_ra8_mipi_csi_gsiu_gfclr_mask = 0x00000100UL, 
  k_ra8_mipi_csi_gsiu_gfen_mask  = 0x00010000UL, 
} ra8_mipi_csi_gsiu_bits_t;

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_mipi_csi_reg32(ra8_mipi_csi_off_t off)
{
  return (volatile uint32_t*)(k_ra8_mipi_csi_base_addr + (uint16_t)off);
}

static inline ra8_mipi_csi_off_t ra8_mipi_csi_vc_off(ra8_mipi_csi_off_t base, uint8_t vc)
{
  /* Computed stride offset is a valid HUM-defined VC register location, not a
   * literal enumerator -- the analyzer can't see that. */
  return (ra8_mipi_csi_off_t)((uint16_t)base + ((uint16_t)vc * k_ra8_mipi_csi_vc_stride));
}

static inline ra8_mipi_csi_off_t ra8_mipi_csi_dl_off(ra8_mipi_csi_off_t base, uint8_t lane)
{
  return (ra8_mipi_csi_off_t)((uint16_t)base + ((uint16_t)lane * k_ra8_mipi_csi_dl_stride));
}
 
#ifdef __cplusplus
}
#endif