Flash / MRAM controller register layout for the Renesas RA8D2. More...

#include <stdint.h>

Include dependency graph for ra8_flash_regs.h:

This graph shows which files directly or indirectly include this file:

Enumerations
enum	ra8_flash_map_t : uintptr_t { k_ra8_flash_code_start = 0x02000000UL , k_ra8_flash_code_size = 0x00100000UL , k_ra8_flash_extra_start = 0x02E07600UL , k_ra8_flash_extra_size = 0x00010400UL , k_ra8_flash_gpotp_start = 0x02E076A0UL , k_ra8_flash_gpotp_size = 0x00000060UL , k_ra8_flash_extra_locked_start = 0x02E17700UL , k_ra8_flash_ofs_start = 0x02C9F000UL , k_ra8_flash_ofs_size = 0x00001000UL , k_ra8_flash_ofs_arccs_addr = 0x02E17932UL , k_ra8_flash_ofs_arc_sec_addr = 0x02F27E00UL , k_ra8_flash_ofs_arc_nsec_addr = 0x02F27E08UL }
	Address bounds of the user-visible MRAM windows. More...
enum	ra8_mram_base_addr_t : uintptr_t { k_ra8_mram_base_addr = 0x4013C000UL , k_ra8_mram_base_addr_ns = 0x5013C000UL , k_ra8_mram_cmd_base = 0x40120000UL }
	MRMS controller base addresses. More...
enum	ra8_mram_off_t : uint16_t { k_ra8_mram_off_mrcpfb = 0x0000U , k_ra8_mram_off_mrcfreq = 0x0004U , k_ra8_mram_off_mrefreq = 0x0008U , k_ra8_mram_off_mrcdecc = 0x0010U , k_ra8_mram_off_mrcraeint = 0x0014U , k_ra8_mram_off_mrcraes = 0x0018U , k_ra8_mram_off_mrcrtea = 0x001CU , k_ra8_mram_off_mrcrdea = 0x0020U , k_ra8_mram_off_mreraint = 0x0034U , k_ra8_mram_off_mreraes = 0x0038U , k_ra8_mram_off_mrertea = 0x003CU , k_ra8_mram_off_mrerdea = 0x0040U , k_ra8_mram_off_msar = 0x0100U , k_ra8_mram_off_mrezs = 0x0400U , k_ra8_mram_off_mrezc = 0x0404U , k_ra8_mram_off_mastat = 0x2010U , k_ra8_mram_off_mpaeint = 0x2014U , k_ra8_mram_off_mrdyie = 0x2018U , k_ra8_mram_off_msaddr = 0x2030U , k_ra8_mram_off_mcntselr = 0x2048U , k_ra8_mram_off_mcntdtr0 = 0x204CU , k_ra8_mram_off_mcntdtr1 = 0x2050U , k_ra8_mram_off_mctrcntr = 0x2060U , k_ra8_mram_off_mctrlsr = 0x2064U , k_ra8_mram_off_mctrstatr = 0x206CU , k_ra8_mram_off_mstatr = 0x2080U , k_ra8_mram_off_mentryr = 0x2084U , k_ra8_mram_off_msuinitr = 0x208CU , k_ra8_mram_off_mcmdr = 0x20A0U , k_ra8_mram_off_msuasmon = 0x20DCU , k_ra8_mram_off_msuacr = 0x20E8U , k_ra8_mram_off_mrpsc = 0x2800U , k_ra8_mram_off_mrcpc0 = 0x3000U , k_ra8_mram_off_mrcpc1 = 0x3004U , k_ra8_mram_off_mrcbprot0 = 0x3008U , k_ra8_mram_off_mrcbprot1 = 0x300CU , k_ra8_mram_off_mrcps = 0x3010U , k_ra8_mram_off_mrcpaeint = 0x3014U , k_ra8_mram_off_mrcpea = 0x3018U , k_ra8_mram_off_mrcflr = 0x3030U , k_ra8_mram_off_mrceecc = 0x3804U }
	Byte offsets into the MRMS register window. More...
enum	ra8_mrcps_mask_t : uint8_t { k_ra8_mrcps_mask_prgerrc = 0x01U , k_ra8_mrcps_mask_eccerrc = 0x02U , k_ra8_mrcps_mask_abufemp = 0x20U , k_ra8_mrcps_mask_abuffull = 0x40U , k_ra8_mrcps_mask_prgbsyc = 0x80U , k_ra8_mrcps_mask_errors = 0x03U }
	Bit masks for the MRCPS Code MRAM Program Status Register. More...
enum	ra8_mrceecc_mask_t : uint16_t { k_ra8_mrceecc_mask_eccen = 0x0001U , k_ra8_mrceecc_key_shift = 0xC000U }
	Field masks and key for the MRCEECC ECC encoder control. More...
enum	ra8_mrcdecc_mask_t : uint16_t { k_ra8_mrcdecc_mask_dececen = 0x0002U , k_ra8_mrcdecc_key_shift = 0x8C00U }
	Field masks and key for the MRCDECC ECC decoder control. More...
enum	ra8_mrcraes_mask_t : uint8_t { k_ra8_mrcraes_mask_decerrc = 0x01U , k_ra8_mrcraes_mask_tederrc = 0x02U , k_ra8_mrcraes_mask_any = 0x03U }
	MRCRAES / MRERAES read-access error status bits. More...
enum	ra8_mrcraeint_mask_t : uint8_t { k_ra8_mrcraeint_mask_intenbdc = 0x01U , k_ra8_mrcraeint_mask_intenbtc = 0x02U }
	MRCRAEINT / MRERAINT IRQ-enable bits. More...
enum	ra8_mrcpaeint_mask_t : uint8_t { k_ra8_mrcpaeint_mask_mrcaeie = 0x80U }
	MRCPAEINT field mask. More...
enum	ra8_mpaeint_mask_t : uint8_t { k_ra8_mpaeint_mask_mreaeie = 0x08U , k_ra8_mpaeint_mask_cmdlkie = 0x10U }
	MPAEINT field masks (extra MRAM access-error IRQ enable). More...
enum	ra8_mrdyie_mask_t : uint8_t { k_ra8_mrdyie_mask_mrdyie = 0x01U }
	MRDYIE field mask. More...
enum	ra8_mastat_mask_t : uint8_t { k_ra8_mastat_mask_mreae = 0x08U , k_ra8_mastat_mask_cmdlk = 0x10U }
	MASTAT field masks. More...
enum	ra8_mrezs_mask_t : uint8_t { k_ra8_mrezs_mask_whukzf = 0x01U , k_ra8_mrezs_mask_whukexe = 0x02U }
	MREZS field masks (zeroization status). More...
enum	ra8_mrezc_t : uint16_t { k_ra8_mrezc_full_zero = 0xA505U }
	MREZC keyed control words (zeroization). More...
enum	ra8_mentryr_t : uint16_t { k_ra8_mentryr_pe_enter = 0xAA80U , k_ra8_mentryr_read_mode = 0xAA00U , k_ra8_mentryr_mask_pe_mode = 0x0080U , k_ra8_mentryr_mask_pcka = 0x0040U , k_ra8_mentryr_pe_pause = 0xAAC0U , k_ra8_mentryr_pe_resume = 0xAA80U }
	Keyed values and field masks for the MENTRYR P/E entry register. More...
enum	ra8_msuacr_t : uint16_t { k_ra8_msuacr_key = 0x6600U , k_ra8_msuacr_swap_default = 0x0000U , k_ra8_msuacr_swap_alternate = 0x0001U }
	Keyed values for MSUACR start-up swap. More...
enum	ra8_msuasmon_mask_t : uint32_t { k_ra8_msuasmon_mask_fspr = 0x00008000UL , k_ra8_msuasmon_mask_btflg = 0x80000000UL }
	MSUASMON read-only field masks. More...
enum	ra8_msuinitr_t : uint16_t { k_ra8_msuinitr_full_init = 0xAA01U , k_ra8_msuinitr_mask_suinit = 0x0001U }
	Keyed value + field mask for MSUINITR. More...
enum	ra8_mcmdr_mask_t : uint16_t { k_ra8_mcmdr_mask_pcmdr = 0x00FFU , k_ra8_mcmdr_mask_cmdr = 0xFF00U , k_ra8_mcmdr_mask_cmd_progress = 0xFFFFU }
	MCMDR field masks (MACI command status snapshot). More...
enum	ra8_mstatr_mask_t : uint32_t { k_ra8_mstatr_mask_cfgseterr = 0x00000020UL , k_ra8_mstatr_mask_prgerr = 0x00001000UL , k_ra8_mstatr_mask_ilglerr = 0x00004000UL , k_ra8_mstatr_mask_mrdy = 0x00008000UL , k_ra8_mstatr_mask_tzferr = 0x00080000UL , k_ra8_mstatr_mask_oterr = 0x00100000UL , k_ra8_mstatr_mask_secerr = 0x00200000UL , k_ra8_mstatr_mask_ilgcomerr = 0x00800000UL , k_ra8_mstatr_mask_any_err = 0x00B85020UL }
	MSTATR field masks (extra-MRAM status flags). More...
enum	ra8_mrpsc_mask_t : uint8_t { k_ra8_mrpsc_mask_mhspen = 0x01U }
	MRPSC field masks (high-speed program enable). More...
enum	ra8_mrcpc0_t : uint16_t { k_ra8_mrcpc0_key_enable = 0x8601U , k_ra8_mrcpc0_key_disable = 0x8600U }
	Keyed values for MRCPC0 (non-secure program-gate). More...
enum	ra8_mrcpc1_t : uint16_t { k_ra8_mrcpc1_key_enable = 0x6801U , k_ra8_mrcpc1_key_disable = 0x6800U }
	Keyed values for MRCPC1 (secure program-gate). More...
enum	ra8_mrcbprot0_t : uint16_t { k_ra8_mrcbprot0_key_lock = 0x8800U , k_ra8_mrcbprot0_key_unlock = 0x8801U }
	Keyed values for MRCBPROT0 (non-secure block-protection cancel). More...
enum	ra8_mrcbprot1_t : uint16_t { k_ra8_mrcbprot1_key_lock = 0x4400U , k_ra8_mrcbprot1_key_unlock = 0x4401U }
	Keyed values for MRCBPROT1 (secure block-protection cancel). More...
enum	ra8_mrcflr_t : uint16_t { k_ra8_mrcflr_key_flush = 0xC301U }
	Keyed value for MRCFLR (write-buffer flush). More...
enum	ra8_mctrcntr_t : uint16_t { k_ra8_mctrcntr_key = 0xA500U , k_ra8_mctrcntr_mask_start = 0x0001U }
	Keyed values + masks for MCTRCNTR. More...
enum	ra8_mctrlsr_mask_t : uint8_t { k_ra8_mctrlsr_mask_list_sel = 0x07U }
	MCTRLSR field mask (transfer-list select). More...
enum	ra8_mctrstatr_mask_t : uint16_t { k_ra8_mctrstatr_mask_busy = 0x0001U , k_ra8_mctrstatr_mask_done = 0x0004U , k_ra8_mctrstatr_mask_err = 0x00F8U }
	MCTRSTATR field masks. More...
enum	ra8_mcntselr_t : uint8_t { k_ra8_mcntselr_sec = 1U , k_ra8_mcntselr_oembl = 2U , k_ra8_mcntselr_nsec_0 = 4U , k_ra8_mcntselr_mask = 0x07U }
	MCNTSELR field-value codes for the four counter families. More...
enum	ra8_arc_limits_t : uint32_t { k_ra8_arc_sec_max_bits = 64UL , k_ra8_arc_oembl_max_bits = 64UL , k_ra8_arc_nsec_single = 256UL , k_ra8_arc_nsec_multiple = 64UL , k_ra8_arc_arccs_mask = 0x03UL , k_ra8_arc_arcns_single = 1UL }
	Per-counter bit limits and ARCCS field masks. More...
enum	ra8_maci_cmd_t : uint8_t { k_ra8_maci_cmd_status_clear = 0x50U , k_ra8_maci_cmd_forced_stop = 0xB3U , k_ra8_maci_cmd_program = 0xE8U , k_ra8_maci_cmd_config_set = 0x40U , k_ra8_maci_cmd_word_count_n = 0x08U , k_ra8_maci_cmd_increment_counter = 0x35U , k_ra8_maci_cmd_read_counter = 0x39U , k_ra8_maci_cmd_final = 0xD0U }
	MACI command opcodes streamed through the MACI command-issuing area. More...
enum	ra8_msaddr_t : uint32_t { k_ra8_msaddr_config_set_startup = 0x02C9F070UL , k_ra8_msaddr_ofs_sas = 0x02C9F074UL }
	Well-known MSADDR targets for configuration-set writes. More...
enum	ra8_mram_data_const_t : uint32_t { k_ra8_mram_write_size_bytes = 32UL , k_ra8_mram_block_size_bytes = 32UL , k_ra8_mram_config_set_word_count = 8UL , k_ra8_mram_config_set_bytes = 16UL , k_ra8_mram_arc_max_words = 16UL }
	Sizes used by the driver when chunking writes / counter reads. More...

Functions
static volatile uint8_t *	ra8_mram_reg8 (uint16_t off)
	Pointer to a byte-wide MRMS register at offset off.
static volatile uint16_t *	ra8_mram_reg16 (uint16_t off)
	Pointer to a halfword-wide MRMS register at offset off.
static volatile uint32_t *	ra8_mram_reg32 (uint16_t off)
	Pointer to a word-wide MRMS register at offset off.
static volatile uint8_t *	ra8_mram_cmd8 (void)
	Pointer to the MACI command-issuing area, byte-wide.
static volatile uint16_t *	ra8_mram_cmd16 (void)
	Pointer to the MACI command-issuing area, halfword-wide.

Detailed Description

Flash / MRAM controller register layout for the Renesas RA8D2.

On RA8D2 the primary non-volatile code memory is MRAM, not traditional NOR flash, but the controller interface follows the RA "MRMS" IP. Writes to code-MRAM use a small store-window plus a keyed flush; updates to anti-rollback counters, the start-up area and other configuration-set words go through the MACI command sequencer; reads of either region are transparent.

All register offsets, field masks and key codes here are derived from the Hardware User's Manual:

Chapter 7 "Option-Setting Memory" pages 278..299
Chapter 59 "MRAM" pages 3542..3625

The companion driver (libs/ra8_hal/src/ra8_flash.c) cites the exact HUM page each time it pokes one of these registers. That keeps the math here a passive layout description: all policy lives in the driver.

Note: FSP names a few of these registers slightly differently (e.g. ECCBYPC vs ECCEN); we use the HUM names wherever they differ. References to FSP source files in comments are pointers, never copies of the FSP code.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_flash_regs.h.

Enumeration Type Documentation

◆ ra8_arc_limits_t

enum ra8_arc_limits_t : uint32_t

Per-counter bit limits and ARCCS field masks.

Values come from BSP_FEATURE_FLASH_ARC_*_MAX_COUNT in the FSP RA8D1/RA8T2 BSP feature header (the RA8D2 inherits the same MRAM macro). HUM Ch 7.2.21 p 296 fixes the ARCCS.ARCNS encoding.

Enumerator
k_ra8_arc_sec_max_bits	RA8 arc sec maximum bits.
k_ra8_arc_oembl_max_bits	RA8 arc oembl maximum bits.
k_ra8_arc_nsec_single	RA8 arc nsec single.
k_ra8_arc_nsec_multiple	RA8 arc nsec multiple.
k_ra8_arc_arccs_mask	RA8 arc arccs mask.
k_ra8_arc_arcns_single	RA8 arc arcns single.

Definition at line 615 of file ra8_flash_regs.h.

◆ ra8_flash_map_t

enum ra8_flash_map_t : uintptr_t

Address bounds of the user-visible MRAM windows.

The code-MRAM lives at 0x02000000 and is 1 MiB. The RA8D2 has no general-purpose data-flash / EEPROM array: the only MRAM area the MACI Program command (0xE8) can target is the extra-MRAM option-setting / OTP window at 0x02E07600..0x02E179F0. Every address enumerated by HUM Ch 59.7.4.5 Table 59.15 lies in that span (FSBL, code certificate, general-purpose OTP, PBPS, POFSPS, REVOKE, HUK-zeroize enable, anti-rollback counter). The previously-declared 0x27000000 "data flash" base is an RA-family assumption this part does not honour (writing it faults, ILGCOMERR|ILGLERR – issue #397). Anti-rollback counters and the start-up area-select fuse live in the Option-Setting Memory window starting at 0x02C9F000.

Enumerator
k_ra8_flash_code_start	Start of code MRAM region.
k_ra8_flash_code_size	1 MiB of code MRAM.
k_ra8_flash_extra_start	First legal Program target (FSBL setting).
k_ra8_flash_extra_size	Covers through 0x02E179F0 (last, reserved).
k_ra8_flash_gpotp_start	GPOTP0.
k_ra8_flash_gpotp_size	24 words (GPOTP0..GPOTP23).
k_ra8_flash_extra_locked_start	First permanent-OTP structure.
k_ra8_flash_ofs_start	Start of OFS config_set window.
k_ra8_flash_ofs_size	4 KiB OFS block.
k_ra8_flash_ofs_arccs_addr	RA8 flash ofs arccs address.
k_ra8_flash_ofs_arc_sec_addr	RA8 flash ofs arc sec address.
k_ra8_flash_ofs_arc_nsec_addr	RA8 flash ofs arc nsec address.

Definition at line 63 of file ra8_flash_regs.h.

◆ ra8_maci_cmd_t

enum ra8_maci_cmd_t : uint8_t

MACI command opcodes streamed through the MACI command-issuing area.

Each value is the literal opcode the extra-MRAM sequencer expects as the first byte written to the MACI command-issuing area (HUM Ch 59.7.4 p 3591.. 3597). The two data-carrying commands share one byte-stream shape – <opener>, N, <N halfwords>, 0xD0 – and differ ONLY in the opener:

Program (0xE8) programs the extra-MRAM data area excluding the configuration area (HUM Ch 59.7.4.5 "Program Command" Figure 59.13 p 3591..3592). This is the correct opener for extra-MRAM data writes.
Configuration Set (0x40) programs the OFS configuration words used by the security / safety functions – BTFLG, ARC settings, etc. (HUM Ch 59.7.4.8 "Configuration Set Command" p 3594..3595). It is NOT a substitute for Program: issuing it against the plain extra-MRAM data area raises MSTATR.CFGSETERR and leaves the target un-programmed.

N (k_ra8_maci_cmd_word_count_n, 0x08) is the halfword count both commands write after the opener: eight halfwords == one 16-byte program unit.

Invariant: Every value is a valid MACI opcode per HUM Ch 59.7.4.

See also: ra8_flash_config_set_write

Enumerator
k_ra8_maci_cmd_status_clear	Clear the command-locked state.
k_ra8_maci_cmd_forced_stop	Abort in-flight command processing.
k_ra8_maci_cmd_program	Program opener: extra-MRAM DATA area.
k_ra8_maci_cmd_config_set	Config-Set opener: OFS config area.
k_ra8_maci_cmd_word_count_n	N = 8 halfwords (one 16-byte unit).
k_ra8_maci_cmd_increment_counter	Increment an anti-rollback count.
k_ra8_maci_cmd_read_counter	Read an anti-rollback counter.
k_ra8_maci_cmd_final	Trailer byte: starts command processing.

Definition at line 660 of file ra8_flash_regs.h.

◆ ra8_mastat_mask_t

enum ra8_mastat_mask_t : uint8_t

MASTAT field masks.

Enumerator
k_ra8_mastat_mask_mreae	Extra MRAM access error.
k_ra8_mastat_mask_cmdlk	Command lock latched.

Definition at line 341 of file ra8_flash_regs.h.

◆ ra8_mcmdr_mask_t

enum ra8_mcmdr_mask_t : uint16_t

MCMDR field masks (MACI command status snapshot).

Enumerator
k_ra8_mcmdr_mask_pcmdr	Pre-command flag.
k_ra8_mcmdr_mask_cmdr	Command flag.
k_ra8_mcmdr_mask_cmd_progress	Any command in flight.

Definition at line 437 of file ra8_flash_regs.h.

◆ ra8_mcntselr_t

enum ra8_mcntselr_t : uint8_t

MCNTSELR field-value codes for the four counter families.

Enumerator
k_ra8_mcntselr_sec	ARC_SEC.
k_ra8_mcntselr_oembl	ARC_OEMBL (OEM bootloader).
k_ra8_mcntselr_nsec_0	ARC_NSEC index 0; +1/+2/+3 follow.
k_ra8_mcntselr_mask	CNTSEL[2:0].

Definition at line 598 of file ra8_flash_regs.h.

◆ ra8_mctrcntr_t

enum ra8_mctrcntr_t : uint16_t

Keyed values + masks for MCTRCNTR.

KEY[15:8] = 0xA5 per the standard RA family transfer-trigger convention. Bit 0 (TRTRG) starts the transfer.

Enumerator
k_ra8_mctrcntr_key	RA8 mctrcntr key.
k_ra8_mctrcntr_mask_start	RA8 mctrcntr mask start.

Definition at line 558 of file ra8_flash_regs.h.

◆ ra8_mctrlsr_mask_t

enum ra8_mctrlsr_mask_t : uint8_t

MCTRLSR field mask (transfer-list select).

Enumerator
k_ra8_mctrlsr_mask_list_sel	RA8 mctrlsr mask list sel.

Definition at line 568 of file ra8_flash_regs.h.

◆ ra8_mctrstatr_mask_t

enum ra8_mctrstatr_mask_t : uint16_t

MCTRSTATR field masks.

The HUM only defines TRBUSY (bit 0) and TRMD (bit 2). The driver surfaces an additional "done" view as TRMD inverted from TRBUSY, and an "err" view masking the upper bits for forward-compat.

Enumerator
k_ra8_mctrstatr_mask_busy	TRBUSY.
k_ra8_mctrstatr_mask_done	TRMD.
k_ra8_mctrstatr_mask_err	Reserved-future error.

Definition at line 582 of file ra8_flash_regs.h.

◆ ra8_mentryr_t

enum ra8_mentryr_t : uint16_t

Keyed values and field masks for the MENTRYR P/E entry register.

Enumerator
k_ra8_mentryr_pe_enter	KEY=0xAA, MENTRY=1.
k_ra8_mentryr_read_mode	KEY=0xAA, MENTRY=0.
k_ra8_mentryr_mask_pe_mode	MENTRY status bit.
k_ra8_mentryr_mask_pcka	Pause / resume gate bit.
k_ra8_mentryr_pe_pause	KEY=0xAA, MENTRY=1, PCKA=1.
k_ra8_mentryr_pe_resume	KEY=0xAA, MENTRY=1, PCKA=0.

Definition at line 379 of file ra8_flash_regs.h.

◆ ra8_mpaeint_mask_t

enum ra8_mpaeint_mask_t : uint8_t

MPAEINT field masks (extra MRAM access-error IRQ enable).

Enumerator
k_ra8_mpaeint_mask_mreaeie	Access-error IRQ enable.
k_ra8_mpaeint_mask_cmdlkie	Command-lock IRQ enable.

Definition at line 322 of file ra8_flash_regs.h.

◆ ra8_mram_base_addr_t

enum ra8_mram_base_addr_t : uintptr_t

MRMS controller base addresses.

The MRMS register window is 0x3808 bytes. Secure alias starts at 0x4013C000. The non-secure alias (BASE_NS_OFFSET = 0x10000000) is 0x5013C000. The MACI command-issuing area is a small two-register window at 0x40120000 (HUM Ch 59 p 3550).

Enumerator
k_ra8_mram_base_addr	Secure MRMS base.
k_ra8_mram_base_addr_ns	Non-secure MRMS alias.
k_ra8_mram_cmd_base	MACI command issue area.

Definition at line 116 of file ra8_flash_regs.h.

◆ ra8_mram_data_const_t

enum ra8_mram_data_const_t : uint32_t

Sizes used by the driver when chunking writes / counter reads.

Enumerator
k_ra8_mram_write_size_bytes	Minimum programmable unit.
k_ra8_mram_block_size_bytes	One programmable block.
k_ra8_mram_config_set_word_count	8 halfwords per MACI write.
k_ra8_mram_config_set_bytes	Bytes per config-set (8 halfwords).
k_ra8_mram_arc_max_words	Max 32-bit words per ARC.

Definition at line 703 of file ra8_flash_regs.h.

◆ ra8_mram_off_t

enum ra8_mram_off_t : uint16_t

Byte offsets into the MRMS register window.

Values track the layout in R_MRMS_Type from the FSP CMSIS device header (R7KA8D2KF_core0.h), which mirrors the HUM Ch 59 register descriptions on pages 3551..3624.

Enumerator
k_ra8_mram_off_mrcpfb	RA8 MRAM off mrcpfb.
k_ra8_mram_off_mrcfreq	RA8 MRAM off mrcfreq.
k_ra8_mram_off_mrefreq	RA8 MRAM off mrefreq.
k_ra8_mram_off_mrcdecc	RA8 MRAM off mrcdecc.
k_ra8_mram_off_mrcraeint	RA8 MRAM off mrcraeint.
k_ra8_mram_off_mrcraes	RA8 MRAM off mrcraes.
k_ra8_mram_off_mrcrtea	RA8 MRAM off mrcrtea.
k_ra8_mram_off_mrcrdea	RA8 MRAM off mrcrdea.
k_ra8_mram_off_mreraint	RA8 MRAM off mreraint.
k_ra8_mram_off_mreraes	RA8 MRAM off mreraes.
k_ra8_mram_off_mrertea	RA8 MRAM off mrertea.
k_ra8_mram_off_mrerdea	RA8 MRAM off mrerdea.
k_ra8_mram_off_msar	RA8 MRAM off msar.
k_ra8_mram_off_mrezs	RA8 MRAM off mrezs.
k_ra8_mram_off_mrezc	RA8 MRAM off mrezc.
k_ra8_mram_off_mastat	RA8 MRAM off mastat.
k_ra8_mram_off_mpaeint	RA8 MRAM off mpaeint.
k_ra8_mram_off_mrdyie	RA8 MRAM off mrdyie.
k_ra8_mram_off_msaddr	RA8 MRAM off msaddr.
k_ra8_mram_off_mcntselr	RA8 MRAM off mcntselr.
k_ra8_mram_off_mcntdtr0	RA8 MRAM off mcntdtr0.
k_ra8_mram_off_mcntdtr1	RA8 MRAM off mcntdtr1.
k_ra8_mram_off_mctrcntr	RA8 MRAM off mctrcntr.
k_ra8_mram_off_mctrlsr	RA8 MRAM off mctrlsr.
k_ra8_mram_off_mctrstatr	RA8 MRAM off mctrstatr.
k_ra8_mram_off_mstatr	RA8 MRAM off mstatr.
k_ra8_mram_off_mentryr	RA8 MRAM off mentryr.
k_ra8_mram_off_msuinitr	RA8 MRAM off msuinitr.
k_ra8_mram_off_mcmdr	RA8 MRAM off mcmdr.
k_ra8_mram_off_msuasmon	RA8 MRAM off msuasmon.
k_ra8_mram_off_msuacr	RA8 MRAM off msuacr.
k_ra8_mram_off_mrpsc	RA8 MRAM off mrpsc.
k_ra8_mram_off_mrcpc0	RA8 MRAM off mrcpc0.
k_ra8_mram_off_mrcpc1	RA8 MRAM off mrcpc1.
k_ra8_mram_off_mrcbprot0	RA8 MRAM off mrcbprot0.
k_ra8_mram_off_mrcbprot1	RA8 MRAM off mrcbprot1.
k_ra8_mram_off_mrcps	RA8 MRAM off mrcps.
k_ra8_mram_off_mrcpaeint	RA8 MRAM off mrcpaeint.
k_ra8_mram_off_mrcpea	RA8 MRAM off mrcpea.
k_ra8_mram_off_mrcflr	RA8 MRAM off mrcflr.
k_ra8_mram_off_mrceecc	RA8 MRAM off mrceecc.

Definition at line 137 of file ra8_flash_regs.h.

◆ ra8_mrcbprot0_t

enum ra8_mrcbprot0_t : uint16_t

Keyed values for MRCBPROT0 (non-secure block-protection cancel).

BPCN0 = 0 locks the block (default protect-on); = 1 cancels. KEY[15:8] = 0x88.

Enumerator
k_ra8_mrcbprot0_key_lock	Keep block protect on.
k_ra8_mrcbprot0_key_unlock	Cancel block protect.

Definition at line 514 of file ra8_flash_regs.h.

◆ ra8_mrcbprot1_t

enum ra8_mrcbprot1_t : uint16_t

Keyed values for MRCBPROT1 (secure block-protection cancel).

KEY[15:8] = 0x44.

Enumerator
k_ra8_mrcbprot1_key_lock	RA8 mrcbprot1 key lock.
k_ra8_mrcbprot1_key_unlock	RA8 mrcbprot1 key unlock.

Definition at line 527 of file ra8_flash_regs.h.

◆ ra8_mrcdecc_mask_t

enum ra8_mrcdecc_mask_t : uint16_t

Field masks and key for the MRCDECC ECC decoder control.

Enumerator
k_ra8_mrcdecc_mask_dececen	Decoder enable (ECCSELC).
k_ra8_mrcdecc_key_shift	Pre-shifted KEY[15:8]=0x8C.

Definition at line 269 of file ra8_flash_regs.h.

◆ ra8_mrceecc_mask_t

enum ra8_mrceecc_mask_t : uint16_t

Field masks and key for the MRCEECC ECC encoder control.

The HUM names the enable bit ECCBYPC (bypass-clear, active high for "encoder enabled"). We expose it as eccen to keep driver code intent-readable.

Enumerator
k_ra8_mrceecc_mask_eccen	Encoder enable bit.
k_ra8_mrceecc_key_shift	Pre-shifted KEY[15:8]=0xC0.

Definition at line 259 of file ra8_flash_regs.h.

◆ ra8_mrcflr_t

enum ra8_mrcflr_t : uint16_t

Keyed value for MRCFLR (write-buffer flush).

0xC301 sets MRCFL=1 with KEY[15:8]=0xC3 (HUM Ch 59 p 3601).

Enumerator
k_ra8_mrcflr_key_flush	RA8 mrcflr key flush.

Definition at line 540 of file ra8_flash_regs.h.

◆ ra8_mrcpaeint_mask_t

enum ra8_mrcpaeint_mask_t : uint8_t

MRCPAEINT field mask.

Enumerator
k_ra8_mrcpaeint_mask_mrcaeie	Code program-error IRQ enable.

Definition at line 313 of file ra8_flash_regs.h.

◆ ra8_mrcpc0_t

enum ra8_mrcpc0_t : uint16_t

Keyed values for MRCPC0 (non-secure program-gate).

KEY[15:8] = 0x86. Bit 0 enables programming when set.

Enumerator
k_ra8_mrcpc0_key_enable	RA8 mrcpc0 key enable.
k_ra8_mrcpc0_key_disable	RA8 mrcpc0 key disable.

Definition at line 487 of file ra8_flash_regs.h.

◆ ra8_mrcpc1_t

enum ra8_mrcpc1_t : uint16_t

Keyed values for MRCPC1 (secure program-gate).

KEY[15:8] = 0x68.

Enumerator
k_ra8_mrcpc1_key_enable	RA8 mrcpc1 key enable.
k_ra8_mrcpc1_key_disable	RA8 mrcpc1 key disable.

Definition at line 500 of file ra8_flash_regs.h.

◆ ra8_mrcps_mask_t

enum ra8_mrcps_mask_t : uint8_t

Bit masks for the MRCPS Code MRAM Program Status Register.

The error bits (PRGERRC, ECCERRC) are W1C; the busy bits (ABUFEMP, ABUFFULL, PRGBSYC) are read-only status.

Enumerator
k_ra8_mrcps_mask_prgerrc	Programming error.
k_ra8_mrcps_mask_eccerrc	ECC error.
k_ra8_mrcps_mask_abufemp	Address buffer empty.
k_ra8_mrcps_mask_abuffull	Address buffer full.
k_ra8_mrcps_mask_prgbsyc	Code MRAM program busy.
k_ra8_mrcps_mask_errors	W1C: PRGERRC + ECCERRC.

Definition at line 235 of file ra8_flash_regs.h.

◆ ra8_mrcraeint_mask_t

enum ra8_mrcraeint_mask_t : uint8_t

MRCRAEINT / MRERAINT IRQ-enable bits.

INTENBDC enables the DEC IRQ; INTENBTC enables the TED IRQ.

Enumerator
k_ra8_mrcraeint_mask_intenbdc	DEC error IRQ enable.
k_ra8_mrcraeint_mask_intenbtc	TED error IRQ enable.

Definition at line 303 of file ra8_flash_regs.h.

◆ ra8_mrcraes_mask_t

enum ra8_mrcraes_mask_t : uint8_t

MRCRAES / MRERAES read-access error status bits.

Same layout in both code and extra registers (DEC at bit 0, TED at bit 1), so the same enum is reused for both via the names k_ra8_mrcraes_mask_*.

Enumerator
k_ra8_mrcraes_mask_decerrc	2-bit DEC error.
k_ra8_mrcraes_mask_tederrc	1-bit TED error.
k_ra8_mrcraes_mask_any	Either 1-bit or 2-bit.

Definition at line 289 of file ra8_flash_regs.h.

◆ ra8_mrdyie_mask_t

enum ra8_mrdyie_mask_t : uint8_t

MRDYIE field mask.

Enumerator
k_ra8_mrdyie_mask_mrdyie	MRDY IRQ enable.

Definition at line 332 of file ra8_flash_regs.h.

◆ ra8_mrezc_t

enum ra8_mrezc_t : uint16_t

MREZC keyed control words (zeroization).

The HUM specifies WHUKZE[2:0] = 0b101 + KEY[15:8] = 0xA5 to launch a full W-HUK zeroize.

Enumerator
k_ra8_mrezc_full_zero	RA8 mrezc full zero.

Definition at line 365 of file ra8_flash_regs.h.

◆ ra8_mrezs_mask_t

enum ra8_mrezs_mask_t : uint8_t

MREZS field masks (zeroization status).

Enumerator
k_ra8_mrezs_mask_whukzf	W-HUK Zero Flag.
k_ra8_mrezs_mask_whukexe	W-HUK Zeroization Executing.

Definition at line 351 of file ra8_flash_regs.h.

◆ ra8_mrpsc_mask_t

enum ra8_mrpsc_mask_t : uint8_t

MRPSC field masks (high-speed program enable).

Enumerator
k_ra8_mrpsc_mask_mhspen	High-speed program enable.

Definition at line 475 of file ra8_flash_regs.h.

◆ ra8_msaddr_t

enum ra8_msaddr_t : uint32_t

Well-known MSADDR targets for configuration-set writes.

0x02C9F070 is the start-up-area select (BTFLG / BTSIZE) word group; the SAS halfword sits 4 bytes deeper at 0x02C9F074.

Enumerator
k_ra8_msaddr_config_set_startup	RA8 msaddr config set startup.
k_ra8_msaddr_ofs_sas	RA8 msaddr ofs sas.

Definition at line 687 of file ra8_flash_regs.h.

◆ ra8_mstatr_mask_t

enum ra8_mstatr_mask_t : uint32_t

MSTATR field masks (extra-MRAM status flags).

Enumerator
k_ra8_mstatr_mask_cfgseterr	Configuration set error.
k_ra8_mstatr_mask_prgerr	Program error.
k_ra8_mstatr_mask_ilglerr	Illegal error.
k_ra8_mstatr_mask_mrdy	MRE ready.
k_ra8_mstatr_mask_tzferr	TrustZone filter error.
k_ra8_mstatr_mask_oterr	Other error.
k_ra8_mstatr_mask_secerr	Security error.
k_ra8_mstatr_mask_ilgcomerr	Illegal command error.
k_ra8_mstatr_mask_any_err	Composite error mask.

Definition at line 448 of file ra8_flash_regs.h.

◆ ra8_msuacr_t

enum ra8_msuacr_t : uint16_t

Keyed values for MSUACR start-up swap.

SAS[1:0] = 0b00 selects default; 0b01 selects alternate. KEY[15:8] must be 0x66 for the write to take effect.

Enumerator
k_ra8_msuacr_key	RA8 msuacr key.
k_ra8_msuacr_swap_default	RA8 msuacr swap default.
k_ra8_msuacr_swap_alternate	RA8 msuacr swap alternate.

Definition at line 401 of file ra8_flash_regs.h.

◆ ra8_msuasmon_mask_t

enum ra8_msuasmon_mask_t : uint32_t

MSUASMON read-only field masks.

Enumerator
k_ra8_msuasmon_mask_fspr	Protection flag.
k_ra8_msuasmon_mask_btflg	Boot-swap flag.

Definition at line 412 of file ra8_flash_regs.h.

◆ ra8_msuinitr_t

enum ra8_msuinitr_t : uint16_t

Keyed value + field mask for MSUINITR.

Enumerator
k_ra8_msuinitr_full_init	KEY=0xAA, SUINIT=1.
k_ra8_msuinitr_mask_suinit	SUINIT status bit.

Definition at line 422 of file ra8_flash_regs.h.

Function Documentation

◆ ra8_mram_cmd16()

volatile uint16_t * ra8_mram_cmd16 ( void )

inlinestatic

Pointer to the MACI command-issuing area, halfword-wide.

Returns: Volatile pointer for a 16-bit MACI payload store.

Precondition: Controller is in P/E mode.

Postcondition: No side effect.

Definition at line 792 of file ra8_flash_regs.h.

References k_ra8_mram_cmd_base.

Referenced by priv_ra8_flash_internal_maci_cmd16().

◆ ra8_mram_cmd8()

volatile uint8_t * ra8_mram_cmd8 ( void )

inlinestatic

Pointer to the MACI command-issuing area, byte-wide.

Returns: Volatile pointer for an 8-bit MACI opcode store.

Precondition: Controller is in P/E mode (HUM Ch 59 p 3582 transitions).

Postcondition: Returns the same address every call; pure pointer arithmetic, no side effect on the bus.

Definition at line 779 of file ra8_flash_regs.h.

References k_ra8_mram_cmd_base.

Referenced by priv_ra8_flash_internal_maci_cmd8().

◆ ra8_mram_reg16()

volatile uint16_t * ra8_mram_reg16 ( uint16_t off )

inlinestatic

Pointer to a halfword-wide MRMS register at offset off.

Parameters

[in] off Byte offset into the MRMS window; must be 16-bit aligned.

Returns: Volatile pointer for a 16-bit load/store.

Precondition: off & 1 == 0.; Caller has powered the MRMS controller.

Postcondition: No side effect.

Definition at line 750 of file ra8_flash_regs.h.

References k_ra8_mram_base_addr.

Referenced by internal_flash_program_window(), internal_set_program_gate(), ra8_flash_block_protect_set(), ra8_flash_deinit(), ra8_flash_enter_pe_mode(), ra8_flash_exit_pe_mode(), ra8_flash_get_extended_status(), ra8_flash_get_update_status(), ra8_flash_init(), ra8_flash_lock_set(), ra8_flash_msuinitr_kick(), ra8_flash_resume(), ra8_flash_set_ecc_decoder_enable(), ra8_flash_set_ecc_encoder_enable(), ra8_flash_set_security_attribution(), ra8_flash_set_startup_area(), ra8_flash_set_update_transfer(), ra8_flash_status(), ra8_flash_suspend(), and ra8_flash_zeroize_huk().

◆ ra8_mram_reg32()

volatile uint32_t * ra8_mram_reg32 ( uint16_t off )

inlinestatic

Pointer to a word-wide MRMS register at offset off.

Parameters

[in] off Byte offset into the MRMS window; must be 32-bit aligned.

Returns: Volatile pointer for a 32-bit load/store.

Precondition: off & 3 == 0.; Caller has powered the MRMS controller.

Postcondition: No side effect.

Definition at line 765 of file ra8_flash_regs.h.

References k_ra8_mram_base_addr.

Referenced by internal_arc_read_locked(), internal_dispatch_ecc(), priv_ra8_flash_internal_wait_mrdy(), ra8_flash_config_set_write(), ra8_flash_dispatch_isr(), ra8_flash_get_ecc_error_addr(), ra8_flash_get_extended_status(), ra8_flash_get_program_error_addr(), ra8_flash_get_startup_area(), ra8_flash_init(), ra8_flash_status(), and ra8_flash_update_clock_freq().

◆ ra8_mram_reg8()

volatile uint8_t * ra8_mram_reg8 ( uint16_t off )

inlinestatic

Pointer to a byte-wide MRMS register at offset off.

Parameters

[in] off Byte offset into the MRMS window.

Returns: Volatile pointer suitable for a single-byte load/store.

Precondition: off is one of the k_ra8_mram_off_* values (the driver casts the enum to uint16_t at the call site).; Caller has powered the MRMS controller through CGC.

Postcondition: No side effect; returns a valid pointer for the host fake (mmap-backed) or hardware bus address on target.

Note: Accessor is static inline so each driver TU embeds the address arithmetic without function-call overhead.

Definition at line 735 of file ra8_flash_regs.h.

References k_ra8_mram_base_addr.

Referenced by internal_arc_cmd(), internal_dispatch_ecc(), internal_irq_rmw8(), internal_set_hsp_mode(), internal_wait_buffer_ready(), internal_wait_commit_done(), priv_ra8_flash_internal_set_prefetch(), ra8_flash_clear_status(), ra8_flash_deinit(), ra8_flash_dispatch_isr(), ra8_flash_force_stop(), ra8_flash_get_extended_status(), ra8_flash_get_status(), ra8_flash_init(), ra8_flash_set_irq_enable(), ra8_flash_set_update_transfer(), ra8_flash_status(), ra8_flash_write_block(), and ra8_flash_zeroize_huk().

Enumerations

Functions

Detailed Description

Enumeration Type Documentation

◆ ra8_arc_limits_t

◆ ra8_flash_map_t

◆ ra8_maci_cmd_t

◆ ra8_mastat_mask_t

◆ ra8_mcmdr_mask_t

◆ ra8_mcntselr_t

◆ ra8_mctrcntr_t

◆ ra8_mctrlsr_mask_t

◆ ra8_mctrstatr_mask_t

◆ ra8_mentryr_t

◆ ra8_mpaeint_mask_t

◆ ra8_mram_base_addr_t

◆ ra8_mram_data_const_t

◆ ra8_mram_off_t

◆ ra8_mrcbprot0_t

◆ ra8_mrcbprot1_t

◆ ra8_mrcdecc_mask_t

◆ ra8_mrceecc_mask_t

◆ ra8_mrcflr_t

◆ ra8_mrcpaeint_mask_t

◆ ra8_mrcpc0_t

◆ ra8_mrcpc1_t

◆ ra8_mrcps_mask_t

◆ ra8_mrcraeint_mask_t

◆ ra8_mrcraes_mask_t

◆ ra8_mrdyie_mask_t

◆ ra8_mrezc_t

◆ ra8_mrezs_mask_t

◆ ra8_mrpsc_mask_t

◆ ra8_msaddr_t

◆ ra8_mstatr_mask_t

◆ ra8_msuacr_t

◆ ra8_msuasmon_mask_t

◆ ra8_msuinitr_t

Function Documentation

◆ ra8_mram_cmd16()

◆ ra8_mram_cmd8()

◆ ra8_mram_reg16()

◆ ra8_mram_reg32()

◆ ra8_mram_reg8()