ra8_flash_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
/* =============================================================================
 * Memory map: code-MRAM, extra-MRAM, OFS aliases
 * =============================================================================
 */

typedef enum : uintptr_t {
  /* HUM Ch 59.1 "Address Map" p 3543 */
  k_ra8_flash_code_start = 0x02000000UL, 
  k_ra8_flash_code_size  = 0x00100000UL, 
 
  /* Extra-MRAM option-setting / OTP window: the whole address space the MACI
   * Program command accepts. There is NO rewritable data-flash on this part.
   * HUM Ch 59.7.4.5 "Program Command" Table 59.15 p 3592 (0x02E0_7600 first
   * legal target .. 0x02E1_79F0 last). */
  k_ra8_flash_extra_start = 0x02E07600UL, 
  k_ra8_flash_extra_size  = 0x00010400UL, 
 
  /* General-purpose OTP sub-range: the only portion of the window a
   * general-purpose write may target. The rest (FSBL, code certificate, PBPS,
   * POFSPS, REVOKE, HUK-zeroize, anti-rollback) is security-critical and needs
   * a deliberate, separately-named call (see ra8_flash_config_set_write).
   * HUM Ch 7.2.25 "GPOTPn : General Purpose OTP (n = 0 to 23)" p 299 (24 words
   * at 0x02E0_76A0 + 0x4 x n). */
  k_ra8_flash_gpotp_start = 0x02E076A0UL, 
  k_ra8_flash_gpotp_size  = 0x00000060UL, 
 
  /* Guard boundary: the permanent / irreversible option-setting structures
   * begin here (PBPS_SEC, PBPS, POFSPS, REVOKE, Zeroization HUK enable,
   * anti-rollback lock/config). A general-purpose write is refused at or above
   * this address so a caller cannot brick the part or destroy the wrapped HUK
   * by accident. HUM Ch 59.7.4.5 Table 59.15 p 3592 (PBPS_SEC at 0x02E1_7700). */
  k_ra8_flash_extra_locked_start = 0x02E17700UL, 
 
  /* HUM Ch 7 "Option-Setting Memory" p 278 -- the config_set MACI command
   * targets halfwords inside this OFS window (BTFLG/BTSIZE at 0x02C9F070,
   * SAS at 0x02C9F074, etc.). FSP r_mram.c uses MSADDR values inside this
   * 4 KiB block as the only legal config_set destinations. */
  k_ra8_flash_ofs_start = 0x02C9F000UL, 
  k_ra8_flash_ofs_size  = 0x00001000UL, 
 
  /* HUM Ch 7.2.21 "ARCCS Anti-Rollback Counter Configuration" p 296 */
  k_ra8_flash_ofs_arccs_addr = 0x02E17932UL, 
  /* HUM Ch 7.2.22 "ARC_SEC" p 296 */
  k_ra8_flash_ofs_arc_sec_addr = 0x02F27E00UL, 
  /* HUM Ch 7.2.23 "ARC_NSEC" p 297 */
  k_ra8_flash_ofs_arc_nsec_addr = 0x02F27E08UL, 
} ra8_flash_map_t;

typedef enum : uintptr_t {
  /* HUM Ch 59.1 "Address Map" p 3543 */
  k_ra8_mram_base_addr    = 0x4013C000UL, 
  k_ra8_mram_base_addr_ns = 0x5013C000UL, 
  k_ra8_mram_cmd_base     = 0x40120000UL, 
} ra8_mram_base_addr_t;
 
/* =============================================================================
 * Register offsets within the MRMS window
 * =============================================================================
 */

typedef enum : uint16_t {
  /* HUM Ch 59.5.1 "MRCPFB : Code MRAM Pre-Fetch Buffer Enable Register" p 3551 */
  k_ra8_mram_off_mrcpfb = 0x0000U, 
  /* HUM Ch 59.5.2 "MRCFREQ : Code MRAM Frequency Notifications Register" p 3551 */
  k_ra8_mram_off_mrcfreq = 0x0004U, 
  /* HUM Ch 59.5.3 "MREFREQ : Extra MRAM Frequency Notifications Register" p 3552 */
  k_ra8_mram_off_mrefreq = 0x0008U, 
  /* HUM Ch 59.5.4 "MRCDECC : Code MRAM ECC Decoder Control Register" p 3554 */
  k_ra8_mram_off_mrcdecc = 0x0010U, 
  /* HUM Ch 59.5.5 "MRCRAEINT : Code MRAM Read Access Error Interrupt Enable" p 3554 */
  k_ra8_mram_off_mrcraeint = 0x0014U, 
  /* HUM Ch 59.5.6 "MRCRAES : Code MRAM Read Access Error Status Register" p 3554 */
  k_ra8_mram_off_mrcraes = 0x0018U, 
  /* HUM Ch 59.5.7 "MRCRTEA : Code MRAM TED Error Address Register" p 3555 */
  k_ra8_mram_off_mrcrtea = 0x001CU, 
  /* HUM Ch 59.5.8 "MRCRDEA : Code MRAM DEC Error Address Register" p 3556 */
  k_ra8_mram_off_mrcrdea = 0x0020U, 
  /* HUM Ch 59.5.9 "MRERAINT : Extra MRAM Read Access Error Interrupt Enable" p 3557 */
  k_ra8_mram_off_mreraint = 0x0034U, 
  /* HUM Ch 59.5.10 "MRERAES : Extra MRAM Read Access Error Status Register" p 3557 */
  k_ra8_mram_off_mreraes = 0x0038U, 
  /* HUM Ch 59.5.11 "MRERTEA : Extra MRAM TED Error Address Register" p 3558 */
  k_ra8_mram_off_mrertea = 0x003CU, 
  /* HUM Ch 59.5.12 "MRERDEA : Extra MRAM DEC Error Address Register" p 3559 */
  k_ra8_mram_off_mrerdea = 0x0040U, 
  /* HUM Ch 59.5.13 "MSAR : MRAM Security Attribution Register" p 3559 */
  k_ra8_mram_off_msar = 0x0100U, 
  /* HUM Ch 59.5.14 "MREZS : Extra MRAM Zeroization Status Register" p 3561 */
  k_ra8_mram_off_mrezs = 0x0400U, 
  /* HUM Ch 59.5.15 "MREZC : Extra MRAM Zeroization Control Register" p 3561 */
  k_ra8_mram_off_mrezc = 0x0404U, 
  /* HUM Ch 59.5.16 "MASTAT : Extra MRAM Access Status Register" p 3562 */
  k_ra8_mram_off_mastat = 0x2010U, 
  /* HUM Ch 59.5.17 "MPAEINT : Extra MRAM Access Error Interrupt Enable" p 3563 */
  k_ra8_mram_off_mpaeint = 0x2014U, 
  /* HUM Ch 59.5.18 "MRDYIE : Extra MRAM Ready Interrupt Enable Register" p 3564 */
  k_ra8_mram_off_mrdyie = 0x2018U, 
  /* HUM Ch 59.5.19 "MSADDR : MACI Command Start Address Register" p 3564 */
  k_ra8_mram_off_msaddr = 0x2030U, 
  /* HUM Ch 59.5.20 "MCNTSELR : MRAM Counter Select Register" p 3565 */
  k_ra8_mram_off_mcntselr = 0x2048U, 
  /* HUM Ch 59.5.21 "MCNTDTR0 : MRAM Counter Data Register 0" p 3576 */
  k_ra8_mram_off_mcntdtr0 = 0x204CU, 
  /* HUM Ch 59.5.22 "MCNTDTR1 : MRAM Counter Data Register 1" p 3577 */
  k_ra8_mram_off_mcntdtr1 = 0x2050U, 
  /* HUM Ch 59.5.23 "MCTRCNTR : MRAM Configuration Update Transfer Control" p 3566 */
  k_ra8_mram_off_mctrcntr = 0x2060U, 
  /* HUM Ch 59.5.24 "MCTRLSR : MRAM Configuration Update Transfer List Select" p 3567 */
  k_ra8_mram_off_mctrlsr = 0x2064U, 
  /* HUM Ch 59.5.25 "MCTRSTATR : MRAM Configuration Update Transfer Status" p 3568 */
  k_ra8_mram_off_mctrstatr = 0x206CU, 
  /* HUM Ch 59.5.26 "MSTATR : Extra MRAM Status Register" p 3568 */
  k_ra8_mram_off_mstatr = 0x2080U, 
  /* HUM Ch 59.5.27 "MENTRYR : Extra MRAM Program Mode Entry Register" p 3571 */
  k_ra8_mram_off_mentryr = 0x2084U, 
  /* HUM Ch 59.5.28 "MSUINITR : Extra MRAM Sequencer Set-Up Initialization" p 3572 */
  k_ra8_mram_off_msuinitr = 0x208CU, 
  /* HUM Ch 59.5.29 "MCMDR : MACI Command Register" p 3572 */
  k_ra8_mram_off_mcmdr = 0x20A0U, 
  /* HUM Ch 59.5.30 "MSUASMON : MRAM Start-Up Area Select Monitor Register" p 3573 */
  k_ra8_mram_off_msuasmon = 0x20DCU, 
  /* HUM Ch 59.5.31 "MSUACR : MRAM Start-Up Area Control Register" p 3574 */
  k_ra8_mram_off_msuacr = 0x20E8U, 
  /* HUM Ch 59.5.32 "MRPSC : MRAM Program Speed Control Register" p 3575 */
  k_ra8_mram_off_mrpsc = 0x2800U, 
  /* HUM Ch 59.5.33 "MRCPC0 : Code MRAM Program Control Register" p 3575 */
  k_ra8_mram_off_mrcpc0 = 0x3000U, 
  /* HUM Ch 59.5.34 "MRCPC1 : Code MRAM Program Control for Secure Register" p 3576 */
  k_ra8_mram_off_mrcpc1 = 0x3004U, 
  /* HUM Ch 59.5.35 "MRCBPROT0 : Code MRAM Block Protection Register" p 3576 */
  k_ra8_mram_off_mrcbprot0 = 0x3008U, 
  /* HUM Ch 59.5.36 "MRCBPROT1 : Code MRAM Block Protection for Secure Register" p 3577 */
  k_ra8_mram_off_mrcbprot1 = 0x300CU, 
  /* HUM Ch 59.5.37 "MRCPS : Code MRAM Program Status Register" p 3577 */
  k_ra8_mram_off_mrcps = 0x3010U, 
  /* HUM Ch 59.5.38 "MRCPAEINT : Code MRAM Program Access Error Interrupt Enable" p 3579 */
  k_ra8_mram_off_mrcpaeint = 0x3014U, 
  /* HUM Ch 59.5.39 "MRCPEA : Code MRAM Program Error Address Register" p 3579 */
  k_ra8_mram_off_mrcpea = 0x3018U, 
  /* HUM Ch 59.5.40 "MRCFLR : Code MRAM Flush Register" p 3580 */
  k_ra8_mram_off_mrcflr = 0x3030U, 
  /* HUM Ch 59.5.41 "MRCEECC : Code MRAM ECC Encoder Control Register" p 3580 */
  k_ra8_mram_off_mrceecc = 0x3804U, 
} ra8_mram_off_t;
 
/* =============================================================================
 * MRCPS field masks  (HUM Ch 59 "MRCPS" p 3601)
 * =============================================================================
 */

typedef enum : uint8_t {
  /* HUM Ch 59 "MRCPS : Code MRAM Program Status Register" p 3577 */
  k_ra8_mrcps_mask_prgerrc  = 0x01U, 
  k_ra8_mrcps_mask_eccerrc  = 0x02U, 
  k_ra8_mrcps_mask_abufemp  = 0x20U, 
  k_ra8_mrcps_mask_abuffull = 0x40U, 
  k_ra8_mrcps_mask_prgbsyc  = 0x80U, 
  k_ra8_mrcps_mask_errors   = 0x03U, 
} ra8_mrcps_mask_t;
 
/* =============================================================================
 * MRCEECC / MRCDECC ECC controls  (HUM Ch 59 p 3554, p 3624)
 * =============================================================================
 */

typedef enum : uint16_t {
  /* HUM Ch 59 "MRCEECC : Code MRAM ECC Encoder Control" p 3580 */
  k_ra8_mrceecc_mask_eccen = 0x0001U, 
  k_ra8_mrceecc_key_shift  = 0xC000U, 
} ra8_mrceecc_mask_t;

typedef enum : uint16_t {
  /* HUM Ch 59 "MRCDECC : Code MRAM ECC Decoder Control" p 3554 */
  k_ra8_mrcdecc_mask_dececen = 0x0002U, 
  k_ra8_mrcdecc_key_shift    = 0x8C00U, 
} ra8_mrcdecc_mask_t;
 
/* =============================================================================
 * Read-error and access-error masks
 * =============================================================================
 */

typedef enum : uint8_t {
  /* HUM Ch 59 "MRCRAES : Code MRAM Read Access Error Status" p 3554 */
  k_ra8_mrcraes_mask_decerrc = 0x01U, 
  k_ra8_mrcraes_mask_tederrc = 0x02U, 
  k_ra8_mrcraes_mask_any     = 0x03U, 
} ra8_mrcraes_mask_t;

typedef enum : uint8_t {
  /* HUM Ch 59 "MRCRAEINT : Code MRAM Read Access Error IRQ Enable" p 3554 */
  k_ra8_mrcraeint_mask_intenbdc = 0x01U, 
  k_ra8_mrcraeint_mask_intenbtc = 0x02U, 
} ra8_mrcraeint_mask_t;

typedef enum : uint8_t {
  /* HUM Ch 59 "MRCPAEINT : Code MRAM Program Access Error IRQ Enable" p 3579 */
  k_ra8_mrcpaeint_mask_mrcaeie = 0x80U, 
} ra8_mrcpaeint_mask_t;

typedef enum : uint8_t {
  /* HUM Ch 59 "MPAEINT : Extra MRAM Access Error IRQ Enable" p 3563 */
  k_ra8_mpaeint_mask_mreaeie = 0x08U, 
  k_ra8_mpaeint_mask_cmdlkie = 0x10U, 
} ra8_mpaeint_mask_t;

typedef enum : uint8_t {
  /* HUM Ch 59 "MRDYIE : Extra MRAM Ready Interrupt Enable" p 3564 */
  k_ra8_mrdyie_mask_mrdyie = 0x01U, 
} ra8_mrdyie_mask_t;

typedef enum : uint8_t {
  /* HUM Ch 59 "MASTAT : Extra MRAM Access Status Register" p 3562 */
  k_ra8_mastat_mask_mreae = 0x08U, 
  k_ra8_mastat_mask_cmdlk = 0x10U, 
} ra8_mastat_mask_t;

typedef enum : uint8_t {
  /* HUM Ch 59 "MREZS : Extra MRAM Zeroization Status Register" p 3561 */
  k_ra8_mrezs_mask_whukzf  = 0x01U, 
  k_ra8_mrezs_mask_whukexe = 0x02U, 
} ra8_mrezs_mask_t;

typedef enum : uint16_t {
  /* HUM Ch 59 "MREZC : Extra MRAM Zeroization Control" p 3561 */
  k_ra8_mrezc_full_zero = 0xA505U, 
} ra8_mrezc_t;
 
/* =============================================================================
 * MENTRYR / MSUACR / MSUINITR / MSUASMON
 * =============================================================================
 */

typedef enum : uint16_t {
  /* HUM Ch 59 "MENTRYR : Extra MRAM Program-Mode Entry" p 3571 */
  k_ra8_mentryr_pe_enter     = 0xAA80U, 
  k_ra8_mentryr_read_mode    = 0xAA00U, 
  k_ra8_mentryr_mask_pe_mode = 0x0080U, 
  /* PCKA -- driver-internal name for the suspend/resume gate the
   * FSP firmware exposes through the keyed MENTRYR write window.
   * Setting PCKA pauses an in-flight P/E at the next page boundary;
   * clearing it resumes.  HUM Ch 59 "MENTRYR" pp 3582+. */
  k_ra8_mentryr_mask_pcka = 0x0040U, 
  k_ra8_mentryr_pe_pause  = 0xAAC0U, 
  k_ra8_mentryr_pe_resume = 0xAA80U, 
} ra8_mentryr_t;

typedef enum : uint16_t {
  /* HUM Ch 59 "MSUACR : Start-Up Area Control Register" p 3574 */
  k_ra8_msuacr_key            = 0x6600U, 
  k_ra8_msuacr_swap_default   = 0x0000U, 
  k_ra8_msuacr_swap_alternate = 0x0001U, 
} ra8_msuacr_t;

typedef enum : uint32_t {
  /* HUM Ch 59 "MSUASMON : Start-Up Area Monitor" p 3573 */
  k_ra8_msuasmon_mask_fspr  = 0x00008000UL, 
  k_ra8_msuasmon_mask_btflg = 0x80000000UL, 
} ra8_msuasmon_mask_t;

typedef enum : uint16_t {
  /* HUM Ch 59 "MSUINITR : Extra MRAM Sequencer Set-Up Init" p 3572 */
  k_ra8_msuinitr_full_init   = 0xAA01U, 
  k_ra8_msuinitr_mask_suinit = 0x0001U, 
} ra8_msuinitr_t;
 
/* =============================================================================
 * MCMDR / MSTATR
 * =============================================================================
 */

typedef enum : uint16_t {
  /* HUM Ch 59 "MCMDR : MACI Command Register" p 3572 */
  k_ra8_mcmdr_mask_pcmdr        = 0x00FFU, 
  k_ra8_mcmdr_mask_cmdr         = 0xFF00U, 
  k_ra8_mcmdr_mask_cmd_progress = 0xFFFFU, 
} ra8_mcmdr_mask_t;

typedef enum : uint32_t {
  /* HUM Ch 59 "MSTATR : Extra MRAM Status Register" p 3568 */
  k_ra8_mstatr_mask_cfgseterr = 0x00000020UL, 
  k_ra8_mstatr_mask_prgerr    = 0x00001000UL, 
  k_ra8_mstatr_mask_ilglerr   = 0x00004000UL, 
  k_ra8_mstatr_mask_mrdy      = 0x00008000UL, 
  k_ra8_mstatr_mask_tzferr    = 0x00080000UL, 
  k_ra8_mstatr_mask_oterr     = 0x00100000UL, 
  k_ra8_mstatr_mask_secerr    = 0x00200000UL, 
  k_ra8_mstatr_mask_ilgcomerr = 0x00800000UL, 
  /* Aggregate of all error bits used by the driver to gate command success.
   * HUM Ch 59.5.26 "MSTATR" p 3578 lists CFGSETERR(5)=0x20, PRGERR(12)=0x1000,
   * ILGLERR(14)=0x4000, TZFERR(19)=0x80000, OTERR(20)=0x100000,
   * SECERR(21)=0x200000, ILGCOMERR(23)=0x800000. OR of all seven = 0x00B85020.
   * The previous 0x009850A0 dropped SECERR and added a stray bit 7. */
  k_ra8_mstatr_mask_any_err = 0x00B85020UL, 
} ra8_mstatr_mask_t;
 
/* =============================================================================
 * MRPSC / MRCPC0 / MRCPC1 / MRCBPROT0 / MRCBPROT1 / MRCFLR
 * =============================================================================
 */

typedef enum : uint8_t {
  /* HUM Ch 59 "MRPSC : MRAM Program Speed Control Register" p 3575 */
  k_ra8_mrpsc_mask_mhspen = 0x01U, 
} ra8_mrpsc_mask_t;

typedef enum : uint16_t {
  /* HUM Ch 59 "MRCPC0 : Code MRAM Program Control Register" p 3575 */
  k_ra8_mrcpc0_key_enable  = 0x8601U, 
  k_ra8_mrcpc0_key_disable = 0x8600U, 
} ra8_mrcpc0_t;

typedef enum : uint16_t {
  /* HUM Ch 59 "MRCPC1 : Code MRAM Program Control for Secure Register" p 3576 */
  k_ra8_mrcpc1_key_enable  = 0x6801U, 
  k_ra8_mrcpc1_key_disable = 0x6800U, 
} ra8_mrcpc1_t;

typedef enum : uint16_t {
  /* HUM Ch 59 "MRCBPROT0 : Code MRAM Block Protection (NS)" p 3576 */
  k_ra8_mrcbprot0_key_lock   = 0x8800U, 
  k_ra8_mrcbprot0_key_unlock = 0x8801U, 
} ra8_mrcbprot0_t;

typedef enum : uint16_t {
  /* HUM Ch 59 "MRCBPROT1 : Code MRAM Block Protection (S)" p 3577 */
  k_ra8_mrcbprot1_key_lock   = 0x4400U, 
  k_ra8_mrcbprot1_key_unlock = 0x4401U, 
} ra8_mrcbprot1_t;

typedef enum : uint16_t {
  /* HUM Ch 59 "MRCFLR : Code MRAM Flush Register" p 3580 */
  k_ra8_mrcflr_key_flush = 0xC301U, 
} ra8_mrcflr_t;
 
/* =============================================================================
 * Update-transfer registers (MCTRCNTR / MCTRSTATR / MCTRLSR)
 * =============================================================================
 */

typedef enum : uint16_t {
  /* HUM Ch 59 "MCTRCNTR : MRAM Update Transfer Control" p 3566 */
  k_ra8_mctrcntr_key        = 0xA500U, 
  k_ra8_mctrcntr_mask_start = 0x0001U, 
} ra8_mctrcntr_t;

typedef enum : uint8_t {
  /* HUM Ch 59 "MCTRLSR : MRAM Update Transfer List Select" p 3567 */
  k_ra8_mctrlsr_mask_list_sel = 0x07U, 
} ra8_mctrlsr_mask_t;

typedef enum : uint16_t {
  /* HUM Ch 59 "MCTRSTATR : MRAM Update Transfer Status" p 3568 */
  k_ra8_mctrstatr_mask_busy = 0x0001U, 
  k_ra8_mctrstatr_mask_done = 0x0004U, 
  k_ra8_mctrstatr_mask_err  = 0x00F8U, 
} ra8_mctrstatr_mask_t;
 
/* =============================================================================
 * MCNTSELR (counter select) and ARC layout
 * =============================================================================
 */

typedef enum : uint8_t {
  /* HUM Ch 59 "MCNTSELR : MRAM Counter Select Register" p 3565 */
  k_ra8_mcntselr_sec    = 1U,    
  k_ra8_mcntselr_oembl  = 2U,    
  k_ra8_mcntselr_nsec_0 = 4U,    
  k_ra8_mcntselr_mask   = 0x07U, 
} ra8_mcntselr_t;

typedef enum : uint32_t {
  /* HUM Ch 7.2.22 "ARC_SEC" p 296 */
  k_ra8_arc_sec_max_bits = 64UL, 
  /* HUM Ch 7.2.21 "ARCCS OEMBL counter" p 296 */
  k_ra8_arc_oembl_max_bits = 64UL, 
  /* HUM Ch 7.2.21 "ARCCS NSEC single-counter mode" p 296 */
  k_ra8_arc_nsec_single = 256UL, 
  /* HUM Ch 7.2.21 "ARCCS NSEC multi-counter mode" p 296 */
  k_ra8_arc_nsec_multiple = 64UL, 
  /* HUM Ch 7.2.21 "ARCCS ARCNS field mask" p 296 */
  k_ra8_arc_arccs_mask = 0x03UL, 
  /* HUM Ch 7.2.21 "ARCCS ARCNS=1 selects single big counter" p 296 */
  k_ra8_arc_arcns_single = 1UL, 
} ra8_arc_limits_t;
 
/* =============================================================================
 * MACI command opcodes and configuration-set targets
 * =============================================================================
 */

typedef enum : uint8_t {
  /* HUM Ch 59.7.4.6 "Status Clear Command" p 3593 */
  k_ra8_maci_cmd_status_clear = 0x50U, 
  /* HUM Ch 59.7.4.7 "Forced Stop Command" p 3593 */
  k_ra8_maci_cmd_forced_stop = 0xB3U, 
  /* HUM Ch 59.7.4.5 "Program Command" Figure 59.13 p 3591 */
  k_ra8_maci_cmd_program = 0xE8U, 
  /* HUM Ch 59.7.4.8 "Configuration Set Command" p 3594 */
  k_ra8_maci_cmd_config_set = 0x40U, 
  /* HUM Ch 59.7.4.5 "Program Command" p 3591 */
  k_ra8_maci_cmd_word_count_n = 0x08U, 
  /* HUM Ch 59.7.4.9 "Increment Counter Command" p 3595 */
  k_ra8_maci_cmd_increment_counter = 0x35U, 
  /* HUM Ch 59.7.4.10 "Read Counter Command" p 3596 */
  k_ra8_maci_cmd_read_counter = 0x39U, 
  /* HUM Ch 59.7.4.5 "Program Command" p 3592 */
  k_ra8_maci_cmd_final = 0xD0U, 
} ra8_maci_cmd_t;

typedef enum : uint32_t {
  /* HUM Ch 7 "Option-Setting Memory" p 278 */
  k_ra8_msaddr_config_set_startup = 0x02C9F070UL, 
  /* HUM Ch 7 "OFS SAS region" p 278 */
  k_ra8_msaddr_ofs_sas = 0x02C9F074UL, 
} ra8_msaddr_t;
 
/* =============================================================================
 * Driver-facing data constants
 * =============================================================================
 */

typedef enum : uint32_t {
  /* HUM Ch 59.4.2 "Code MRAM programming" p 3548 */
  k_ra8_mram_write_size_bytes = 32UL, 
  /* HUM Ch 59.4.2 "Block layout" p 3548 */
  k_ra8_mram_block_size_bytes = 32UL, 
  /* HUM Ch 59 "Configuration-set MACI sequence" p 3550 */
  k_ra8_mram_config_set_word_count = 8UL,  
  k_ra8_mram_config_set_bytes      = 16UL, 
  /* HUM Ch 7.2.23 "ARC_NSEC layout" p 297 */
  k_ra8_mram_arc_max_words = 16UL, 
} ra8_mram_data_const_t;
 
/* =============================================================================
 * Inline accessors: register windows and MACI command issue area
 * =============================================================================
 */

static inline volatile uint8_t* ra8_mram_reg8(uint16_t off)
{
  return (volatile uint8_t*)(k_ra8_mram_base_addr + (uintptr_t)off);
}

static inline volatile uint16_t* ra8_mram_reg16(uint16_t off)
{
  return (volatile uint16_t*)(k_ra8_mram_base_addr + (uintptr_t)off);
}

static inline volatile uint32_t* ra8_mram_reg32(uint16_t off)
{
  return (volatile uint32_t*)(k_ra8_mram_base_addr + (uintptr_t)off);
}

static inline volatile uint8_t* ra8_mram_cmd8(void)
{
  return (volatile uint8_t*)k_ra8_mram_cmd_base;
}

static inline volatile uint16_t* ra8_mram_cmd16(void)
{
  return (volatile uint16_t*)k_ra8_mram_cmd_base;
}
 
#ifdef __cplusplus
}
#endif