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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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CRC calculator register layout for the Renesas RA8D2. More...
#include <stdint.h>Go to the source code of this file.
Data Structures | |
| struct | r_crc_regs_t |
| CRC peripheral register block. More... | |
Enumerations | |
| enum | ra8_crc_addr_t : uintptr_t { k_ra8_crc_base_addr = 0x40310000UL } |
| CRC peripheral base address. More... | |
| enum | ra8_crc_poly_t : uint8_t { k_ra8_crc_poly_none = 0U , k_ra8_crc_poly_8 = 1U , k_ra8_crc_poly_16 = 2U , k_ra8_crc_poly_16_ccitt = 3U , k_ra8_crc_poly_32_ieee802_3 = 4U , k_ra8_crc_poly_32c_rev = 5U } |
| Polynomial selection values written to CRCCR0.GPS[2:0]. More... | |
| enum | ra8_crc_bit_order_t : uint8_t { k_ra8_crc_lsb_first = 0U , k_ra8_crc_msb_first = 1U } |
| Bit-order for CRC calculation, written to CRCCR0.LMS (bit 6). More... | |
Functions | |
| static volatile r_crc_regs_t * | ra8_crc (void) |
| Get pointer to the CRC peripheral register block. | |
CRC calculator register layout for the Renesas RA8D2.
The RA8D2 CRC unit lives at 0x40310000 (HUM Ch 48 p 3180) and is a single 16-byte register block. The unit supports five hard-wired polynomials selected via CRCCR0.GPS[2:0]:
Input data is fed via CRCDIR (32-bit access for CRC-32/32C) or CRCDIR_BY (8-bit access alias for CRC-8/16/CCITT). The running result is read from CRCDOR (32-bit), CRCDOR_HA (16-bit half-word alias for CRC-16/CCITT), or CRCDOR_BY (8-bit alias for CRC-8). CRCDIR and CRCDIR_BY share the same physical address +0x04; CRCDOR, CRCDOR_HA and CRCDOR_BY share the same physical address +0x08. They are union aliases in the FSP CMSIS header.
Layout cross-verified against FSP R_CRC_Type in R7KA8D2KF_core0.h (lines 5289-5386, total size 16 bytes).
Definition in file ra8_crc_regs.h.
| enum ra8_crc_addr_t : uintptr_t |
CRC peripheral base address.
| Enumerator | |
|---|---|
| k_ra8_crc_base_addr | HUM Ch 48 p 3180 "CRC base". |
Definition at line 43 of file ra8_crc_regs.h.
| enum ra8_crc_bit_order_t : uint8_t |
Bit-order for CRC calculation, written to CRCCR0.LMS (bit 6).
Mirrors FSP crc_bit_order_t. HUM Ch 48.2.1 p 3181.
| Enumerator | |
|---|---|
| k_ra8_crc_lsb_first | LMS=0 LSB-first communication. |
| k_ra8_crc_msb_first | LMS=1 MSB-first communication. |
Definition at line 69 of file ra8_crc_regs.h.
| enum ra8_crc_poly_t : uint8_t |
Polynomial selection values written to CRCCR0.GPS[2:0].
Values mirror FSP crc_polynomial_t and HUM Ch 48.2.1 "CRCCR0 : CRC Control Register 0" (p 3181) GPS field encoding.
Definition at line 54 of file ra8_crc_regs.h.
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inlinestatic |
Get pointer to the CRC peripheral register block.
Definition at line 105 of file ra8_crc_regs.h.
References k_ra8_crc_base_addr.
Referenced by internal_crc_feed_bytes(), internal_crc_feed_words(), ra8_crc_compute(), ra8_crc_deinit(), ra8_crc_enter_stop(), ra8_crc_get_status(), ra8_crc_init(), ra8_crc_reset(), and ra8_crc_set_poly().