ra8_cnecc_regs.h File Reference

CANFD ECC (CNECC) register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"

Include dependency graph for ra8_cnecc_regs.h:

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Data Structures
struct	r_cnecc_regs_t
	Per-instance CNECC register window (size = 0x14 bytes). More...

Enumerations
enum	ra8_cnecc_addr_t : uintptr_t {   k_ra8_cnecc0_base_addr = 0x4036F200UL ,   k_ra8_cnecc1_base_addr = 0x4036F300UL }
	Memory-mapped base addresses for the two CNECC instances. More...
enum	ra8_cnecc_limits_t : uint16_t {   k_ra8_cnecc_instance_count = 2U ,   k_ra8_cnecc_stride = 0x100U ,   k_ra8_cnecc_ead_max = 0x3FFU }
	Instance count and per-instance stride. More...
enum	ra8_cnecc_ctl_bit_t : uint8_t {   k_ra8_cnecc_bit_ecemf = 0U ,   k_ra8_cnecc_bit_ecer1f = 1U ,   k_ra8_cnecc_bit_ecer2f = 2U ,   k_ra8_cnecc_bit_ec1edic = 3U ,   k_ra8_cnecc_bit_ec2edic = 4U ,   k_ra8_cnecc_bit_ec1ecp = 5U ,   k_ra8_cnecc_bit_ecervf = 6U ,   k_ra8_cnecc_bit_ecer1c = 9U ,   k_ra8_cnecc_bit_ecer2c = 10U ,   k_ra8_cnecc_bit_ecovff = 11U ,   k_ra8_cnecc_bit_emca0 = 14U ,   k_ra8_cnecc_bit_emca1 = 15U ,   k_ra8_cnecc_bit_ecsedf0 = 16U ,   k_ra8_cnecc_bit_ecdedf0 = 17U }
	EC710CTL bit positions. More...
enum	ra8_cnecc_ctl_mask_t : uint32_t {   k_ra8_cnecc_mask_ecemf = 0x00000001UL ,   k_ra8_cnecc_mask_ecer1f = 0x00000002UL ,   k_ra8_cnecc_mask_ecer2f = 0x00000004UL ,   k_ra8_cnecc_mask_ec1edic = 0x00000008UL ,   k_ra8_cnecc_mask_ec2edic = 0x00000010UL ,   k_ra8_cnecc_mask_ec1ecp = 0x00000020UL ,   k_ra8_cnecc_mask_ecervf = 0x00000040UL ,   k_ra8_cnecc_mask_ecer1c = 0x00000200UL ,   k_ra8_cnecc_mask_ecer2c = 0x00000400UL ,   k_ra8_cnecc_mask_ecovff = 0x00000800UL ,   k_ra8_cnecc_mask_emca = 0x0000C000UL ,   k_ra8_cnecc_mask_emca_unlock = 0x00004000UL ,   k_ra8_cnecc_mask_ecsedf0 = 0x00010000UL ,   k_ra8_cnecc_mask_ecdedf0 = 0x00020000UL ,   k_ra8_cnecc_mask_clear_all = 0x00000600UL ,   k_ra8_cnecc_mask_status_all = 0x00030806UL ,   k_ra8_cnecc_mask_irq_all = 0x00000018UL ,   k_ra8_cnecc_mask_ctl_writable }
	EC710CTL bit masks (32-bit register). More...
enum	ra8_cnecc_tmc_bit_t : uint8_t {   k_ra8_cnecc_bit_ecdcs = 1U ,   k_ra8_cnecc_bit_ectmce = 7U ,   k_ra8_cnecc_bit_etma0 = 14U ,   k_ra8_cnecc_bit_etma1 = 15U }
	EC710TMC bit positions (16-bit register). More...
enum	ra8_cnecc_tmc_mask_t : uint16_t {   k_ra8_cnecc_mask_ecdcs = 0x0002U ,   k_ra8_cnecc_mask_ectmce = 0x0080U ,   k_ra8_cnecc_mask_etma = 0xC000U ,   k_ra8_cnecc_mask_etma_unlock = 0x8000U ,   k_ra8_cnecc_mask_test_disable = 0x8000U ,   k_ra8_cnecc_mask_test_enable = 0x8080U ,   k_ra8_cnecc_mask_test_subst = 0x8082U }
	EC710TMC bit masks (16-bit register). More...
enum	ra8_cnecc_ead_mask_t : uint32_t {   k_ra8_cnecc_mask_ecead = 0x000003FFUL ,   k_ra8_cnecc_mask_ead_reserved = 0xFFFFFC00UL }
	EC710EAD0 field mask (10-bit RAM offset). More...

Functions
static volatile r_cnecc_regs_t *	ra8_cnecc (uint8_t instance)
	Get pointer to CNECC instance instance.

Detailed Description

CANFD ECC (CNECC) register layout for the RA8D2.

The RA8D2 ships two CANFD message-buffer SRAM (MBRAM) ECC blocks (ECCMB0 and ECCMB1). Each instance is a small 0x14-byte window that detects single-bit ECC errors (correctable) and dual-bit ECC errors (uncorrectable) on the 32-bit CANFD message buffer SRAM that sits behind the corresponding CANFD channel (CAN0 for ECCMB0, CAN1 for ECCMB1).

Per-instance registers (HUM Ch 42.2 p 2868-2873):

Offset	Name	Width	Purpose
0x00	EC710CTL	32	Enable / status / IRQ / clear
0x04	EC710TMC	16	Test-mode control (decoder fault inject)
0x06	(reserved)	16
0x08	(reserved)	32
0x0C	EC710TED	32	Test substitute data (fault inject src)
0x10	EC710EAD0	32	Captured faulting RAM offset

Layout cross-checked against FSP R_ECCMB0_Type in R7KA8D2KF_core0.h (size = 20 bytes, base 0x4036F200 for instance 0, 0x4036F300 for instance 1, NS aliases at 0x5036F200 / 0x5036F300).

The single shared interrupt vector for both instances is CANn_MRAM_ERI (HUM 42.4 p 2875).

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Definition in file ra8_cnecc_regs.h.

Enumeration Type Documentation

ra8_cnecc_addr_t

enum ra8_cnecc_addr_t : uintptr_t

Memory-mapped base addresses for the two CNECC instances.

Secure aliases (0x4036F200 family). The non-secure aliases (0x5036F200 family) are not mirrored here – security-attribute routing is the job of the SAR layer, not the per-driver register header. HUM Ch 42.2.1 "Base address" line, p 2868.

Enumerator
k_ra8_cnecc0_base_addr	ECCMB0 (CAN0 MRAM).
k_ra8_cnecc1_base_addr	ECCMB1 (CAN1 MRAM).

Definition at line 57 of file ra8_cnecc_regs.h.

ra8_cnecc_ctl_bit_t

enum ra8_cnecc_ctl_bit_t : uint8_t

EC710CTL bit positions.

Verified against HUM Ch 42.2.1 "EC710CTL" p 2868 and FSP R_ECCMB0_EC710CTL_*_Pos defines in R7KA8D2KF_core0.h.

Enumerator
k_ra8_cnecc_bit_ecemf	Present-cycle ECC error flag (R).
k_ra8_cnecc_bit_ecer1f	1-bit error latched (R).
k_ra8_cnecc_bit_ecer2f	2-bit error latched (R).
k_ra8_cnecc_bit_ec1edic	1-bit error IRQ enable (R/W).
k_ra8_cnecc_bit_ec2edic	2-bit error IRQ enable (R/W).
k_ra8_cnecc_bit_ec1ecp	1-bit-error correction permission (R/W).
k_ra8_cnecc_bit_ecervf	Error judgment enable (R/W, EMCA-gated).
k_ra8_cnecc_bit_ecer1c	Write-1 to clear ECER1F (R/W).
k_ra8_cnecc_bit_ecer2c	Write-1 to clear ECER2F (R/W).
k_ra8_cnecc_bit_ecovff	Address-capture overflow flag (R).
k_ra8_cnecc_bit_emca0	EMCA[1:0] write-trigger lo (R/W).
k_ra8_cnecc_bit_emca1	EMCA[1:0] write-trigger hi (R/W).
k_ra8_cnecc_bit_ecsedf0	1-bit error address captured flag (R).
k_ra8_cnecc_bit_ecdedf0	2-bit error address captured flag (R).

Definition at line 80 of file ra8_cnecc_regs.h.

ra8_cnecc_ctl_mask_t

enum ra8_cnecc_ctl_mask_t : uint32_t

EC710CTL bit masks (32-bit register).

Cross-checked against FSP R_ECCMB0_EC710CTL_*_Msk defines. HUM Ch 42.2.1 p 2870 EMCA[1:0] = 01b is the write-unlock pattern for ECERVF.

Enumerator
k_ra8_cnecc_mask_ecemf	ECEMF.
k_ra8_cnecc_mask_ecer1f	ECER1F.
k_ra8_cnecc_mask_ecer2f	ECER2F.
k_ra8_cnecc_mask_ec1edic	EC1EDIC.
k_ra8_cnecc_mask_ec2edic	EC2EDIC.
k_ra8_cnecc_mask_ec1ecp	EC1ECP.
k_ra8_cnecc_mask_ecervf	ECERVF.
k_ra8_cnecc_mask_ecer1c	ECER1C (write-1-clear).
k_ra8_cnecc_mask_ecer2c	ECER2C (write-1-clear).
k_ra8_cnecc_mask_ecovff	ECOVFF overflow.
k_ra8_cnecc_mask_emca	EMCA[1:0] @ [15:14].
k_ra8_cnecc_mask_emca_unlock	EMCA = 01b -> unlock ECERVF.
k_ra8_cnecc_mask_ecsedf0	1-bit address captured.
k_ra8_cnecc_mask_ecdedf0	2-bit address captured.
k_ra8_cnecc_mask_clear_all	ECER1C | ECER2C bundle.
k_ra8_cnecc_mask_status_all	ECER1F|ECER2F|ECOVFF|ECSEDF0|ECDEDF0.
k_ra8_cnecc_mask_irq_all	EC1EDIC | EC2EDIC.
k_ra8_cnecc_mask_ctl_writable	Bits we may legally write (excludes RO + reserved).

Definition at line 106 of file ra8_cnecc_regs.h.

ra8_cnecc_ead_mask_t

enum ra8_cnecc_ead_mask_t : uint32_t

EC710EAD0 field mask (10-bit RAM offset).

HUM Ch 42.2.4 p 2872: ECEAD[9:0] holds the captured RAM word offset; bits [31:10] are reserved and read as 0.

Enumerator
k_ra8_cnecc_mask_ecead	ECEAD[9:0].
k_ra8_cnecc_mask_ead_reserved	Bits [31:10] always 0.

Definition at line 171 of file ra8_cnecc_regs.h.

ra8_cnecc_limits_t

enum ra8_cnecc_limits_t : uint16_t

Instance count and per-instance stride.

Enumerator
k_ra8_cnecc_instance_count	ECCMB0 + ECCMB1.
k_ra8_cnecc_stride	Bytes between instances.
k_ra8_cnecc_ead_max	Largest valid ECEAD[9:0].

Definition at line 66 of file ra8_cnecc_regs.h.

ra8_cnecc_tmc_bit_t

enum ra8_cnecc_tmc_bit_t : uint8_t

EC710TMC bit positions (16-bit register).

HUM Ch 42.2.2 p 2871, cross-checked against FSP R_ECCMB0_EC710TMC_*_Pos.

Enumerator
k_ra8_cnecc_bit_ecdcs	ECDCS decoder input source (R/W).
k_ra8_cnecc_bit_ectmce	ECTMCE test-mode enable (R/W).
k_ra8_cnecc_bit_etma0	ETMA[1:0] write-trigger lo.
k_ra8_cnecc_bit_etma1	ETMA[1:0] write-trigger hi.

Definition at line 136 of file ra8_cnecc_regs.h.

ra8_cnecc_tmc_mask_t

enum ra8_cnecc_tmc_mask_t : uint16_t

EC710TMC bit masks (16-bit register).

HUM Ch 42.2.2 p 2871. ETMA[1:0] = 10b is the write-unlock pattern for ECTMCE; the figure 42.2 procedure on p 2875 also writes the literal values 0x8000 (disable) / 0x8080 (enable) / 0x8082 (substitute decoder input) to this register.

Enumerator
k_ra8_cnecc_mask_ecdcs	ECDCS decoder input select.
k_ra8_cnecc_mask_ectmce	ECTMCE test-mode enable.
k_ra8_cnecc_mask_etma	ETMA[1:0] @ [15:14].
k_ra8_cnecc_mask_etma_unlock	ETMA = 10b -> unlock ECTMCE.
k_ra8_cnecc_mask_test_disable	Figure 42.2 "Disable test".
k_ra8_cnecc_mask_test_enable	Figure 42.2 "Enable test".
k_ra8_cnecc_mask_test_subst	Figure 42.2 "Use ECEDB".

Definition at line 153 of file ra8_cnecc_regs.h.

Function Documentation

ra8_cnecc()

volatile r_cnecc_regs_t * ra8_cnecc ( uint8_t instance )

inlinestatic

Get pointer to CNECC instance instance.

Parameters

[in]

instance

Instance index (0..1).

Returns

Volatile pointer to the instance register block, or nullptr if instance is out of range.

Precondition

instance < k_ra8_cnecc_instance_count.

Postcondition

Returned pointer is either nullptr or a stable address within the CNECC peripheral window.

Definition at line 205 of file ra8_cnecc_regs.h.

References k_ra8_cnecc0_base_addr, k_ra8_cnecc_instance_count, and k_ra8_cnecc_stride.

Referenced by internal_apply_instance(), ra8_cnecc_clear_status(), ra8_cnecc_deinit(), ra8_cnecc_disable_instance(), ra8_cnecc_enable_instance(), ra8_cnecc_enter_standby(), ra8_cnecc_get_status(), ra8_cnecc_inject_fault(), ra8_cnecc_isr_handler(), ra8_cnecc_set_correction_permission(), ra8_cnecc_set_irq_enables(), ra8_cnecc_test_mode_active(), and ra8_cnecc_test_mode_disable().