board_periph_usbhs_host.c

Go to the documentation of this file.

 
#include <stdint.h>
#include <stdio.h>
#include <string.h>
 
#include "board_periph_block.h"
#include "board_usb.h"
#include "emu_host_io_internal.h"
#include "ra8_usb_regs.h"
 
/* =============================================================================
 * Window geometry + model sizing.
 * =============================================================================
 */

typedef enum : uint64_t {
  k_usbhs_base       = 0x40351000UL, 
  k_usbhs_span       = 0x200UL,      
  k_usbhs_words      = 0x200UL / 2U, 
  k_usbhs_dev_span   = 0x100UL,      
  k_usbhs_pipes      = 10UL,         
  k_usbhs_pkt_cap    = 512UL,        
  k_usbhs_din_cap    = 512UL,        
  k_usbhs_setup_len  = 8UL,          
  k_usbhs_report_ord = 155UL,        
} usbhs_geom_t;
 
/* =============================================================================
 * Host-role register bit/field values not carried by ra8_usb_regs.h.
 * =============================================================================
 */

typedef enum : uint16_t {
  k_usbhs_lnst_j  = 0x0001U, 
  k_usbhs_rhst_fs = 0x0002U, 
} usbhs_lines_t;

typedef enum : uint8_t {
  k_usbhs_dvstctr_usbrst = 6U, 
} usbhs_dvstctr_bit_t;

typedef enum : uint16_t {
  k_usbhs_plllock = 0x0001U, 
} usbhs_pllsta_bit_t;

typedef enum : uint16_t {
  k_usbhs_dcp_bit = 0x0001U, 
} usbhs_status_bit_t;

typedef enum : uint8_t {
  k_usbhs_setup_dir_in    = 0x80U, 
  k_usbhs_breq_set_addr   = 0x05U, 
  k_usbhs_breq_set_config = 0x09U, 
} usbhs_usb_std_t;

typedef enum : uint32_t {
  k_usbhs_byte_bits  = 8U,    
  k_usbhs_byte_mask  = 0xFFU, 
  k_usbhs_epnum_mask = 0x0FU, 
  k_usbhs_cfifo_h    = 2U,    
  k_usbhs_cfifo_hh   = 3U,    
} usbhs_lit_t;

typedef enum : uint8_t {
  k_usbhs_setup_bmrt    = 0U, 
  k_usbhs_setup_breq    = 1U, 
  k_usbhs_setup_wval_lo = 2U, 
  k_usbhs_setup_wval_hi = 3U, 
  k_usbhs_setup_widx_lo = 4U, 
  k_usbhs_setup_widx_hi = 5U, 
  k_usbhs_setup_wlen_lo = 6U, 
  k_usbhs_setup_wlen_hi = 7U, 
} usbhs_setup_idx_t;
 
/* =============================================================================
 * Model state.
 * =============================================================================
 */

typedef struct {
  uint16_t reg[k_usbhs_words]; 
 
  uint8_t  din[k_usbhs_din_cap]; 
  uint16_t din_len;              
  uint16_t din_rd;               
  bool     din_ready;            
 
  uint8_t setup[k_usbhs_setup_len]; 
  bool    ctrl_read;                
  uint8_t ctrl_breq;                
  bool    ctrl_status_pending;      
 
  uint8_t  pout[k_usbhs_pipes][k_usbhs_pkt_cap]; 
  uint16_t pout_len[k_usbhs_pipes];              
  bool     pout_wait[k_usbhs_pipes];             
 
  uint8_t  pin[k_usbhs_pipes][k_usbhs_pkt_cap]; 
  uint16_t pin_len[k_usbhs_pipes];              
  uint16_t pin_rd[k_usbhs_pipes];               
  bool     pin_ready[k_usbhs_pipes];            
 
  uint8_t  pipe_ep[k_usbhs_pipes];   
  uint16_t pipe_maxp[k_usbhs_pipes]; 
  uint16_t pipe_pid[k_usbhs_pipes];  
 
  bool prev_usbrst; 
 
  uint32_t setups;   
  uint32_t bulk_out; 
  uint32_t bulk_in;  
} usbhs_state_t;
 
static usbhs_state_t s_hs;
 
/* =============================================================================
 * Small register / pipe helpers (defined before the dispatchers that use them).
 * =============================================================================
 */

RA8_INTERNAL static uint32_t internal_hs_word(uint64_t off)
{
  return (uint32_t)((off & ~(uint64_t)1U) / 2U);
}

RA8_INTERNAL static uint16_t internal_hs_reg(uint16_t off)
{
  return s_hs.reg[internal_hs_word((uint64_t)off)];
}

RA8_INTERNAL static void internal_hs_set(uint16_t off, uint16_t value)
{
  s_hs.reg[internal_hs_word((uint64_t)off)] = value;
}

RA8_INTERNAL static void internal_hs_or(uint16_t off, uint16_t bits)
{
  internal_hs_set(off, (uint16_t)(internal_hs_reg(off) | bits));
}

RA8_INTERNAL static uint8_t internal_hs_curpipe(void)
{
  const uint16_t sel =
    internal_hs_reg((uint16_t)k_ra8_usb_off_cfifosel) & (uint16_t)k_ra8_fifosel_curpipe;
  return (uint8_t)(sel % (uint8_t)k_usbhs_pipes);
}

RA8_INTERNAL static uint8_t internal_hs_pipesel(void)
{
  return (uint8_t)(internal_hs_reg((uint16_t)k_ra8_usb_off_pipesel) % (uint8_t)k_usbhs_pipes);
}

RA8_INTERNAL static bool internal_hs_is_pipectr(uint64_t off)
{
  const uint64_t lo = (uint64_t)k_ra8_usb_off_pipectr;
  const uint64_t hi = lo + ((uint64_t)k_ra8_usb_pipectr_count * 2U);
  return (off >= lo) && (off < hi);
}

RA8_INTERNAL static uint8_t internal_hs_pipectr_index(uint64_t off)
{
  const uint8_t p = (uint8_t)(((off - (uint64_t)k_ra8_usb_off_pipectr) / 2U) + 1U);
  return (uint8_t)(p % (uint8_t)k_usbhs_pipes);
}

RA8_INTERNAL static uint16_t internal_hs_cfifo_dtln(void)
{
  const uint8_t p = internal_hs_curpipe();
  if (p == 0U) {
    return (uint16_t)(s_hs.din_len - s_hs.din_rd);
  }
  return (uint16_t)(s_hs.pin_len[p] - s_hs.pin_rd[p]);
}
 
/* =============================================================================
 * CFIFO data port -- move payload bytes between the host and the staging buffers.
 * =============================================================================
 */

RA8_INTERNAL static void internal_hs_cfifo_write(uint32_t value, unsigned size)
{
  const uint8_t p = internal_hs_curpipe();
  for (unsigned i = 0U; (i < size) && (s_hs.pout_len[p] < (uint16_t)k_usbhs_pkt_cap); i++) {
    s_hs.pout[p][s_hs.pout_len[p]] =
      (uint8_t)((value >> (i * (unsigned)k_usbhs_byte_bits)) & (uint32_t)k_usbhs_byte_mask);
    s_hs.pout_len[p]++;
  }
}

RA8_INTERNAL static uint32_t internal_hs_cfifo_read(unsigned size)
{
  const uint8_t  p    = internal_hs_curpipe();
  uint8_t*       data = (p == 0U) ? s_hs.din : s_hs.pin[p];
  uint16_t*      rd   = (p == 0U) ? &s_hs.din_rd : &s_hs.pin_rd[p];
  const uint16_t len  = (p == 0U) ? s_hs.din_len : s_hs.pin_len[p];
  uint32_t       v    = 0U;
  for (unsigned i = 0U; (i < size) && (*rd < len); i++) {
    v |= (uint32_t)((uint32_t)data[*rd] << (i * (unsigned)k_usbhs_byte_bits));
    (*rd)++;
  }
  return v;
}
 
/* =============================================================================
 * Bulk pipe helpers.
 * =============================================================================
 */

RA8_INTERNAL static void internal_hs_bulk_out_commit(uc_engine* uc)
{
  const uint8_t p = internal_hs_curpipe();
  if (p == 0U) {
    /* DCP OUT: a control-write data stage (e.g. a DFU_DNLOAD block). Deliver it
     * to the device and gate BEMP on the device draining it. A zero-length DCP
     * BVAL is instead the control-read OUT status ZLP, driven from the CCPL
     * path -- ignore it here. */
    if (s_hs.pout_len[0] > 0U) {
      board_usb_bridge_dcp_out(uc, s_hs.pout[0], s_hs.pout_len[0]);
      s_hs.pout_wait[0] = true;
      s_hs.pout_len[0]  = 0U;
    }
    return;
  }
  board_usb_bridge_bulk_out(uc, s_hs.pipe_ep[p], s_hs.pout[p], s_hs.pout_len[p]);
  s_hs.bulk_out++;
  /* DEFER the buffer-empty (BEMP) signal until the device firmware drains this
   * packet from its CFIFO: raising it now lets the polled host push the next
   * OUT packet immediately, overwriting the undrained bank (which wedged the
   * multi-packet WRITE(10) data stage -- the device saw only the last chunk and
   * never produced the CSW). internal_hs_bempsts_read() raises BEMP on device drain. */
  s_hs.pout_wait[p] = true;
  s_hs.pout_len[p]  = 0U;
}

RA8_INTERNAL static uint16_t internal_hs_bempsts_read(void)
{
  if (s_hs.pout_wait[0] && board_usb_bridge_dcp_out_consumed()) {
    s_hs.pout_wait[0] = false; /* DCP control-write data stage drained by device. */
    internal_hs_or((uint16_t)k_ra8_usb_off_bempsts, (uint16_t)k_usbhs_dcp_bit);
  }
  for (uint8_t p = 1U; p < (uint8_t)k_usbhs_pipes; p++) {
    if (s_hs.pout_wait[p] && board_usb_bridge_bulk_out_consumed(s_hs.pipe_ep[p])) {
      s_hs.pout_wait[p] = false;
      internal_hs_or((uint16_t)k_ra8_usb_off_bempsts, (uint16_t)(1U << p));
    }
  }
  return internal_hs_reg((uint16_t)k_ra8_usb_off_bempsts);
}

RA8_INTERNAL static void internal_hs_ctrl_status_complete(uc_engine* uc)
{
  s_hs.din_len   = 0U;
  s_hs.din_rd    = 0U;
  s_hs.din_ready = true;
  internal_hs_or((uint16_t)k_ra8_usb_off_brdysts, (uint16_t)k_usbhs_dcp_bit);
  if (s_hs.ctrl_breq == (uint8_t)k_usbhs_breq_set_config) {
    board_usb_bridge_mark_configured(uc);
  }
}

RA8_INTERNAL static uint16_t internal_hs_brdysts_read(uc_engine* uc)
{
  if (s_hs.ctrl_status_pending && board_usb_bridge_dev_took_ccpl()) {
    s_hs.ctrl_status_pending = false;
    internal_hs_ctrl_status_complete(uc);
  }
  if (!s_hs.din_ready && board_usb_bridge_dcp_in_ready()) {
    s_hs.din_len   = board_usb_bridge_dcp_in_take(s_hs.din, (uint16_t)k_usbhs_din_cap);
    s_hs.din_rd    = 0U;
    s_hs.din_ready = true;
    internal_hs_or((uint16_t)k_ra8_usb_off_brdysts, (uint16_t)k_usbhs_dcp_bit);
  }
  for (uint8_t p = 1U; p < (uint8_t)k_usbhs_pipes; p++) {
    const bool armed = (s_hs.pipe_pid[p] & (uint16_t)k_ra8_pid_mask) == (uint16_t)k_ra8_pid_buf;
    if (!armed || s_hs.pin_ready[p]) {
      continue;
    }
    if (board_usb_bridge_bulk_in_ready(s_hs.pipe_ep[p])) {
      s_hs.pin_len[p] =
        board_usb_bridge_bulk_in_take(uc, s_hs.pipe_ep[p], s_hs.pin[p], (uint16_t)k_usbhs_pkt_cap);
      s_hs.pin_rd[p]    = 0U;
      s_hs.pin_ready[p] = true;
      s_hs.bulk_in++;
      internal_hs_or((uint16_t)k_ra8_usb_off_brdysts, (uint16_t)(1U << p));
    }
  }
  return internal_hs_reg((uint16_t)k_ra8_usb_off_brdysts);
}

RA8_INTERNAL static void internal_hs_brdysts_write(uint16_t value)
{
  const uint16_t before  = internal_hs_reg((uint16_t)k_ra8_usb_off_brdysts);
  const uint16_t cleared = (uint16_t)(before & (uint16_t)~value); /* 1 -> 0 transitions. */
  internal_hs_set((uint16_t)k_ra8_usb_off_brdysts, (uint16_t)(before & value));
  if ((cleared & (uint16_t)k_usbhs_dcp_bit) != 0U) {
    s_hs.din_ready = false; /* host consumed the DCP IN packet; allow a re-latch. */
  }
  for (uint8_t p = 1U; p < (uint8_t)k_usbhs_pipes; p++) {
    if ((cleared & (uint16_t)(1U << p)) != 0U) {
      s_hs.pin_ready[p] = false; /* host acked this pipe's BRDY; allow the next. */
    }
  }
}
 
/* =============================================================================
 * Control-transfer bridge -- SETUP launch + status completion.
 * =============================================================================
 */

RA8_INTERNAL static void internal_hs_capture_setup(void)
{
  const uint16_t req             = internal_hs_reg((uint16_t)k_ra8_usb_off_usbreq);
  const uint16_t val             = internal_hs_reg((uint16_t)k_ra8_usb_off_usbval);
  const uint16_t indx            = internal_hs_reg((uint16_t)k_ra8_usb_off_usbindx);
  const uint16_t leng            = internal_hs_reg((uint16_t)k_ra8_usb_off_usbleng);
  s_hs.setup[k_usbhs_setup_bmrt] = (uint8_t)(req & (uint16_t)k_usbhs_byte_mask);
  s_hs.setup[k_usbhs_setup_breq] =
    (uint8_t)((req >> (uint16_t)k_usbhs_byte_bits) & (uint16_t)k_usbhs_byte_mask);
  s_hs.setup[k_usbhs_setup_wval_lo] = (uint8_t)(val & (uint16_t)k_usbhs_byte_mask);
  s_hs.setup[k_usbhs_setup_wval_hi] =
    (uint8_t)((val >> (uint16_t)k_usbhs_byte_bits) & (uint16_t)k_usbhs_byte_mask);
  s_hs.setup[k_usbhs_setup_widx_lo] = (uint8_t)(indx & (uint16_t)k_usbhs_byte_mask);
  s_hs.setup[k_usbhs_setup_widx_hi] =
    (uint8_t)((indx >> (uint16_t)k_usbhs_byte_bits) & (uint16_t)k_usbhs_byte_mask);
  s_hs.setup[k_usbhs_setup_wlen_lo] = (uint8_t)(leng & (uint16_t)k_usbhs_byte_mask);
  s_hs.setup[k_usbhs_setup_wlen_hi] =
    (uint8_t)((leng >> (uint16_t)k_usbhs_byte_bits) & (uint16_t)k_usbhs_byte_mask);
}

RA8_INTERNAL static void internal_hs_setup_launch(uc_engine* uc)
{
  internal_hs_capture_setup();
  const uint16_t leng = internal_hs_reg((uint16_t)k_ra8_usb_off_usbleng);
  s_hs.ctrl_breq      = s_hs.setup[k_usbhs_setup_breq];
  s_hs.ctrl_read =
    ((s_hs.setup[k_usbhs_setup_bmrt] & (uint8_t)k_usbhs_setup_dir_in) != 0U) && (leng != 0U);
  s_hs.ctrl_status_pending = false; /* fresh transfer: no deferred status yet. */
  /* Discard any device CCPL left over from the previous control transfer's
   * status stage (a control read leaves it unconsumed). Otherwise a deferred
   * no-data status stage would complete on that stale pulse instead of waiting
   * for THIS request's completion, re-introducing the host-races-device bug. */
  (void)board_usb_bridge_dev_took_ccpl();
 
  s_hs.din_ready = false; /* stale DCP IN state cleared for the fresh transfer. */
  s_hs.din_len   = 0U;
  s_hs.din_rd    = 0U;
  board_usb_bridge_deliver_setup(uc, s_hs.setup);
  s_hs.setups++;
 
  /* The SIE latches SACK when the device ACKs the SETUP; the host gates on it. */
  internal_hs_or((uint16_t)k_ra8_usb_off_intsts1, (uint16_t)(1U << k_ra8_int1_bit_sack));
}

RA8_INTERNAL static void internal_hs_ccpl_status(uc_engine* uc)
{
  if (s_hs.ctrl_read) {
    /* Control-read OUT status: let the device close its side, then report the
     * buffer empty so the host's best-effort BEMP wait returns promptly. */
    board_usb_bridge_ctrl_status(uc);
    internal_hs_or((uint16_t)k_ra8_usb_off_bempsts, (uint16_t)k_usbhs_dcp_bit);
    return;
  }
  /* A host-to-device control write the DEVICE must apply -- every one except
   * SET_ADDRESS, whose USBADDR latch and IN-ZLP status stage the SIE owns:
   * DEFER the host's status-stage BRDY until the device firmware has actually
   * processed the request and pulsed DCPCTR.CCPL. Completing it synchronously
   * races the polled host past a request the device is still applying:
   *  - no-data (SET_CONFIGURATION): it would issue GET_MAX_LUN and the first
   *    BOT CBW before the MSC class had activated and armed its bulk endpoints;
   *  - with-data (DFU_DNLOAD): it would issue the next SETUP -- clearing the
   *    device DCP-OUT staging -- before the device had drained the block, so
   *    the firmware image never lands. The device pulses CCPL only after it
   *    drains the data stage and applies the request, which is exactly the
   *    completion to wait on. internal_hs_brdysts_read() finishes the stage on it. */
  if (s_hs.ctrl_breq != (uint8_t)k_usbhs_breq_set_addr) {
    s_hs.ctrl_status_pending = true;
    return;
  }
  /* SET_ADDRESS: SIE-owned, no device CCPL to wait on -- complete now. */
  internal_hs_ctrl_status_complete(uc);
}

RA8_INTERNAL static void internal_hs_dcpctr_write(uc_engine* uc, uint16_t value)
{
  const uint16_t before = internal_hs_reg((uint16_t)k_ra8_usb_off_dcpctr);
  const uint16_t sureq  = (uint16_t)(1U << k_ra8_dcpctr_bit_sureq);
  const uint16_t ccpl   = (uint16_t)(1U << k_ra8_dcpctr_bit_ccpl);
  if ((value & sureq) != 0U) {
    internal_hs_setup_launch(uc);
  }
  if (((value & ccpl) != 0U) && ((before & ccpl) == 0U)) {
    internal_hs_ccpl_status(uc);
  }
  /* SUREQ self-clears once the SIE has delivered the token; never latch it. */
  internal_hs_set((uint16_t)k_ra8_usb_off_dcpctr, (uint16_t)(value & (uint16_t)~sureq));
}
 
/* =============================================================================
 * CFIFOCTR write (BCLR / BVAL) + bus-reset edge.
 * =============================================================================
 */

RA8_INTERNAL static void internal_hs_cfifoctr_write(uc_engine* uc, uint16_t value)
{
  const uint8_t p = internal_hs_curpipe();
  if ((value & (uint16_t)k_ra8_fifoctr_bclr) != 0U) {
    if (p == 0U) {
      s_hs.din_len   = 0U;
      s_hs.din_rd    = 0U;
      s_hs.din_ready = false;
    } else {
      s_hs.pout_len[p] = 0U;
      s_hs.pin_rd[p]   = s_hs.pin_len[p];
    }
  }
  if ((value & (uint16_t)k_ra8_fifoctr_bval) != 0U) {
    internal_hs_bulk_out_commit(uc);
  }
}

RA8_INTERNAL static void internal_hs_dvstctr0_write(uc_engine* uc, uint16_t value)
{
  const bool usbrst = (value & (uint16_t)(1U << k_usbhs_dvstctr_usbrst)) != 0U;
  internal_hs_set((uint16_t)k_ra8_usb_off_dvstctr0, value);
  if (s_hs.prev_usbrst && !usbrst) {
    board_usb_bridge_bus_reset(uc); /* USBRST released: device returns to Default. */
  }
  s_hs.prev_usbrst = usbrst;
}
 
/* =============================================================================
 * MMIO read / write dispatch.
 * =============================================================================
 */

RA8_INTERNAL static uint64_t internal_hs_read(uc_engine* uc, uint64_t off, unsigned size)
{
  switch ((uint16_t)off) {
    case (uint16_t)k_ra8_usbhs_off_pllsta:
      return (uint64_t)k_usbhs_plllock; /* PHY PLL reported locked so init proceeds. */
    case (uint16_t)k_ra8_usb_off_syssts0:
      return board_usb_dev_attached() ? (uint64_t)k_usbhs_lnst_j : 0U;
    case (uint16_t)k_ra8_usb_off_dvstctr0: {
      uint16_t v = internal_hs_reg((uint16_t)k_ra8_usb_off_dvstctr0);
      if (board_usb_dev_attached()) {
        v = (uint16_t)(v | (uint16_t)k_usbhs_rhst_fs); /* connected FS device speed. */
      }
      return (uint64_t)v;
    }
    case (uint16_t)k_ra8_usb_off_cfifo:
      return (uint64_t)internal_hs_cfifo_read(size);
    case (uint16_t)k_ra8_usb_off_cfifoctr:
      return (uint64_t)((uint16_t)k_ra8_fifoctr_frdy |
                        (internal_hs_cfifo_dtln() & (uint16_t)k_ra8_fifoctr_dtln));
    case (uint16_t)k_ra8_usb_off_brdysts:
      return (uint64_t)internal_hs_brdysts_read(uc);
    case (uint16_t)k_ra8_usb_off_bempsts:
      return (uint64_t)internal_hs_bempsts_read();
    case (uint16_t)k_ra8_usb_off_pipemaxp:
      return (uint64_t)s_hs.pipe_maxp[internal_hs_pipesel()];
    default:
      break;
  }
  if (internal_hs_is_pipectr(off)) {
    return (uint64_t)s_hs.pipe_pid[internal_hs_pipectr_index(off)];
  }
  return (uint64_t)internal_hs_reg((uint16_t)off);
}

RA8_INTERNAL static void
internal_hs_write(uc_engine* uc, uint64_t off, unsigned size, uint64_t value)
{
  const uint16_t v16 = (uint16_t)value;
  switch ((uint16_t)off) {
    case (uint16_t)k_ra8_usb_off_cfifo:
    /* CFIFOH tail. */
    case (uint16_t)((uint16_t)k_ra8_usb_off_cfifo + (uint16_t)k_usbhs_cfifo_h):
    /* CFIFOHH tail. */
    case (uint16_t)((uint16_t)k_ra8_usb_off_cfifo + (uint16_t)k_usbhs_cfifo_hh):
      internal_hs_cfifo_write((uint32_t)value, size); /* full width: HS CFIFO is 32-bit (MBW=32). */
      return;
    case (uint16_t)k_ra8_usb_off_cfifoctr:
      internal_hs_cfifoctr_write(uc, v16);
      return;
    case (uint16_t)k_ra8_usb_off_dcpctr:
      internal_hs_dcpctr_write(uc, v16);
      return;
    case (uint16_t)k_ra8_usb_off_dvstctr0:
      internal_hs_dvstctr0_write(uc, v16);
      return;
    case (uint16_t)k_ra8_usb_off_brdysts:
      internal_hs_brdysts_write(v16);
      return;
    case (uint16_t)k_ra8_usb_off_bempsts:
    case (uint16_t)k_ra8_usb_off_nrdysts:
    case (uint16_t)k_ra8_usb_off_intsts0:
    case (uint16_t)k_ra8_usb_off_intsts1:
      internal_hs_set((uint16_t)off, (uint16_t)(internal_hs_reg((uint16_t)off) & v16)); /* W0C. */
      return;
    case (uint16_t)k_ra8_usb_off_pipecfg:
      s_hs.pipe_ep[internal_hs_pipesel()] = (uint8_t)(v16 & (uint16_t)k_usbhs_epnum_mask);
      internal_hs_set((uint16_t)off, v16);
      return;
    case (uint16_t)k_ra8_usb_off_pipemaxp:
      s_hs.pipe_maxp[internal_hs_pipesel()] = v16;
      return;
    default:
      break;
  }
  if (internal_hs_is_pipectr(off)) {
    s_hs.pipe_pid[internal_hs_pipectr_index(off)] = v16;
    return;
  }
  internal_hs_set((uint16_t)off, v16);
}
 
/* =============================================================================
 * Role-routed public entry points (see the role-routing section of board_usb.h).
 * =============================================================================
 */
 
uint64_t board_usbhs_host_reg_read(uc_engine* uc, uint64_t off, unsigned size)
{
  return internal_hs_read(uc, off, size);
}
 
void board_usbhs_host_reg_write(uc_engine* uc, uint64_t off, unsigned size, uint64_t value)
{
  internal_hs_write(uc, off, size, value);
}
 
uint32_t board_usbhs_host_shadow_handoff(uint16_t* dst_words, uint32_t word_capacity)
{
  if (dst_words == nullptr) {
    return 0U;
  }
  uint32_t n = (uint32_t)k_usbhs_words;
  if (n > word_capacity) {
    n = word_capacity;
  }
  (void)memcpy(dst_words, s_hs.reg, (size_t)n * sizeof(uint16_t));
  /* The embedded-PHY page past the device-model span (LPSTS.SUSPENDM at 0x102)
   * is per-WINDOW state, not per-role: it stays with this physical controller
   * so the device firmware's PHY configuration survives the rebinding. */
  uint16_t phy_page[k_usbhs_words] = {};
  (void)memcpy(&phy_page[(uint32_t)k_usbhs_dev_span / 2U],
               &s_hs.reg[(uint32_t)k_usbhs_dev_span / 2U],
               ((size_t)k_usbhs_words - ((size_t)k_usbhs_dev_span / 2U)) * sizeof(uint16_t));
  s_hs = (usbhs_state_t){}; /* fresh start behind the USBFS window (Config B). */
  (void)memcpy(s_hs.reg, phy_page, sizeof(phy_page));
  return n;
}
 
/* =============================================================================
 * Block entry points, reset, report, self-registration.
 * =============================================================================
 */

RA8_INTERNAL static uint64_t internal_usbhs_block_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  const uint64_t off = addr - (uint64_t)k_usbhs_base;
  if ((uint16_t)off == (uint16_t)k_ra8_usbhs_off_pllsta) {
    return (uint64_t)
      k_usbhs_plllock; /* HUM Ch 37.2.4 "PLLSTA : PLL Status Register" p 2065 -- role-agnostic. */
  }
  if (board_usb_roles_swapped()) {
    if (off >= (uint64_t)k_usbhs_dev_span) {
      return (uint64_t)internal_hs_reg((uint16_t)off); /* PHY page (LPSTS): local shadow. */
    }
    return board_usb_dev_reg_read(uc, off, size);
  }
  return internal_hs_read(uc, off, size);
}

RA8_INTERNAL static void
internal_usbhs_block_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  const uint64_t off = addr - (uint64_t)k_usbhs_base;
  /* Role declaration (HUM Ch 37.2.1 SYSCFG.DPRPU, p 2060): only the device
   * role pulls D+ up. A DPRPU=1 write to THIS instance pins it to the device
   * model -- the FS controller must then be the loop's host (Config B). */
  if (!board_usb_roles_swapped() && ((uint16_t)off == (uint16_t)k_ra8_usb_off_syscfg) &&
      (((uint16_t)value & (uint16_t)(1U << k_ra8_syscfg_bit_dprpu)) != 0U)) {
    board_usb_roles_swap(uc);
  }
  if (board_usb_roles_swapped()) {
    if (off >= (uint64_t)k_usbhs_dev_span) {
      internal_hs_set((uint16_t)off, (uint16_t)value); /* PHY page (LPSTS): local shadow. */
      return;
    }
    board_usb_dev_reg_write(uc, off, size, value);
    return;
  }
  internal_hs_write(uc, off, size, value);
}

RA8_INTERNAL static void internal_usbhs_reset(void)
{
  s_hs = (usbhs_state_t){};
}

RA8_INTERNAL static void internal_usbhs_report(void)
{
  if (s_hs.setups == 0U) {
    return; /* the loop's host side never came up this run; stay silent. */
  }
  (void)priv_emu_io_errf(
    "  %s host   : %u SETUP(s), %u bulk-OUT, %u bulk-IN (chip-internal loop)\n",
    board_usb_roles_swapped() ? "USB-FS" : "USB-HS",
    s_hs.setups,
    s_hs.bulk_out,
    s_hs.bulk_in);
}

static const board_periph_block_t s_k_usbhs_block = {
  .base      = (uint64_t)k_usbhs_base,
  .span      = (uint64_t)k_usbhs_span,
  .order     = (uint32_t)k_usbhs_report_ord,
  .read      = internal_usbhs_block_read,
  .write     = internal_usbhs_block_write,
  .tick      = nullptr,
  .reset     = internal_usbhs_reset,
  .report    = internal_usbhs_report,
  .name      = "USBHS-host",
  .observe   = false,
  .device    = k_board_block_dev_any,
  .loop_only = true,
};

[[gnu::constructor]] RA8_INTERNAL static void internal_usbhs_block_register(void)
{
  board_periph_register_block(&s_k_usbhs_block);
}