SRAM controller ECC self-test / error-status model (SRAMCRn / SRAMESR). More...

#include <stdint.h>
#include <stdio.h>
#include "board_periph_block.h"
#include "emu_host_io_internal.h"

Include dependency graph for board_periph_sram.c:

Data Structures
struct	sram_state_t
	SRAM-controller model state (cleared each run / reboot). More...

Enumerations
enum	sram_geom_t : uint64_t { k_sram_base = 0x40002000ULL , k_sram_span = 0x100ULL , k_sram_off_cr0 = 0x10ULL , k_sram_off_cr3 = 0x1CULL , k_sram_off_esr = 0x40ULL , k_sram_off_esclr = 0x48ULL , k_sram_off_ear0 = 0x50ULL }
	SRAM-controller window geometry + register offsets (ra8_sram_regs.h). More...
enum	sram_model_t : uint32_t { k_sram_cr_bypass = 0x80U , k_sram_cr_verify = 0x1CU , k_sram_cr_mask = 0xFFU , k_sram_bank_count = 4U , k_sram_slots_bank = 2U , k_sram_ear_bank_str = 8U , k_sram_ear_slot_str = 4U , k_sram_byte_bits = 8U }
	Self-test phase CR values + ESR/bank layout (no magic numbers). More...
enum	sram_order_t : uint32_t { k_sram_block_order = 176U }
	Per-tick order slot for the SRAM-ECC block (relative order). More...

Functions
static RA8_INTERNAL uint16_t	internal_sram_esr_bit (uint32_t bank, uint32_t slot)
	ESR bit for (bank, slot): slot 0 = 1-bit error, slot 1 = 2-bit.
static RA8_INTERNAL void	internal_sram_shadow_store (uint64_t off, unsigned size, uint64_t value)
	Write `value` (size bytes) into the read-back shadow at `off`.
static RA8_INTERNAL uint64_t	internal_sram_shadow_load (uint64_t off, unsigned size)
	Read `size` bytes from the read-back shadow at `off`.
static RA8_INTERNAL void	internal_sram_latch_bank (uint32_t bank)
	Latch both ESR slots + EAR for `bank` (self-test verify reached).
static RA8_INTERNAL void	internal_sram_cr_write (uint32_t bank, uint8_t cr)
	Detect the self-test bypass->verify CR transition for `bank`.
static RA8_INTERNAL void	internal_sram_clear (uint16_t mask)
	Clear the ESR / EAR slots named by an SRAMESCLR write mask.
static RA8_INTERNAL uint64_t	internal_sram_read (uc_engine *uc, uint64_t addr, unsigned size)
	MMIO read inside the SRAM-control window (width-aware).
static RA8_INTERNAL void	internal_sram_write (uc_engine *uc, uint64_t addr, unsigned size, uint64_t value)
	MMIO write inside the SRAM-control window (width-aware).
static RA8_INTERNAL void	internal_sram_reset (void)
	Clear all SRAM-controller model state on reset / process start.
static RA8_INTERNAL void	internal_sram_report (void)
	End-of-run SRAM-ECC section: self-test latches observed this run.
static RA8_INTERNAL void	internal_sram_block_register (void)
	Register the SRAM-controller block before main (host constructor).

Variables
static const uint32_t	s_k_sram_bank_data_off [k_sram_bank_count]
	Per-bank data-window offsets, for a plausible EAR fault address.
static sram_state_t	s_sram
static const board_periph_block_t	s_k_sram_block
	SRAM-controller block descriptor (self-registered with the core).

Detailed Description

SRAM controller ECC self-test / error-status model (SRAMCRn / SRAMESR).

Models the RA8D2 SRAM controller window (ra8_sram_regs.h, ra8_sram.c) at 0x40002000 so mem_ecc_fault_demo (issue #130) can prove the ECC error-detection path headlessly. The sparse MMIO fallback shadows these registers as plain read-back memory, which is enough for ecc_monitor_demo (it only reads a clean SRAMESR) but NOT for a fault-injection demo: a real decoder self-test latches SRAMESR when the corrupted syndrome is read back, and nothing in the fallback does that.

This block claims the control window and models the HUM Ch 58.3.4 ECC decoder self-test (ra8_sram_self_test). That routine drives each bank's SRAMCRn through write (0x08) -> bypass (0x80) -> verify (0x1C); the bank's data line is corrupted while in bypass mode and the verify read latches the error. ra8_emulator cannot observe the syndrome data write (on-chip SRAM is host-backed RAM, not an MMIO hook), so it cannot tell a 1-bit fault from a 2-bit one – it latches BOTH SRAMESR slots for the bank on the bypass->verify transition. That is enough for ra8_sram_self_test to report out_caught for either injection (it checks its own slot), proving the detection + reporting + clear plumbing. The precise per-slot fidelity (and 1-bit correction vs the 2-bit NMI) is silicon-only; the demo stays in hw_pending. All other registers (SRAMPRCR / SRAMWTSC / SRAMCRn / SRAMECCRGNn / SRAMEARnm) read back exactly as written, and SRAMESCLR writes clear the matching SRAMESR / SRAMEAR slots.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file board_periph_sram.c.

Enumeration Type Documentation

◆ sram_geom_t

enum sram_geom_t : uint64_t

SRAM-controller window geometry + register offsets (ra8_sram_regs.h).

Enumerator
k_sram_base	Secure SRAM-control window base.
k_sram_span	Covers SRAMPRCR..SRAMEARnm.
k_sram_off_cr0	SRAMCR0 (CRn at 0x10 + 4*bank), 8-bit.
k_sram_off_cr3	SRAMCR3 – last per-bank control byte.
k_sram_off_esr	SRAMESR error status, 16-bit.
k_sram_off_esclr	SRAMESCLR error-status clear, 16-bit.
k_sram_off_ear0	SRAMEAR[0][0]; [bank][slot] at +8b/+4s.

Definition at line 44 of file board_periph_sram.c.

◆ sram_model_t

enum sram_model_t : uint32_t

Self-test phase CR values + ESR/bank layout (no magic numbers).

Enumerator
k_sram_cr_bypass	Self-test bypass phase (TSTBYP=1).
k_sram_cr_verify	Self-test verify phase (ECC+check).
k_sram_cr_mask	SRAMCRn is one byte wide.
k_sram_bank_count	SRAM0..SRAM3.
k_sram_slots_bank	ESR slots per bank: 0=1-bit, 1=2-bit.
k_sram_ear_bank_str	EAR stride per bank (2 slots * 4 bytes).
k_sram_ear_slot_str	EAR stride per slot (32-bit register).
k_sram_byte_bits	Bits per byte for width-aware assembly.

Definition at line 58 of file board_periph_sram.c.

◆ sram_order_t

enum sram_order_t : uint32_t

Per-tick order slot for the SRAM-ECC block (relative order).

Enumerator
k_sram_block_order	After the VBATT-backup block; report order.

Definition at line 305 of file board_periph_sram.c.

Function Documentation

◆ internal_sram_block_register()

RA8_INTERNAL void internal_sram_block_register ( void )

static

Register the SRAM-controller block before main (host constructor).

Definition at line 323 of file board_periph_sram.c.

References board_periph_register_block(), RA8_INTERNAL, and s_k_sram_block.

◆ internal_sram_clear()

RA8_INTERNAL void internal_sram_clear ( uint16_t mask )

static

Clear the ESR / EAR slots named by an SRAMESCLR write mask.

Clear the esr / ear slots named by an sramesclr write mask; this step is contained within the board periph sram model and uses bounded caller or module-owned storage.

Parameters

[in] mask Mask input used by the operation.

Precondition: Arguments satisfy the ranges documented for sram clear.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph sram model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 202 of file board_periph_sram.c.

References internal_sram_esr_bit(), internal_sram_shadow_store(), k_sram_bank_count, k_sram_ear_bank_str, k_sram_ear_slot_str, k_sram_off_ear0, k_sram_slots_bank, RA8_INTERNAL, and s_sram.

Referenced by internal_sram_write().

◆ internal_sram_cr_write()

RA8_INTERNAL void internal_sram_cr_write	(	uint32_t	bank,
		uint8_t	cr )

static

Detect the self-test bypass->verify CR transition for bank.

Detect the self-test bypass->verify cr transition for bank; this step is contained within the board periph sram model and uses bounded caller or module-owned storage.

Parameters

[in]	bank	Memory or peripheral bank selected by the operation.
[in]	cr	Cr input used by the operation.

Precondition: Arguments satisfy the ranges documented for sram cr write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph sram model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 181 of file board_periph_sram.c.

References internal_sram_latch_bank(), k_sram_cr_bypass, k_sram_cr_verify, RA8_INTERNAL, and s_sram.

Referenced by internal_sram_write().

◆ internal_sram_esr_bit()

RA8_INTERNAL uint16_t internal_sram_esr_bit	(	uint32_t	bank,
		uint32_t	slot )

static

ESR bit for (bank, slot): slot 0 = 1-bit error, slot 1 = 2-bit.

Esr bit for (bank, slot): slot 0 = 1-bit error, slot 1 = 2-bit; this step is contained within the board periph sram model and uses bounded caller or module-owned storage.

Parameters

[in]	bank	Memory or peripheral bank selected by the operation.
[in]	slot	Slot input used by the operation.

Returns: The sram esr bit result produced by the board periph sram model.

Return values

value The operation-specific sram esr bit value.

Precondition: Arguments satisfy the ranges documented for sram esr bit.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph sram model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 99 of file board_periph_sram.c.

References k_sram_slots_bank, and RA8_INTERNAL.

Referenced by internal_sram_clear(), and internal_sram_latch_bank().

◆ internal_sram_latch_bank()

RA8_INTERNAL void internal_sram_latch_bank ( uint32_t bank )

static

Latch both ESR slots + EAR for bank (self-test verify reached).

Latch both esr slots + ear for bank (self-test verify reached); this step is contained within the board periph sram model and uses bounded caller or module-owned storage.

Parameters

[in] bank Memory or peripheral bank selected by the operation.

Precondition: Arguments satisfy the ranges documented for sram latch bank.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph sram model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 159 of file board_periph_sram.c.

References internal_sram_esr_bit(), internal_sram_shadow_store(), k_sram_ear_bank_str, k_sram_ear_slot_str, k_sram_off_ear0, RA8_INTERNAL, s_k_sram_bank_data_off, and s_sram.

Referenced by internal_sram_cr_write().

◆ internal_sram_read()

RA8_INTERNAL uint64_t internal_sram_read	(	uc_engine *	uc,
		uint64_t	addr,
		unsigned	size )

static

MMIO read inside the SRAM-control window (width-aware).

MMIO read inside the sram-control window (width-aware); this step is contained within the board periph sram model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in]	size	Size of the requested region or access in bytes.

Returns: The sram read result produced by the board periph sram model.

Return values

value The operation-specific sram read value.

Precondition: Arguments satisfy the ranges documented for sram read.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph sram model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 229 of file board_periph_sram.c.

References internal_sram_shadow_load(), k_sram_base, k_sram_off_esr, RA8_INTERNAL, and s_sram.

◆ internal_sram_report()

RA8_INTERNAL void internal_sram_report ( void )

static

End-of-run SRAM-ECC section: self-test latches observed this run.

End-of-run sram-ecc section: self-test latches observed this run; this step is contained within the board periph sram model and uses bounded caller or module-owned storage.

Precondition: Arguments satisfy the ranges documented for sram report.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph sram model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 295 of file board_periph_sram.c.

References priv_emu_io_errf(), RA8_INTERNAL, and s_sram.

◆ internal_sram_reset()

RA8_INTERNAL void internal_sram_reset ( void )

static

Clear all SRAM-controller model state on reset / process start.

Clear all sram-controller model state on reset / process start; this step is contained within the board periph sram model and uses bounded caller or module-owned storage.

Precondition: Arguments satisfy the ranges documented for sram reset.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph sram model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 282 of file board_periph_sram.c.

References RA8_INTERNAL, and s_sram.

◆ internal_sram_shadow_load()

RA8_INTERNAL uint64_t internal_sram_shadow_load	(	uint64_t	off,
		unsigned	size )

static

Read size bytes from the read-back shadow at off.

Read size bytes from the read-back shadow at off; this step is contained within the board periph sram model and uses bounded caller or module-owned storage.

Parameters

[in]	off	Register or byte offset addressed by the operation.
[in]	size	Size of the requested region or access in bytes.

Returns: The sram shadow load result produced by the board periph sram model.

Return values

value The operation-specific sram shadow load value.

Precondition: Arguments satisfy the ranges documented for sram shadow load.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph sram model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 138 of file board_periph_sram.c.

References k_sram_byte_bits, k_sram_span, RA8_INTERNAL, and s_sram.

Referenced by internal_sram_read().

◆ internal_sram_shadow_store()

RA8_INTERNAL void internal_sram_shadow_store	(	uint64_t	off,
		unsigned	size,
		uint64_t	value )

static

Write value (size bytes) into the read-back shadow at off.

Write value (size bytes) into the read-back shadow at off; this step is contained within the board periph sram model and uses bounded caller or module-owned storage.

Parameters

[in]	off	Register or byte offset addressed by the operation.
[in]	size	Size of the requested region or access in bytes.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for sram shadow store.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph sram model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 116 of file board_periph_sram.c.

References k_sram_byte_bits, k_sram_span, RA8_INTERNAL, and s_sram.

Referenced by internal_sram_clear(), internal_sram_latch_bank(), and internal_sram_write().

◆ internal_sram_write()

RA8_INTERNAL void internal_sram_write	(	uc_engine *	uc,
		uint64_t	addr,
		unsigned	size,
		uint64_t	value )

static

MMIO write inside the SRAM-control window (width-aware).

MMIO write inside the sram-control window (width-aware); this step is contained within the board periph sram model and uses bounded caller or module-owned storage.

Parameters

[in,out]	uc	Unicorn engine whose emulated state is read or updated.
[in]	addr	Guest address involved in the operation.
[in]	size	Size of the requested region or access in bytes.
[in]	value	Register or payload value involved in the operation.

Precondition: Arguments satisfy the ranges documented for sram write.; The call executes on the emulator's single owning thread.

Postcondition: State changes remain confined to the board periph sram model and documented output objects.; Ownership of caller-supplied storage is unchanged.

Note: The operation is synchronous and does not transfer heap ownership.

Since: 0.1.0

Definition at line 252 of file board_periph_sram.c.

References internal_sram_clear(), internal_sram_cr_write(), internal_sram_shadow_store(), k_sram_base, k_sram_cr_mask, k_sram_off_cr0, k_sram_off_cr3, k_sram_off_esclr, k_sram_off_esr, and s_sram.

Variable Documentation

◆ s_k_sram_bank_data_off

const uint32_t s_k_sram_bank_data_off[k_sram_bank_count]

static

Initial value:

                                             = {
  0x00000000U, 
  0x00080000U, 
  0x00100000U, 
  0x00180000U, 
}

Per-bank data-window offsets, for a plausible EAR fault address.

Definition at line 70 of file board_periph_sram.c.

Referenced by internal_sram_latch_bank().

◆ s_k_sram_block

const board_periph_block_t s_k_sram_block

static

Initial value:

                                                 = {
  .base   = (uint64_t)k_sram_base,
  .span   = (uint64_t)k_sram_span,
  .order  = (uint32_t)k_sram_block_order,
  .read   = internal_sram_read,
  .write  = internal_sram_write,
  .tick   = nullptr,
  .reset  = internal_sram_reset,
  .report = internal_sram_report,
  .name   = "SRAM-ECC",
}

SRAM-controller block descriptor (self-registered with the core).

Definition at line 310 of file board_periph_sram.c.

Referenced by internal_sram_block_register().

◆ s_sram

sram_state_t s_sram

static

Definition at line 85 of file board_periph_sram.c.

Referenced by internal_sram_clear(), internal_sram_cr_write(), internal_sram_latch_bank(), internal_sram_read(), internal_sram_report(), internal_sram_reset(), internal_sram_shadow_load(), internal_sram_shadow_store(), and internal_sram_write().

Data Structures

Enumerations

Functions

Variables

Detailed Description

Enumeration Type Documentation

◆ sram_geom_t

◆ sram_model_t

◆ sram_order_t

Function Documentation

◆ internal_sram_block_register()

◆ internal_sram_clear()

◆ internal_sram_cr_write()

◆ internal_sram_esr_bit()

◆ internal_sram_latch_bank()

◆ internal_sram_read()

◆ internal_sram_report()

◆ internal_sram_reset()

◆ internal_sram_shadow_load()

◆ internal_sram_shadow_store()

◆ internal_sram_write()

Variable Documentation

◆ s_k_sram_bank_data_off

◆ s_k_sram_block

◆ s_sram