Injected SPI-bus seam consumed by Ring-3 SPI device drivers. More...

#include <stdint.h>
#include "ra8_err.h"

Include dependency graph for ra8_spi_bus_ops.h:

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Data Structures
struct	ra8_spi_bus_ops_t
	Caller-filled SPI transfer seam: one full-duplex byte exchange. More...

Detailed Description

Injected SPI-bus seam consumed by Ring-3 SPI device drivers.

Tag: [Ring 3 / HAL] {World: NS}

The RA8D2 implements SPI twice: the dedicated SPI_B block (ra8_spi.h) and SCI in Simple-SPI mode (ra8_sci_spi.h). A device driver at [Ring 3 / HAL] (e.g. the IT8951 e-paper driver in ra8_epaper.h) must not care which physical peripheral its bus pins route to – pin routing differs per board revision – so it takes this small function-pointer seam in its config instead of naming ra8_spi_* or ra8_sci_spi_* directly.

This seam deliberately lives at Ring 3, NOT in the ra8_io fabric: the peripheral-agnostic bus facade ra8_io_spi_bus.h sits at [Ring 4 / PAL], and a Ring-3 driver depending on it would invert ring ordering (see docs/RING_AND_WORLD.md and the identical ra8_vsource / ra8_io_blockdev split). The sanctioned bridge is the Ring-4 adapter ra8_io_spi_bus_as_ops(), which fills this struct with trampolines into a bound ra8_io_spi_bus_t; the app owns the bus, binds a backend, and hands the filled seam to the device driver's _init()/_open() cfg.

The seam is transfer-only by design: bus bring-up (peripheral init, CPOL/CPHA mode, bit-rate) is the app's responsibility, because only the app knows which peripheral the board wires to the device.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file ra8_spi_bus_ops.h.

Data Structures

Detailed Description