ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_poeg_regs.h File Reference

Port Output Enable for GPT (POEG) register layout for the RA8D2. More...

#include <stdint.h>
#include "ra8_attributes.h"
Include dependency graph for ra8_poeg_regs.h:
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Go to the source code of this file.

Data Structures

struct  r_poeg_regs_t

Enumerations

enum  ra8_poeg_addr_t : uintptr_t {
  k_ra8_poeg0_base_addr = 0x40212000UL ,
  k_ra8_poeg1_base_addr = 0x40212100UL ,
  k_ra8_poeg2_base_addr = 0x40212200UL ,
  k_ra8_poeg3_base_addr = 0x40212300UL
}
enum  ra8_poeg_limits_t : uint16_t {
  k_ra8_poeg_group_count = 4U ,
  k_ra8_poeg_group_stride = 0x100U
}

Functions

static volatile r_poeg_regs_tra8_poeg (uint8_t group)
 Get pointer to POEG group N (0..3).

Detailed Description

Port Output Enable for GPT (POEG) register layout for the RA8D2.

Four POEG groups (POEG0..POEG3) at 0x40212000 with 0x100 stride. Each group monitors one external emergency-stop input and, on trigger, forces the associated GPT outputs into a safe (high-impedance) state without CPU involvement. Essential for safety-critical motor control so an over-current fault can halt the H-bridges in a single cycle.

Definition in file ra8_poeg_regs.h.

Enumeration Type Documentation

◆ ra8_poeg_addr_t

enum ra8_poeg_addr_t : uintptr_t
Enumerator
k_ra8_poeg0_base_addr 

RA8 poeg0 base address.

k_ra8_poeg1_base_addr 

RA8 poeg1 base address.

k_ra8_poeg2_base_addr 

RA8 poeg2 base address.

k_ra8_poeg3_base_addr 

RA8 poeg3 base address.

Definition at line 28 of file ra8_poeg_regs.h.

◆ ra8_poeg_limits_t

enum ra8_poeg_limits_t : uint16_t
Enumerator
k_ra8_poeg_group_count 

RA8 poeg group count.

k_ra8_poeg_group_stride 

RA8 poeg group stride.

Definition at line 35 of file ra8_poeg_regs.h.

Function Documentation

◆ ra8_poeg()

volatile r_poeg_regs_t * ra8_poeg ( uint8_t group)
inlinestatic