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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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Port Output Enable for GPT (POEG) register layout for the RA8D2. More...
Go to the source code of this file.
Data Structures | |
| struct | r_poeg_regs_t |
Enumerations | |
| enum | ra8_poeg_addr_t : uintptr_t { k_ra8_poeg0_base_addr = 0x40212000UL , k_ra8_poeg1_base_addr = 0x40212100UL , k_ra8_poeg2_base_addr = 0x40212200UL , k_ra8_poeg3_base_addr = 0x40212300UL } |
| enum | ra8_poeg_limits_t : uint16_t { k_ra8_poeg_group_count = 4U , k_ra8_poeg_group_stride = 0x100U } |
Functions | |
| static volatile r_poeg_regs_t * | ra8_poeg (uint8_t group) |
| Get pointer to POEG group N (0..3). | |
Port Output Enable for GPT (POEG) register layout for the RA8D2.
Four POEG groups (POEG0..POEG3) at 0x40212000 with 0x100 stride. Each group monitors one external emergency-stop input and, on trigger, forces the associated GPT outputs into a safe (high-impedance) state without CPU involvement. Essential for safety-critical motor control so an over-current fault can halt the H-bridges in a single cycle.
Definition in file ra8_poeg_regs.h.
| enum ra8_poeg_addr_t : uintptr_t |
| Enumerator | |
|---|---|
| k_ra8_poeg0_base_addr | RA8 poeg0 base address. |
| k_ra8_poeg1_base_addr | RA8 poeg1 base address. |
| k_ra8_poeg2_base_addr | RA8 poeg2 base address. |
| k_ra8_poeg3_base_addr | RA8 poeg3 base address. |
Definition at line 28 of file ra8_poeg_regs.h.
| enum ra8_poeg_limits_t : uint16_t |
| Enumerator | |
|---|---|
| k_ra8_poeg_group_count | RA8 poeg group count. |
| k_ra8_poeg_group_stride | RA8 poeg group stride. |
Definition at line 35 of file ra8_poeg_regs.h.
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inlinestatic |
Get pointer to POEG group N (0..3).
Definition at line 46 of file ra8_poeg_regs.h.
References k_ra8_poeg0_base_addr, k_ra8_poeg_group_count, and k_ra8_poeg_group_stride.
Referenced by ra8_poeg_clear_status(), ra8_poeg_deinit(), ra8_poeg_dispatch(), ra8_poeg_get_status(), ra8_poeg_init(), and ra8_poeg_trigger_stop().