36typedef enum : uint8_t {
173typedef enum : uint8_t {
Error Code Definitions for ra8-firmware.
MIPI CSI-2 Receiver register layout for the RA8D2 (HUM Ch 66).
ra8_mipi_csi_vlsien_t
Encodings for EMCT.VLSIEN[5:4] (HUM Ch 66.3.8 p 3941).
void(* ra8_mipi_csi_dl_event_fn_t)(void *ctx, uint8_t lane, uint32_t dlst)
Data-lane IRQ callback.
void(* ra8_mipi_csi_event_fn_t)(void *ctx, uint32_t rxst_mask)
MIPI CSI receive-status event callback.
void(* ra8_mipi_csi_pm_event_fn_t)(void *ctx, uint32_t pmst)
Power-management IRQ callback.
ra8_mipi_csi_lanes_t
Number of D-PHY data lanes the receiver should bring up.
@ k_ra8_mipi_csi_lanes_2
Dual-lane D-PHY operation.
@ k_ra8_mipi_csi_lanes_1
Single-lane D-PHY operation.
void(* ra8_mipi_csi_short_event_fn_t)(void *ctx, uint32_t gsst)
Generic-short-packet FIFO IRQ callback.
ra8_mipi_csi_data_format_t
Per-virtual-channel payload format used by ra8_mipi_csi_set_data_format.
@ k_ra8_mipi_csi_format_off
Disable – accept nothing for VC.
@ k_ra8_mipi_csi_format_yuv422_10
CSI-2 DT 0x1F – YUV 4:2:2 10-bit.
@ k_ra8_mipi_csi_format_rgb888
CSI-2 DT 0x24 – RGB888.
@ k_ra8_mipi_csi_format_yuv420
CSI-2 DT 0x18 – YUV 4:2:0 8-bit.
@ k_ra8_mipi_csi_format_raw8
CSI-2 DT 0x2A – RAW8.
@ k_ra8_mipi_csi_format_yuv422_8
CSI-2 DT 0x1E – YUV 4:2:2 8-bit.
@ k_ra8_mipi_csi_format_raw10
CSI-2 DT 0x2B – RAW10 (FSP-only).
void(* ra8_mipi_csi_error_fn_t)(void *ctx, const ra8_mipi_csi_error_report_t *report)
Callback invoked when the receiver reports an ECC or CRC error.
void(* ra8_mipi_csi_vc_event_fn_t)(void *ctx, uint8_t vc, uint32_t vcst)
Per-virtual-channel IRQ callback.
Configuration descriptor for ra8_mipi_csi_init.
uint16_t frrskw
MCT2.FRRSKW[8:0] skew.
bool zlmd
MCT0.ZLMD – zero-length LP.
bool eccv13
MCT0.ECCV13 – ECC v1.3 mode.
bool lfsren
MCT0.LFSREN – descrambling on.
bool edmd
MCT0.EDMD – ErrFrameData notify.
ra8_mipi_csi_vlsien_t vlsien
EMCT.VLSIEN[5:4] LRTE spacer.
uint32_t vc_irq_mask[16]
VCIE0..VCIE15 values.
uint8_t short_threshold
GSCT.SHTH (threshold-1 in stages).
bool epd_option_2
EPCT.EPDOP – 1 = Option 2 (recommended).
ra8_mipi_csi_lanes_t lanes
1 or 2 lanes (MCT0.VDLN).
uint16_t epd_short_spacer
EPCT.SSP[14:0].
uint32_t pm_irq_mask
PMIE value.
uint16_t frrclk
MCT2.FRRCLK[8:0] rate.
bool rvmd
MCT0.RVMD – reserved-DT receive.
bool epd_enable
EPCT.EPDEN – enable EPD.
uint32_t dl_irq_mask[2]
DLIE0 / DLIE1 values.
bool generic_rule
MCT0.GRMD: must be 1 here.
bool short_store_enable
GSCT.GFIF – 1 = store in FIFO.
uint32_t dt_high_mask
DTEH value to programme.
uint16_t epd_long_spacer
EPCT.SLP[14:0].
uint32_t short_irq_mask
GSIE value.
uint32_t dt_low_mask
DTEL value to programme.
bool eotp_enable
EMCT.EOTPEN bit 6.
uint32_t rx_irq_mask
RXIE value.
One ECC / CRC error notification from the receiver.
bool ecc_two_bit_error
VCST.ECD – 2-bit ECC error.
bool crc_error
VCST.CRC – payload CRC mismatch.
bool ecc_corrected
VCST.ECC – 1-bit ECC corrected.
uint32_t raw_vcst
Original VCST snapshot (bits as decoded).
uint8_t vc
Virtual channel that reported, or 0xFF.
Decoded MCG (Module Configuration) RO snapshot.
uint32_t raw
Unprocessed register snapshot.
uint8_t lanes_max
MCG.SDLN[11:8] – max supported lanes.
uint8_t version
MCG.VER[3:0] – IP-core version.
uint8_t fifo_stages
MCG.GSNM[23:16] – short-packet FIFO depth.
One drained generic short-packet header.
uint16_t payload
GSHT.SPDT[15:0] – 16-bit user data.
uint32_t raw
Unprocessed register snapshot.
uint8_t data_type
GSHT.DTYP[21:16] – short-packet DT (0x08-0x0F).
uint8_t vc
GSHT.SPVC[27:24] – virtual channel.