ra8_lvd.c

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#include "ra8_lvd.h"
 
#include <stdint.h>
 
#include "ra8_attributes.h"
#include "ra8_check.h"
#include "ra8_err.h"
#include "ra8_lvd_internal.h"
#include "ra8_lvd_regs.h"

bool priv_ra8_lvd_internal_reject_hvd_after(uint32_t hvd_val,
                                            uint32_t after_assert_val,
                                            uint32_t hysteresis,
                                            uint32_t negate)
{
  return (hysteresis == hvd_val) && (negate == after_assert_val);
}

bool priv_ra8_lvd_internal_set_ri_bit(uint32_t reset_val,
                                      uint32_t reset_on_rise_val,
                                      uint32_t response)
{
  return (response == reset_val) || (response == reset_on_rise_val);
}
#include "ra8_log.h"

static const char* s_tag = "LVD";
 
/* =============================================================================
 * Channel-map helpers
 * =============================================================================
 */

const ra8_lvd_channel_map_t g_lvd_map[k_ra8_lvd_map_idx_count] = {
  {.cmpcr   = k_ra8_lvd_pvd1_cmpcr_off,
   .cr0     = k_ra8_lvd_pvd1_cr0_off,
   .cr1     = k_ra8_lvd_pvd1_cr1_off,
   .sr      = k_ra8_lvd_pvd1_sr_off,
   .fcr     = k_ra8_lvd_pvd1_fcr_off,
   .has_irq = true},
  {.cmpcr   = k_ra8_lvd_pvd2_cmpcr_off,
   .cr0     = k_ra8_lvd_pvd2_cr0_off,
   .cr1     = k_ra8_lvd_pvd2_cr1_off,
   .sr      = k_ra8_lvd_pvd2_sr_off,
   .fcr     = k_ra8_lvd_pvd2_fcr_off,
   .has_irq = true},
  {.cmpcr   = k_ra8_lvd_pvd4_cmpcr_off,
   .cr0     = k_ra8_lvd_pvd4_cr0_off,
   .cr1     = k_ra8_lvd_pvd4_cr0_off, /* unused -- n channels have no CR1. */
   .sr      = k_ra8_lvd_pvd4_cr0_off, /* unused -- n channels have no SR.  */
   .fcr     = k_ra8_lvd_pvd4_fcr_off,
   .has_irq = false},
  {.cmpcr   = k_ra8_lvd_pvd5_cmpcr_off,
   .cr0     = k_ra8_lvd_pvd5_cr0_off,
   .cr1     = k_ra8_lvd_pvd5_cr0_off,
   .sr      = k_ra8_lvd_pvd5_cr0_off,
   .fcr     = k_ra8_lvd_pvd5_fcr_off,
   .has_irq = false},
};
 
/* =============================================================================
 * Internal helpers
 * =============================================================================
 */

ra8_err_t priv_ra8_lvd_internal_channel_to_idx(ra8_lvd_channel_t channel, uint8_t* out_idx)
{
  switch (channel) {
    case k_ra8_lvd_ch1:
      *out_idx = k_ra8_lvd_map_idx_ch1;
      return k_ra8_ok;
    case k_ra8_lvd_ch2:
      *out_idx = k_ra8_lvd_map_idx_ch2;
      return k_ra8_ok;
    case k_ra8_lvd_ch4:
      *out_idx = k_ra8_lvd_map_idx_ch4;
      return k_ra8_ok;
    case k_ra8_lvd_ch5:
      *out_idx = k_ra8_lvd_map_idx_ch5;
      return k_ra8_ok;
    default:
      return k_ra8_err_invalid_arg;
  }
}

RA8_INTERNAL static ra8_err_t internal_validate_threshold(ra8_lvd_pvdlvl_t threshold)
{
  if ((uint8_t)threshold < k_ra8_lvd_pvdlvl_min) {
    return k_ra8_err_invalid_arg;
  }
  if ((uint8_t)threshold > k_ra8_lvd_pvdlvl_max) {
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

ra8_err_t priv_ra8_lvd_internal_validate_div(ra8_lvd_loco_div_t div)
{
  if ((uint8_t)div > k_ra8_lvd_loco_div_max) {
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

RA8_INTERNAL static ra8_err_t internal_validate_edge(ra8_lvd_edge_t edge)
{
  /* HUM Ch 8.2.6 "PVDmCR1 : Voltage Monitor m Circuit Control Register" p 307 */
  if ((uint8_t)edge > k_ra8_lvd_edge_both) {
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

uint8_t priv_ra8_lvd_internal_read_ri(const ra8_lvd_channel_map_t* map)
{
  /* HUM Ch 8.2.4 "PVDmCR0 : Voltage Monitor m Circuit Control Register 0" p 305 */
  return (uint8_t)(*ra8_lvd_reg8(map->cr0) & k_ra8_lvd_cr0_mask_ri);
}

RA8_INTERNAL static uint8_t internal_n_cr0_with_reserved(uint8_t base)
{
  /* HUM Ch 8.2.5 "PVDnCR0 : Voltage Monitor n Circuit Control Register 0" p 306 */
  return (uint8_t)(base | k_ra8_lvd_cr0_mask_n_bit6);
}

RA8_INTERNAL static uint8_t internal_m_cr0_with_reserved(uint8_t base)
{
  /* HUM Ch 8.2.4 "PVDmCR0 : Voltage Monitor m Circuit Control Register 0" p 305 */
  return (uint8_t)(base | k_ra8_lvd_cr0_mask_bit3);
}

RA8_INTERNAL static uint8_t internal_cr0_apply_reserved(const ra8_lvd_channel_map_t* map,
                                                        uint8_t                      base)
{
  if (map->has_irq) {
    return internal_m_cr0_with_reserved(base);
  }
  return internal_n_cr0_with_reserved(base);
}

void priv_ra8_lvd_internal_cr0_rmw(const ra8_lvd_channel_map_t* map,
                                   uint8_t                      clear_mask,
                                   uint8_t                      set_bits)
{
  /* HUM Ch 8.2.4 "PVDmCR0 : Voltage Monitor m Circuit Control Register 0" p 305 */
  /* HUM Ch 8.2.5 "PVDnCR0 : Voltage Monitor n Circuit Control Register 0" p 306 */
  const uint8_t prev      = *ra8_lvd_reg8(map->cr0);
  const uint8_t base      = (uint8_t)((prev & (uint8_t)~clear_mask) | set_bits);
  *ra8_lvd_reg8(map->cr0) = internal_cr0_apply_reserved(map, base);
}
 
/* =============================================================================
 * Channel init / deinit -- follows HUM Table 8.4 / Table 8.6
 * =============================================================================
 */

RA8_INTERNAL static ra8_err_t internal_validate_cfg(const ra8_lvd_channel_map_t* map,
                                                    const ra8_lvd_cfg_t*         cfg)
{
  ra8_err_t err = internal_validate_threshold(cfg->threshold);
  if (err != k_ra8_ok) {
    return err;
  }
  err = priv_ra8_lvd_internal_validate_div(cfg->filter_div);
  if (err != k_ra8_ok) {
    return err;
  }
  if (map->has_irq) {
    err = internal_validate_edge(cfg->edge);
    if (err != k_ra8_ok) {
      return err;
    }
  } else {
    /* HUM Ch 8.2.5 "PVDnCR0 : Voltage Monitor n Circuit Control Register 0" p 306 */
    /* n channels only have RE -- reject IRQ / NMI responses. */
    if ((cfg->response == k_ra8_lvd_response_interrupt) ||
        (cfg->response == k_ra8_lvd_response_nmi)) {
      return k_ra8_err_not_supported;
    }
  }
  /* HUM Ch 8.2.4 "PVDmCR0 : Voltage Monitor m Circuit Control Register 0" p 306 */
  /* RN=1 prohibited when RHSEL=1. */
  if (priv_ra8_lvd_internal_reject_hvd_after((uint32_t)k_ra8_lvd_hysteresis_hvd,
                                             (uint32_t)k_ra8_lvd_negate_after_assert,
                                             (uint32_t)cfg->hysteresis,
                                             (uint32_t)cfg->negate)) {
    return k_ra8_err_invalid_arg;
  }
  return k_ra8_ok;
}

RA8_INTERNAL static uint8_t internal_compose_cr0(const ra8_lvd_channel_map_t* map,
                                                 const ra8_lvd_cfg_t*         cfg)
{
  uint8_t cr0 = (uint8_t)((uint8_t)cfg->filter_div << k_ra8_lvd_cr0_shift_fsamp);
  cr0 &= k_ra8_lvd_cr0_mask_fsamp;
  cr0 |= k_ra8_lvd_cr0_mask_dfdis; /* DFDIS = 1 while writing FSAMP. */
  if (map->has_irq) {
    if (cfg->negate == k_ra8_lvd_negate_after_assert) {
      cr0 |= k_ra8_lvd_cr0_mask_rn;
    }
    if (priv_ra8_lvd_internal_set_ri_bit((uint32_t)k_ra8_lvd_response_reset,
                                         (uint32_t)k_ra8_lvd_response_reset_on_rise,
                                         (uint32_t)cfg->response)) {
      cr0 |= k_ra8_lvd_cr0_mask_ri;
    }
  }
  return cr0;
}

RA8_INTERNAL static void internal_program_cr1(const ra8_lvd_channel_map_t* map,
                                              const ra8_lvd_cfg_t*         cfg)
{
  /* HUM Ch 8.2.6 "PVDmCR1 : Voltage Monitor m Circuit Control Register" p 307 */
  uint8_t cr1 = (uint8_t)((uint8_t)cfg->edge & k_ra8_lvd_cr1_mask_idtsel);
  if (cfg->irq_type == k_ra8_lvd_irq_maskable) {
    cr1 |= k_ra8_lvd_cr1_mask_irqsel;
  }
  *ra8_lvd_reg8(map->cr1) = cr1;
 
  if (cfg->clear_status) {
    /* HUM Ch 8.2.7 "PVDmSR : Voltage Monitor m Circuit Status Register" p 307 */
    *ra8_lvd_reg8(map->sr) = 0U;
  }
}

RA8_INTERNAL static void internal_lvd_program_cmpcr(const ra8_lvd_channel_map_t* map,
                                                    const ra8_lvd_cfg_t*         cfg)
{
  /* Step 1: disable everything; HUM Ch 8.2.4 / 8.2.2 */
  *ra8_lvd_reg8(map->cr0)   = internal_cr0_apply_reserved(map, 0U);
  *ra8_lvd_reg8(map->cmpcr) = 0U;
 
  /* Step 2: PVDLVL with PVDE = 0 */
  uint8_t cmpcr             = (uint8_t)((uint8_t)cfg->threshold & k_ra8_lvd_cmpcr_mask_pvdlvl);
  *ra8_lvd_reg8(map->cmpcr) = cmpcr;
 
  /* Step 3: HUM Ch 8.2.8 / 8.2.9 -- RHSEL on FCR */
  *ra8_lvd_reg8(map->fcr) = (uint8_t)((uint8_t)cfg->hysteresis & k_ra8_lvd_fcr_mask_rhsel);
 
  /* Step 4: re-assert PVDE */
  cmpcr |= k_ra8_lvd_cmpcr_mask_pvde;
  *ra8_lvd_reg8(map->cmpcr) = cmpcr;
}

RA8_INTERNAL static void internal_lvd_program_cr0_chain(const ra8_lvd_channel_map_t* map,
                                                        const ra8_lvd_cfg_t*         cfg)
{
  uint8_t cr0             = internal_compose_cr0(map, cfg);
  *ra8_lvd_reg8(map->cr0) = internal_cr0_apply_reserved(map, cr0);
 
  if (cfg->filter_en) {
    cr0 &= (uint8_t)~k_ra8_lvd_cr0_mask_dfdis;
    *ra8_lvd_reg8(map->cr0) = internal_cr0_apply_reserved(map, cr0);
  }
 
  if (map->has_irq) {
    internal_program_cr1(map, cfg);
  }
 
  if (cfg->irq_enable && (cfg->response != k_ra8_lvd_response_none)) {
    /* RIE (m-channel: IRQ/reset enable) and RE (n-channel: reset-only)
     * sit at the same CR0 bit position (0x01) on RA8D2; the semantic
     * distinction lives in `map->has_irq`. Either mask gates bit 0. */
    cr0 |= k_ra8_lvd_cr0_mask_rie;
    *ra8_lvd_reg8(map->cr0) = internal_cr0_apply_reserved(map, cr0);
  }
 
  cr0 |= k_ra8_lvd_cr0_mask_cmpe;
  *ra8_lvd_reg8(map->cr0) = internal_cr0_apply_reserved(map, cr0);
}

ra8_err_t ra8_lvd_channel_init(ra8_lvd_channel_t channel, const ra8_lvd_cfg_t* cfg)
{
  RA8_CHECK_NULL_PTR(cfg, s_tag, "cfg must not be nullptr");
 
  uint8_t         idx     = 0U;
  const ra8_err_t map_err = priv_ra8_lvd_internal_channel_to_idx(channel, &idx);
  RA8_RETURN_ON_ERROR(map_err, s_tag, "lvd_init: bad channel");
 
  const ra8_lvd_channel_map_t map     = g_lvd_map[idx];
  const ra8_err_t             cfg_err = internal_validate_cfg(&map, cfg);
  RA8_RETURN_ON_ERROR(cfg_err, s_tag, "lvd_init: bad cfg");
 
  internal_lvd_program_cmpcr(&map, cfg);
  internal_lvd_program_cr0_chain(&map, cfg);
 
  ra8_log_info_val(s_tag, "lvd_init ch", (uint32_t)channel);
  return k_ra8_ok;
}

ra8_err_t ra8_lvd_channel_deinit(ra8_lvd_channel_t channel)
{
  uint8_t         idx     = 0U;
  const ra8_err_t map_err = priv_ra8_lvd_internal_channel_to_idx(channel, &idx);
  RA8_RETURN_ON_ERROR(map_err, s_tag, "lvd_deinit: bad channel");
 
  const ra8_lvd_channel_map_t map = g_lvd_map[idx];
 
  /* === HUM Table 8.5 step 1 / Table 8.7 step 1 -- drop CMPE. */
  priv_ra8_lvd_internal_cr0_rmw(&map, k_ra8_lvd_cr0_mask_cmpe, 0U);
 
  /* === HUM Table 8.5 step 3 / Table 8.7 step 3 -- drop RIE / RE. */
  uint8_t enable_bit = k_ra8_lvd_cr0_mask_re;
  if (map.has_irq) {
    enable_bit = k_ra8_lvd_cr0_mask_rie;
  }
  priv_ra8_lvd_internal_cr0_rmw(&map, enable_bit, 0U);
 
  /* === HUM Table 8.5 step 4 / Table 8.7 step 4 -- DFDIS = 1 (filter off). */
  priv_ra8_lvd_internal_cr0_rmw(&map, 0U, k_ra8_lvd_cr0_mask_dfdis);
 
  /* === HUM Table 8.5 step 5 / Table 8.7 step 5 -- drop PVDE. */
  /* HUM Ch 8.2.2 "PVDmCMPCR" p 303 */
  *ra8_lvd_reg8(map.cmpcr) = 0U;
 
  /* Cleanly drop the rest of the per-channel state. */
  *ra8_lvd_reg8(map.cr0) = internal_cr0_apply_reserved(&map, 0U);
  *ra8_lvd_reg8(map.fcr) = 0U;
  if (map.has_irq) {
    /* HUM Ch 8.2.6 "PVDmCR1 : Voltage Monitor m Circuit Control Register" p 307 */
    *ra8_lvd_reg8(map.cr1) = 0U;
    /* HUM Ch 8.2.7 "PVDmSR : Voltage Monitor m Circuit Status Register" p 307 */
    *ra8_lvd_reg8(map.sr) = 0U;
  }
  return k_ra8_ok;
}
 
/* =============================================================================
 * Threshold + edge + kind setters
 * =============================================================================
 */

ra8_err_t ra8_lvd_set_threshold(ra8_lvd_channel_t channel, ra8_lvd_pvdlvl_t threshold)
{
  uint8_t         idx     = 0U;
  const ra8_err_t map_err = priv_ra8_lvd_internal_channel_to_idx(channel, &idx);
  RA8_RETURN_ON_ERROR(map_err, s_tag, "lvd_set_threshold: bad channel");
 
  const ra8_err_t lvl_err = internal_validate_threshold(threshold);
  RA8_RETURN_ON_ERROR(lvl_err, s_tag, "lvd_set_threshold: bad threshold");
 
  const ra8_lvd_channel_map_t map = g_lvd_map[idx];
 
  /* HUM Ch 8.2.2 "PVDmCMPCR : Voltage Monitor m Comparator Control Register" p 303 */
  /* Preserve the PVDE bit, drop it around the PVDLVL write, restore it afterwards. */
  const uint8_t prev     = *ra8_lvd_reg8(map.cmpcr);
  const uint8_t pvde_was = (uint8_t)(prev & k_ra8_lvd_cmpcr_mask_pvde);
 
  *ra8_lvd_reg8(map.cmpcr) = 0U;
 
  uint8_t cmpcr = (uint8_t)((uint8_t)threshold & k_ra8_lvd_cmpcr_mask_pvdlvl);
  cmpcr |= pvde_was;
  *ra8_lvd_reg8(map.cmpcr) = cmpcr;
  return k_ra8_ok;
}

ra8_err_t ra8_lvd_set_irq_edge(ra8_lvd_channel_t channel, ra8_lvd_edge_t edge)
{
  uint8_t         idx     = 0U;
  const ra8_err_t map_err = priv_ra8_lvd_internal_channel_to_idx(channel, &idx);
  /* GCOVR_EXCL_BR_START -- channel_to_idx() error edge; set_irq_edge pre-validates the channel */
  RA8_RETURN_ON_ERROR(map_err, s_tag, "lvd_set_irq_edge: bad channel");
  /* GCOVR_EXCL_BR_STOP */
 
  const ra8_err_t edge_err = internal_validate_edge(edge);
  RA8_RETURN_ON_ERROR(edge_err, s_tag, "lvd_set_irq_edge: bad edge");
 
  const ra8_lvd_channel_map_t map = g_lvd_map[idx];
  if (!map.has_irq) {
    return k_ra8_err_not_supported;
  }
 
  /* HUM Ch 8.2.6 "PVDmCR1 : Voltage Monitor m Circuit Control Register" p 307 */
  const uint8_t prev     = *ra8_lvd_reg8(map.cr1);
  const uint8_t next     = (uint8_t)((prev & (uint8_t)~k_ra8_lvd_cr1_mask_idtsel) |
                                     ((uint8_t)edge & k_ra8_lvd_cr1_mask_idtsel));
  *ra8_lvd_reg8(map.cr1) = next;
  return k_ra8_ok;
}

ra8_err_t ra8_lvd_set_irq_kind(ra8_lvd_channel_t channel, ra8_lvd_irq_type_t kind)
{
  uint8_t         idx     = 0U;
  const ra8_err_t map_err = priv_ra8_lvd_internal_channel_to_idx(channel, &idx);
  /* GCOVR_EXCL_BR_START -- channel_to_idx() error edge; set_irq_kind pre-validates the channel */
  RA8_RETURN_ON_ERROR(map_err, s_tag, "lvd_set_irq_kind: bad channel");
  /* GCOVR_EXCL_BR_STOP */
 
  const ra8_lvd_channel_map_t map = g_lvd_map[idx];
  if (!map.has_irq) {
    return k_ra8_err_not_supported;
  }
 
  /* HUM Ch 8.2.6 "PVDmCR1 : Voltage Monitor m Circuit Control Register" p 307 */
  const uint8_t prev = *ra8_lvd_reg8(map.cr1);
  uint8_t       next = (uint8_t)(prev & (uint8_t)~k_ra8_lvd_cr1_mask_irqsel);
  if (kind == k_ra8_lvd_irq_maskable) {
    next |= k_ra8_lvd_cr1_mask_irqsel;
  }
  *ra8_lvd_reg8(map.cr1) = next;
  return k_ra8_ok;
}