ra8_lvd_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>

typedef enum : uintptr_t {
  k_ra8_lvd_sysc_base_addr  = 0x4001E000UL, 
  k_ra8_lvd_cpscu_base_addr = 0x40008000UL, 
} ra8_lvd_base_addr_t;

typedef enum : uintptr_t {
  /* PVD1 -- m series. */
  k_ra8_lvd_pvd1_cr1_off   = 0x4001E0E0UL, 
  k_ra8_lvd_pvd1_sr_off    = 0x4001E0E1UL, 
  k_ra8_lvd_pvd1_cmpcr_off = 0x4001EA58UL, 
  k_ra8_lvd_pvd1_cr0_off   = 0x4001EA70UL, 
  k_ra8_lvd_pvd1_fcr_off   = 0x4001EB20UL, 
  /* PVD2 -- m series. */
  k_ra8_lvd_pvd2_cr1_off   = 0x4001E0E2UL, 
  k_ra8_lvd_pvd2_sr_off    = 0x4001E0E3UL, 
  k_ra8_lvd_pvd2_cmpcr_off = 0x4001EA5CUL, 
  k_ra8_lvd_pvd2_cr0_off   = 0x4001EA74UL, 
  k_ra8_lvd_pvd2_fcr_off   = 0x4001EB24UL, 
  /* PVD4 -- n series (no CR1, no SR). */
  k_ra8_lvd_pvd4_cmpcr_off = 0x4001EA64UL, 
  k_ra8_lvd_pvd4_cr0_off   = 0x4001EA7CUL, 
  k_ra8_lvd_pvd4_fcr_off   = 0x4001EB2CUL, 
  /* PVD5 -- n series (no CR1, no SR). */
  k_ra8_lvd_pvd5_cmpcr_off = 0x4001EA68UL, 
  k_ra8_lvd_pvd5_cr0_off   = 0x4001EA80UL, 
  k_ra8_lvd_pvd5_fcr_off   = 0x4001EB30UL, 
  /* Lock + security registers. */
  k_ra8_lvd_pvdlr_off  = 0x4001EB34UL, 
  k_ra8_lvd_pvdsar_off = 0x400083CCUL, 
} ra8_lvd_off_t;

typedef enum : uint8_t {
  k_ra8_lvd_cmpcr_mask_pvdlvl = 0x1FU, 
  k_ra8_lvd_cmpcr_mask_pvde   = 0x80U, 
} ra8_lvd_cmpcr_mask_t;

typedef enum : uint8_t {
  k_ra8_lvd_cr0_mask_rie    = 0x01U, 
  k_ra8_lvd_cr0_mask_re     = 0x01U, 
  k_ra8_lvd_cr0_mask_dfdis  = 0x02U, 
  k_ra8_lvd_cr0_mask_cmpe   = 0x04U, 
  k_ra8_lvd_cr0_mask_bit3   = 0x08U, 
  k_ra8_lvd_cr0_mask_fsamp  = 0x30U, 
  k_ra8_lvd_cr0_mask_ri     = 0x40U, 
  k_ra8_lvd_cr0_mask_n_bit6 = 0x40U, 
  k_ra8_lvd_cr0_mask_rn     = 0x80U, 
} ra8_lvd_cr0_mask_t;

typedef enum : uint8_t {
  k_ra8_lvd_cr0_shift_fsamp = 4U, 
} ra8_lvd_cr0_shift_t;

typedef enum : uint8_t {
  k_ra8_lvd_cr1_mask_idtsel = 0x03U, 
  k_ra8_lvd_cr1_mask_irqsel = 0x04U, 
} ra8_lvd_cr1_mask_t;

typedef enum : uint8_t {
  k_ra8_lvd_sr_mask_det = 0x01U, 
  k_ra8_lvd_sr_mask_mon = 0x02U, 
} ra8_lvd_sr_mask_t;

typedef enum : uint8_t {
  k_ra8_lvd_fcr_mask_rhsel = 0x01U, 
} ra8_lvd_fcr_mask_t;

typedef enum : uint8_t {
  k_ra8_lvd_pvdlr_mask_lock    = 0x01U, 
  k_ra8_lvd_pvdlr_value_unlock = 0x00U, 
  k_ra8_lvd_pvdlr_value_relock = 0x01U, 
} ra8_lvd_pvdlr_t;

typedef enum : uint32_t {
  k_ra8_lvd_pvdsar_mask_nonsec0 = 0x00000001UL, 
  k_ra8_lvd_pvdsar_mask_nonsec1 = 0x00000002UL, 
  k_ra8_lvd_pvdsar_mask_all     = 0x00000003UL, 
} ra8_lvd_pvdsar_mask_t;

typedef enum : uint32_t {
  k_ra8_lvd_filter_factor   = 2U,       
  k_ra8_lvd_filter_extra    = 3U,       
  k_ra8_lvd_us_per_sec      = 1000000U, 
  k_ra8_lvd_loco_hz_default = 32768U,   
} ra8_lvd_filter_const_t;

typedef enum : uint8_t {
  k_ra8_lvd_nmi_channel_count = 2U, 
} ra8_lvd_misc_const_t;

static inline volatile uint8_t* ra8_lvd_reg8(ra8_lvd_off_t off)
{
  return (volatile uint8_t*)(uintptr_t)off;
}

static inline volatile uint32_t* ra8_lvd_reg32(ra8_lvd_off_t off)
{
  return (volatile uint32_t*)(uintptr_t)off;
}
 
#ifdef __cplusplus
}
#endif