ra8_adc_b_regs.h

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#pragma once
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#include "ra8_attributes.h"

typedef enum : uintptr_t {
  k_ra8_adc_b_base_addr = 0x40338000UL, 
} ra8_adc_b_addr_t;

typedef enum : uint8_t {
  k_ra8_adc_b_unit_count     = 2U,    
  k_ra8_adc_b_max_channels   = 24U,   
  k_ra8_adc_b_result_regs    = 23U,   
  k_ra8_adc_b_scan_groups    = 9U,    
  k_ra8_adc_b_cmp_tables     = 8U,    
  k_ra8_adc_b_adchcr_stride  = 0x10U, 
  k_ra8_adc_b_addr_stride    = 0x4U,  
  k_ra8_adc_b_adstr_stride   = 0x4U,  
  k_ra8_adc_b_cmptbr_stride  = 0x4U,  
  k_ra8_adc_b_adsgdcr_stride = 0x4U,  
  k_ra8_adc_b_adexdr_stride  = 0x4U,  
  k_ra8_adc_b_ext_data_regs  = 23U,   
} ra8_adc_b_limits_t;

typedef enum : uint16_t {
  k_ra8_adc_b_off_adclkenr   = 0x0000U, 
  k_ra8_adc_b_off_adclksr    = 0x0004U, 
  k_ra8_adc_b_off_adclkcr    = 0x0008U, 
  k_ra8_adc_b_off_adsycr     = 0x000CU, 
  k_ra8_adc_b_off_aderintcr  = 0x0020U, 
  k_ra8_adc_b_off_admdr      = 0x0040U, 
  k_ra8_adc_b_off_adsger     = 0x0048U, 
  k_ra8_adc_b_off_adintcr    = 0x005CU, 
  k_ra8_adc_b_off_adsgdcr0   = 0x0200U, 
  k_ra8_adc_b_off_adcmpenr   = 0x0400U, 
  k_ra8_adc_b_off_adcmpintcr = 0x0404U, 
  k_ra8_adc_b_off_adcmpmdr0  = 0x0448U, 
  k_ra8_adc_b_off_adcmpmdr1  = 0x044CU, 
  k_ra8_adc_b_off_adcmptbr0  = 0x0458U, 
  k_ra8_adc_b_off_adchcr0    = 0x0600U, 
  k_ra8_adc_b_off_addopcrb0  = 0x0608U, 
  k_ra8_adc_b_off_addopcrc0  = 0x060CU, 
  k_ra8_adc_b_off_adtrgenr   = 0x0C08U, 
  k_ra8_adc_b_off_adsystr    = 0x0C10U, 
  k_ra8_adc_b_off_adstr0     = 0x0C20U, 
  k_ra8_adc_b_off_adstopr    = 0x0C60U, 
  k_ra8_adc_b_off_adsr       = 0x0C80U, 
  k_ra8_adc_b_off_addr0      = 0x2000U, 
  k_ra8_adc_b_off_adexdr0    = 0x2180U, 
} ra8_adc_b_off_t;

typedef enum : uint8_t {
  k_ra8_adclkenr_bit_clken = 0U, 
} ra8_adclkenr_bit_t;

typedef enum : uint32_t {
  k_ra8_adclkenr_mask_clken = 0x00000001UL, 
} ra8_adclkenr_mask_t;

typedef enum : uint32_t {
  k_ra8_adclksr_mask_clksr = 0x00000001UL, 
} ra8_adclksr_mask_t;

typedef enum : uint8_t {
  k_ra8_admdr_bit_admd0 = 0U, 
  k_ra8_admdr_bit_admd1 = 8U, 
} ra8_admdr_bit_t;

typedef enum : uint32_t {
  k_ra8_admdr_mask_admd0 = 0x0000000FUL, 
  k_ra8_admdr_mask_admd1 = 0x00000F00UL, 
} ra8_admdr_mask_t;

typedef enum : uint8_t {
  k_ra8_admdr_mode_disabled   = 0x0U, 
  k_ra8_admdr_mode_one_cycle  = 0x1U, 
  k_ra8_admdr_mode_continuous = 0x2U, 
} ra8_admdr_mode_t;

typedef enum : uint8_t {
  k_ra8_adchcr_bit_sgsel  = 0U,  
  k_ra8_adchcr_bit_cnvcs  = 8U,  
  k_ra8_adchcr_bit_ainmd  = 15U, 
  k_ra8_adchcr_bit_sstsel = 16U, 
} ra8_adchcr_bit_t;

typedef enum : uint32_t {
  k_ra8_adchcr_mask_sgsel  = 0x0000001FUL, 
  k_ra8_adchcr_mask_cnvcs  = 0x00007F00UL, 
  k_ra8_adchcr_mask_ainmd  = 0x00008000UL, 
  k_ra8_adchcr_mask_sstsel = 0x000F0000UL, 
} ra8_adchcr_mask_t;

typedef enum : uint8_t {
  k_ra8_adchcr_ainmd_single_ended = 0U, 
  k_ra8_adchcr_ainmd_differential = 1U, 
} ra8_adchcr_ainmd_t;

typedef enum : uint8_t {
  k_ra8_adc_b_chan_selfdiag_adc0 = 0x60U, 
  k_ra8_adc_b_chan_selfdiag_adc1 = 0x61U, 
  k_ra8_adc_b_chan_temperature   = 0x64U, 
  k_ra8_adc_b_chan_int_ref_volt  = 0x65U, 
  k_ra8_adc_b_chan_vbatt_div6    = 0x66U, 
  k_ra8_adc_b_chan_dac0          = 0x68U, 
  k_ra8_adc_b_chan_dac1          = 0x69U, 
} ra8_adc_b_ext_chan_t;

typedef enum : uint8_t {
  k_ra8_adc_b_ext_chan_base = 0x60U, 
} ra8_adc_b_ext_chan_base_t;

typedef enum : uint8_t {
  k_ra8_adsgdcr_bit_diagval = 0U, 
} ra8_adsgdcr_bit_t;

typedef enum : uint32_t {
  k_ra8_adsgdcr_mask_diagval = 0x00000007UL, 
} ra8_adsgdcr_mask_t;

typedef enum : uint8_t {
  k_ra8_adsgdcr_diag_off   = 0x0U, 
  k_ra8_adsgdcr_diag_mode1 = 0x4U, 
  k_ra8_adsgdcr_diag_mode2 = 0x5U, 
  k_ra8_adsgdcr_diag_mode3 = 0x6U, 
} ra8_adsgdcr_diag_t;

typedef enum : uint8_t {
  k_ra8_addopcrc_bit_adprc   = 16U, 
  k_ra8_addopcrc_bit_signsel = 20U, 
} ra8_addopcrc_bit_t;

typedef enum : uint32_t {
  k_ra8_addopcrc_mask_adprc   = 0x00030000UL, 
  k_ra8_addopcrc_mask_signsel = 0x00100000UL, 
} ra8_addopcrc_mask_t;

typedef enum : uint8_t {
  k_ra8_addopcrc_adprc_16bit = 0x0U, 
  k_ra8_addopcrc_adprc_14bit = 0x1U, 
  k_ra8_addopcrc_adprc_12bit = 0x2U, 
  k_ra8_addopcrc_adprc_10bit = 0x3U, 
} ra8_addopcrc_adprc_t;

typedef enum : uint8_t {
  k_ra8_addopcrc_signsel_signed   = 0U, 
  k_ra8_addopcrc_signsel_unsigned = 1U, 
} ra8_addopcrc_signsel_t;

typedef enum : uint8_t {
  k_ra8_adexdr_bit_diagsr = 24U, 
  k_ra8_adexdr_bit_err    = 31U, 
} ra8_adexdr_bit_t;

typedef enum : uint32_t {
  k_ra8_adexdr_mask_data   = 0x0000FFFFUL, 
  k_ra8_adexdr_mask_diagsr = 0x07000000UL, 
  k_ra8_adexdr_mask_err    = 0x80000000UL, 
} ra8_adexdr_mask_t;

typedef enum : uint32_t {
  k_ra8_adsger_mask_sgren = 0x000001FFUL, 
} ra8_adsger_mask_t;

typedef enum : uint32_t {
  k_ra8_adsystr_mask_adsystn = 0x000001FFUL, 
} ra8_adsystr_mask_t;

typedef enum : uint32_t {
  k_ra8_adstr_mask_adst = 0x00000001UL, 
} ra8_adstr_mask_t;

typedef enum : uint8_t {
  k_ra8_adsr_bit_adact0  = 0U,  
  k_ra8_adsr_bit_adact1  = 1U,  
  k_ra8_adsr_bit_calact0 = 16U, 
  k_ra8_adsr_bit_calact1 = 17U, 
} ra8_adsr_bit_t;

typedef enum : uint32_t {
  k_ra8_adsr_mask_adact0  = 0x00000001UL, 
  k_ra8_adsr_mask_adact1  = 0x00000002UL, 
  k_ra8_adsr_mask_adact   = 0x00000003UL, 
  k_ra8_adsr_mask_calact0 = 0x00010000UL, 
  k_ra8_adsr_mask_calact1 = 0x00020000UL, 
} ra8_adsr_mask_t;

typedef enum : uint32_t {
  k_ra8_adstopr_mask_adstop0 = 0x00000001UL, 
  k_ra8_adstopr_mask_adstop1 = 0x00000100UL, 
} ra8_adstopr_mask_t;

typedef enum : uint32_t {
  k_ra8_addr_mask_data = 0x0000FFFFUL, 
  k_ra8_addr_mask_err  = 0x80000000UL, 
} ra8_addr_mask_t;

typedef enum : uint32_t {
  k_ra8_adtrgenr_mask_sttrgen = 0x000001FFUL, 
} ra8_adtrgenr_mask_t;

typedef enum : uint32_t {
  k_ra8_adcmpenr_mask_cmpen = 0x000000FFUL, 
} ra8_adcmpenr_mask_t;

typedef enum : uint8_t {
  k_ra8_adcmptbr_bit_low  = 0U,  
  k_ra8_adcmptbr_bit_high = 16U, 
} ra8_adcmptbr_bit_t;

typedef enum : uint32_t {
  k_ra8_adcmptbr_mask_low  = 0x0000FFFFUL, 
  k_ra8_adcmptbr_mask_high = 0xFFFF0000UL, 
} ra8_adcmptbr_mask_t;

typedef enum : uint8_t {
  k_ra8_adcmpmd_disabled   = 0x0U, 
  k_ra8_adcmpmd_inside     = 0x1U, 
  k_ra8_adcmpmd_outside    = 0x2U, 
  k_ra8_adcmpmd_greater_eq = 0x3U, 
} ra8_adcmpmd_t;

typedef enum : uint8_t {
  k_ra8_adcmpmd_field_width = 2U, 
  k_ra8_adcmpmd_field_step  = 8U, 
  k_ra8_adcmpmd_per_reg     = 4U, 
} ra8_adcmpmd_layout_t;

typedef enum : uint8_t {
  k_ra8_addopcrb_bit_avemd    = 0U,  
  k_ra8_addopcrb_bit_adc      = 8U,  
  k_ra8_addopcrb_bit_cmptblem = 16U, 
} ra8_addopcrb_bit_t;

typedef enum : uint32_t {
  k_ra8_addopcrb_mask_avemd    = 0x00000003UL, 
  k_ra8_addopcrb_mask_adc      = 0x00000F00UL, 
  k_ra8_addopcrb_mask_cmptblem = 0x00FF0000UL, 
} ra8_addopcrb_mask_t;

typedef enum : uint8_t {
  k_ra8_avemd_off     = 0x0U, 
  k_ra8_avemd_add     = 0x1U, 
  k_ra8_avemd_average = 0x2U, 
} ra8_addopcrb_avemd_t;

typedef enum : uint8_t {
  k_ra8_adc_avg_1x  = 0x0U, 
  k_ra8_adc_avg_2x  = 0x1U, 
  k_ra8_adc_avg_4x  = 0x2U, 
  k_ra8_adc_avg_8x  = 0x3U, 
  k_ra8_adc_avg_16x = 0x4U, 
  k_ra8_adc_avg_64x = 0x6U, 
} ra8_addopcrb_adc_t;

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adclkenr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adclkenr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adclksr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adclksr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adclkcr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adclkcr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_admdr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr + (uintptr_t)k_ra8_adc_b_off_admdr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adsger(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr + (uintptr_t)k_ra8_adc_b_off_adsger);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adintcr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adintcr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adsystr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adsystr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adstopr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adstopr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adsr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr + (uintptr_t)k_ra8_adc_b_off_adsr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adchcr(uint8_t ch)
{
  if (ch >= k_ra8_adc_b_max_channels) {
    return nullptr;
  }
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adchcr0 +
                              ((uintptr_t)ch * (uintptr_t)k_ra8_adc_b_adchcr_stride));
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adstr(uint8_t group)
{
  if (group >= k_ra8_adc_b_scan_groups) {
    return nullptr;
  }
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr + (uintptr_t)k_ra8_adc_b_off_adstr0 +
                              ((uintptr_t)group * (uintptr_t)k_ra8_adc_b_adstr_stride));
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adtrgenr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adtrgenr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adcmpenr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adcmpenr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adcmpintcr(void)
{
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adcmpintcr);
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adcmpmdr(uint8_t which)
{
  if (which == 0U) {
    return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                                (uintptr_t)k_ra8_adc_b_off_adcmpmdr0);
  }
  if (which == 1U) {
    return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                                (uintptr_t)k_ra8_adc_b_off_adcmpmdr1);
  }
  return nullptr;
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adcmptbr(uint8_t table)
{
  if (table >= k_ra8_adc_b_cmp_tables) {
    return nullptr;
  }
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adcmptbr0 +
                              ((uintptr_t)table * (uintptr_t)k_ra8_adc_b_cmptbr_stride));
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_addopcrb(uint8_t ch)
{
  if (ch >= k_ra8_adc_b_max_channels) {
    return nullptr;
  }
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_addopcrb0 +
                              ((uintptr_t)ch * (uintptr_t)k_ra8_adc_b_adchcr_stride));
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_addr(uint8_t ch)
{
  if (ch >= k_ra8_adc_b_result_regs) {
    return nullptr;
  }
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr + (uintptr_t)k_ra8_adc_b_off_addr0 +
                              ((uintptr_t)ch * (uintptr_t)k_ra8_adc_b_addr_stride));
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adsgdcr(uint8_t group)
{
  if (group >= k_ra8_adc_b_scan_groups) {
    return nullptr;
  }
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adsgdcr0 +
                              ((uintptr_t)group * (uintptr_t)k_ra8_adc_b_adsgdcr_stride));
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_addopcrc(uint8_t ch)
{
  if (ch >= k_ra8_adc_b_max_channels) {
    return nullptr;
  }
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_addopcrc0 +
                              ((uintptr_t)ch * (uintptr_t)k_ra8_adc_b_adchcr_stride));
}

RA8_HW_REGISTER_ACCESS
static inline volatile uint32_t* ra8_adc_b_adexdr(uint8_t n)
{
  if (n >= k_ra8_adc_b_ext_data_regs) {
    return nullptr;
  }
  return (volatile uint32_t*)((uintptr_t)k_ra8_adc_b_base_addr +
                              (uintptr_t)k_ra8_adc_b_off_adexdr0 +
                              ((uintptr_t)n * (uintptr_t)k_ra8_adc_b_adexdr_stride));
}

typedef enum : uint8_t {
  k_ra8_adc_b_adexdr_no_index = 0xFFU, 
} ra8_adc_b_adexdr_sentinel_t;

static inline uint8_t ra8_adc_b_adexdr_index_for_chan(uint8_t cnvcs)
{
  if (cnvcs < (uint8_t)k_ra8_adc_b_ext_chan_base) {
    return (uint8_t)k_ra8_adc_b_adexdr_no_index;
  }
  return (uint8_t)(cnvcs - (uint8_t)k_ra8_adc_b_ext_chan_base);
}
 
#ifdef __cplusplus
}
#endif