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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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High-Speed Analog Comparator (ACMPHS) register layout for the RA8D2. More...
Go to the source code of this file.
Data Structures | |
| struct | r_acmphs_regs_t |
| Per-channel ACMPHS register window. More... | |
Enumerations | |
| enum | ra8_acmphs_addr_t : uintptr_t { k_ra8_acmphs0_base_addr = 0x40236000UL } |
| Memory-mapped base addresses for ACMPHS. More... | |
| enum | ra8_acmphs_limits_t : uint16_t { k_ra8_acmphs_channel_count = 6U , k_ra8_acmphs_channel_stride = 0x100U , k_ra8_acmphs_reserved_mid = 47U } |
| Channel count and stride. More... | |
| enum | ra8_cmpctl_bit_t : uint8_t { k_ra8_acmphs_bit_cinv = 0U , k_ra8_acmphs_bit_coe = 1U , k_ra8_acmphs_bit_csten = 2U , k_ra8_acmphs_bit_ceg0 = 3U , k_ra8_acmphs_bit_ceg1 = 4U , k_ra8_acmphs_bit_cdfs0 = 5U , k_ra8_acmphs_bit_cdfs1 = 6U , k_ra8_acmphs_bit_hcmpon = 7U } |
| CMPCTL control-bit positions (verified against FSP R_ACMPHS0_CMPCTL_b, R7KA8D2KF_core0.h lines 3874-3884). More... | |
| enum | ra8_acmphs_mask_t : uint8_t { k_ra8_acmphs_mask_cinv = 0x01U , k_ra8_acmphs_mask_coe = 0x02U , k_ra8_acmphs_mask_csten = 0x04U , k_ra8_acmphs_mask_ceg = 0x18U , k_ra8_acmphs_mask_cdfs = 0x60U , k_ra8_acmphs_mask_hcen = 0x80U , k_ra8_acmphs_mask_hcmon = 0x01U } |
| CMPCTL bit masks. More... | |
Functions | |
| static volatile r_acmphs_regs_t * | ra8_acmphs (uint8_t channel) |
| Get pointer to ACMPHS channel channel. | |
High-Speed Analog Comparator (ACMPHS) register layout for the RA8D2.
The RA8D2 exposes up to six high-speed analog comparator channels (ACMPHS0..ACMPHS5). Each channel has a small independent register window at base 0x40324000 with a 0x100 stride.
Per-channel registers:
| Offset | Name | Width | Purpose |
|---|---|---|---|
| 0x00 | CMPCTL | 8 | Comparator control (HCMON, HCEN, ...) |
| 0x04 | CMPSEL0 | 8 | Plus-input selection |
| 0x08 | CMPSEL1 | 8 | Minus-input selection |
| 0x0C | CMPMON | 8 | Output monitor (read-only) |
| 0x10 | CPIOC | 8 | Output polarity / pin control |
| 0x40 | CPINTCTL | 8 | Interrupt control |
| 0x44 | CPMSKCTL | 8 | Interrupt mask control |
Register offsets tracked against HUM Ch 56 "High-Speed Analog Comparator (ACMPHS)" p 3508.
Definition in file ra8_acmphs_regs.h.
| enum ra8_acmphs_addr_t : uintptr_t |
Memory-mapped base addresses for ACMPHS.
| Enumerator | |
|---|---|
| k_ra8_acmphs0_base_addr | ACMPHS channel 0 base (FSP R_ACMPHS0_BASE). |
Definition at line 44 of file ra8_acmphs_regs.h.
| enum ra8_acmphs_limits_t : uint16_t |
Channel count and stride.
| Enumerator | |
|---|---|
| k_ra8_acmphs_channel_count | Channels 0..5 on this package. |
| k_ra8_acmphs_channel_stride | Bytes between channels. |
| k_ra8_acmphs_reserved_mid | Reserved gap CPIOC->CPINTCTL. |
Definition at line 52 of file ra8_acmphs_regs.h.
| enum ra8_acmphs_mask_t : uint8_t |
CMPCTL bit masks.
Definition at line 78 of file ra8_acmphs_regs.h.
| enum ra8_cmpctl_bit_t : uint8_t |
CMPCTL control-bit positions (verified against FSP R_ACMPHS0_CMPCTL_b, R7KA8D2KF_core0.h lines 3874-3884).
Definition at line 63 of file ra8_acmphs_regs.h.
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inlinestatic |
Get pointer to ACMPHS channel channel.
| [in] | channel | Channel index (0..5). |
Definition at line 123 of file ra8_acmphs_regs.h.
References k_ra8_acmphs0_base_addr, k_ra8_acmphs_channel_count, and k_ra8_acmphs_channel_stride.
Referenced by internal_reset_channel(), ra8_acmphs_channel_deinit(), ra8_acmphs_channel_enable(), ra8_acmphs_channel_init(), ra8_acmphs_clear_status(), ra8_acmphs_get_status(), ra8_acmphs_read_output(), and ra8_acmphs_set_inputs().