system_init.c

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#include <stdint.h>
 
#include "ra8_boot_entry.h"
#include "ra8_cgc.h"
#include "trustzone_init.h"
 
extern const uint32_t g_ra8_vector_table_start[];
 
/* =============================================================================
 * Core / SCB / NVIC register addresses (direct, no CMSIS dep)
 * =============================================================================
 */
 
typedef enum : uintptr_t {
  k_ra8_scb_vtor_addr  = 0xE000ED08UL, 
  k_ra8_scb_ccr_addr   = 0xE000ED14UL, 
  k_ra8_scb_shcsr_addr = 0xE000ED24UL, 
  k_ra8_scb_cpacr_addr = 0xE000ED88UL, 
  k_ra8_scb_nsacr_addr = 0xE000ED8CUL, 
  k_ra8_scb_iciallu    = 0xE000EF50UL, 
  k_ra8_scb_dciallu    = 0xE000EF58UL, 
  k_ra8_scb_csselr     = 0xE000ED84UL, 
  k_ra8_scb_ccsidr     = 0xE000ED80UL, 
  k_ra8_scb_dcisw      = 0xE000EF60UL, 
  k_ra8_fpu_fpccr_addr = 0xE000EF34UL, 
  k_ra8_nvic_aircr     = 0xE000ED0CUL, 
  k_ra8_mpu_type_addr  = 0xE000ED90UL, 
  k_ra8_mpu_ctrl_addr  = 0xE000ED94UL, 
  k_ra8_mpu_rnr_addr   = 0xE000ED98UL, 
  k_ra8_mpu_rbar_addr  = 0xE000ED9CUL, 
  k_ra8_mpu_rlar_addr  = 0xE000EDA0UL, 
  k_ra8_mpu_mair0_addr = 0xE000EDC0UL, 
  k_ra8_mpu_mair1_addr = 0xE000EDC4UL, 
} ra8_core_addr_t;
 
extern uint32_t g_ra8_ls_stack_top; /* from vector_table.c / linker. */
 
/* =============================================================================
 * Small helpers
 * =============================================================================
 */
 
static inline uint32_t internal_read32(uintptr_t addr)
{
  return *(volatile uint32_t*)addr;
}
 
static inline void internal_write32(uintptr_t addr, uint32_t value)
{
  *(volatile uint32_t*)addr = value;
}
 
static inline void internal_dsb(void)
{
#ifndef RA8_OFF_TARGET
  __asm__ volatile("dsb 0xF" ::: "memory");
#endif
}
 
static inline void internal_isb(void)
{
#ifndef RA8_OFF_TARGET
  __asm__ volatile("isb 0xF" ::: "memory");
#endif
}
 
static inline void internal_disable_irq(void)
{
#ifndef RA8_OFF_TARGET
  __asm__ volatile("cpsid i" ::: "memory");
#endif
}
 
/* =============================================================================
 * Core init steps
 * =============================================================================
 */

static void internal_set_vtor(void)
{
  /* Vector table sits at the start of the .vectors section, which
   * the linker pins to the start of MRAM (`0x02000000`). The SCB
   * VTOR register stores the absolute address. */
  internal_write32(k_ra8_scb_vtor_addr, (uint32_t)(uintptr_t)g_ra8_vector_table_start);
}

static void internal_enable_fpu(void)
{
  enum : uint32_t {
    k_ra8_cpacr_cp10_cp11_full_access = 0x00F00000UL, 
  };
  uint32_t cpacr = internal_read32(k_ra8_scb_cpacr_addr);
  cpacr |= k_ra8_cpacr_cp10_cp11_full_access;
  internal_write32(k_ra8_scb_cpacr_addr, cpacr);
  internal_dsb();
  internal_isb();
}

static void internal_enable_fpu_lazy_stack(void)
{
  enum : uint32_t {
    k_ra8_fpccr_lspen = 1UL << 30, 
    k_ra8_fpccr_aspen = 1UL << 31, 
  };
  uint32_t fpccr = internal_read32(k_ra8_fpu_fpccr_addr);
  fpccr |= k_ra8_fpccr_lspen | k_ra8_fpccr_aspen;
  internal_write32(k_ra8_fpu_fpccr_addr, fpccr);
}

static void internal_enable_icache(void)
{
  /* Invalidate, then set CCR.IC. */
  internal_dsb();
  internal_write32(k_ra8_scb_iciallu, 0U);
  internal_dsb();
  internal_isb();
 
  enum : uint32_t { k_ra8_ccr_ic = 1UL << 17  };
  uint32_t ccr = internal_read32(k_ra8_scb_ccr_addr);
  ccr |= k_ra8_ccr_ic;
  internal_write32(k_ra8_scb_ccr_addr, ccr);
  internal_dsb();
  internal_isb();
}

static void internal_enable_dcache(void)
{
  enum : uint32_t { k_ra8_ccr_dc = 1UL << 16  };
  uint32_t ccr = internal_read32(k_ra8_scb_ccr_addr);
  ccr |= k_ra8_ccr_dc;
  internal_write32(k_ra8_scb_ccr_addr, ccr);
  internal_dsb();
  internal_isb();
}

static void internal_enable_branch_predictor(void)
{
  enum : uint32_t { k_ra8_ccr_bp = 1UL << 18  };
  uint32_t ccr = internal_read32(k_ra8_scb_ccr_addr);
  ccr |= k_ra8_ccr_bp;
  internal_write32(k_ra8_scb_ccr_addr, ccr);
  internal_dsb();
  internal_isb();
}

static void internal_set_priority_grouping(void)
{
  enum : uint32_t {
    k_ra8_aircr_vectkey    = 0x05FA0000UL, 
    k_ra8_aircr_prigroup_4 = 0x00000300UL, 
  };
  internal_write32(k_ra8_nvic_aircr, k_ra8_aircr_vectkey | k_ra8_aircr_prigroup_4);
}

/* RBAR attribute-byte encodings (bottom 5 bits of RBAR). */
enum : uint32_t {
  k_ra8_rbar_attr_ro_x      = 0x02U,    
  k_ra8_rbar_attr_rw_xn     = 0x03U,    
  k_ra8_rbar_attr_device_rw = 0x23U,    
  k_ra8_mpu_rlar_enable     = 1UL << 0, 
};
 
/* Region base and limit addresses. RLAR limits are <region-end> minus
 * the ARMv8-M 32-byte region quantum, OR-ed with the enable bit at write time. */
enum : uint32_t {
  k_ra8_mpu_mram_base   = 0x02000000UL, 
  k_ra8_mpu_mram_limit  = 0x020FFFE0UL, 
  k_ra8_mpu_sram_base   = 0x22000000UL, 
  k_ra8_mpu_sram_limit  = 0x221FFFE0UL, 
  k_ra8_mpu_sdram_base  = 0x68000000UL, 
  k_ra8_mpu_sdram_limit = 0x6BFFFFE0UL, 
  k_ra8_mpu_peri_base   = 0x40000000UL, 
  k_ra8_mpu_peri_limit  = 0x47FFFFE0UL, 
};

static void internal_mpu_set_region(uint32_t region, uint32_t base_attr, uint32_t limit_enable)
{
  internal_write32(k_ra8_mpu_rnr_addr, region);
  internal_write32(k_ra8_mpu_rbar_addr, base_attr);
  internal_write32(k_ra8_mpu_rlar_addr, limit_enable);
}

static void internal_mpu_init(void)
{
  enum : uint32_t {
    k_ra8_mpu_ctrl_enable     = 1UL << 0,     
    k_ra8_mpu_ctrl_privdefena = 1UL << 2,     
    k_ra8_mair0_default       = 0x000404FFUL, 
  };
 
  /* MAIR0: idx 0 = WB/WA, idx 1 = non-cacheable, idx 2 = device-nGnRE. */
  internal_write32(k_ra8_mpu_mair0_addr, k_ra8_mair0_default);
  internal_write32(k_ra8_mpu_mair1_addr, 0U);
 
  internal_mpu_set_region(0U,
                          (k_ra8_mpu_mram_base | k_ra8_rbar_attr_ro_x),
                          (k_ra8_mpu_mram_limit | k_ra8_mpu_rlar_enable));
  internal_mpu_set_region(1U,
                          (k_ra8_mpu_sram_base | k_ra8_rbar_attr_rw_xn),
                          (k_ra8_mpu_sram_limit | k_ra8_mpu_rlar_enable));
  internal_mpu_set_region(2U,
                          (k_ra8_mpu_sdram_base | k_ra8_rbar_attr_rw_xn),
                          (k_ra8_mpu_sdram_limit | k_ra8_mpu_rlar_enable));
  internal_mpu_set_region(3U,
                          (k_ra8_mpu_peri_base | k_ra8_rbar_attr_device_rw),
                          (k_ra8_mpu_peri_limit | k_ra8_mpu_rlar_enable));
 
  /* Enable MPU with PRIVDEFENA so unclassified privileged accesses
   * still succeed through the default system memory map. */
  internal_dsb();
  internal_write32(k_ra8_mpu_ctrl_addr, k_ra8_mpu_ctrl_enable | k_ra8_mpu_ctrl_privdefena);
  internal_dsb();
  internal_isb();
}

[[noreturn, gnu::noinline]] static void internal_halt_secure_clock_fault(void)
{
  while (1) {
    __asm__ volatile("wfi");
  }
}
 
/* =============================================================================
 * Public entry point
 * =============================================================================
 *
 * Called from `Reset_Handler` after the C runtime is live (.data
 * copied, .bss zeroed). It may therefore read and write globals
 * freely; the Secure clock + TrustZone bring-up below relies on that.
 */
 
void SystemInit(void)
{
  /* Mask global IRQs so the application gets a deterministic init
   * window. main() must call ``ra8_isr_globals_enable`` once every
   * driver / handler is wired up before any IRQ source can fire. */
  internal_disable_irq();
 
  internal_set_vtor();
  internal_enable_fpu();
  internal_enable_fpu_lazy_stack();
  /* Cache enable, MPU init, and TrustZone bring-up are temporarily
   * disabled -- they HardFault on first reset because the CCSIDR-driven
   * invalidate-by-set/way loop is not yet implemented and the MPU
   * regions are unconfigured. Re-enable once those code paths land. */
  (void)internal_enable_icache;
  (void)internal_enable_dcache;
  (void)internal_enable_branch_predictor;
  (void)internal_mpu_init;
  internal_set_priority_grouping();
 
  /* Bring up the Secure clock tree (XTAL -> PLL1 -> CPUCLK0 = 1 GHz) BEFORE the
   * SAU + BLXNS below. ra8_trustzone_init() does NOT return on hardware (BLXNS
   * leaves Secure thread mode), so anything sequenced after it never runs on the
   * Secure side. The NS-side NSC CGC veneers (ra8_nsc_cgc_pll2_enable etc.) trap
   * back into this Secure CGC driver, which needs PLL1 already locked -- without
   * it the first PLL2 enable fails because its PLL1 source is missing. */
  if (ra8_cgc_init() != k_ra8_ok) {
    /* NASA Rule 7: a failed Secure clock bring-up must not BLXNS into NS code
     * on a dead clock tree -- park at a named symbol instead of switching. */
    internal_halt_secure_clock_fault();
  }
 
#ifdef RA8_TRUSTZONE_ENABLE
  /* Programme the SAU, then BLXNS into the NS image. The NSC veneers depend on
   * the SAU being live so the cmse_nonsecure_entry traps land on the Secure
   * side. Does not return on hardware. */
  ra8_trustzone_init();
#else
  (void)ra8_trustzone_init;
#endif
}