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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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CPU0 (M85) Secure fallback entry for the TZ ping-pong demo. More...
Go to the source code of this file.
Functions | |
| void | main (void) |
| CPU0 S-side fallback entry point. | |
Variables | |
| volatile uint32_t | g_cpu1_pingpong_s_fallback_count = 0U |
| Bench diagnostic: bumps when the S-side fallback main runs. | |
CPU0 (M85) Secure fallback entry for the TZ ping-pong demo.
On the happy path this function is never reached. SystemInit calls ra8_trustzone_init, which programmes the SAU, writes IPCSAR=0x00050000, releases CPU1 via ra8_cpu1_release (still in S), then BLXNS-es into the NS image at 0x02080000 (ns_reset_handler in ns_main.c). BLXNS does not return on hardware, so the Reset_Handler step that calls main() is unreachable.
If the BLXNS path fails – the NS vector table is blank, the SAU could not be programmed, or the IPCSAR write was rejected – the secure-boot library returns and main becomes the fallback. We stamp a diagnostic counter so the bench memprobe can distinguish "BLXNS succeeded -> main never ran" (counter stays 0) from "BLXNS failed -> main ran" (counter advances). The fallback then parks the CPU in a NOP loop so it cannot accidentally touch the NS-attributed IPC channels (which would BusFault in S state).
Definition in file main.c.
| void main | ( | void | ) |
CPU0 S-side fallback entry point.
The application entry point Reset_Handler hands control to.
See file header.
Definition at line 67 of file main.c.
References g_cpu1_pingpong_s_fallback_count.
| volatile uint32_t g_cpu1_pingpong_s_fallback_count = 0U |
Bench diagnostic: bumps when the S-side fallback main runs.
Stays 0 on the happy path because BLXNS in ra8_trustzone_init never returns. Any non-zero value means the secure-boot library bailed out before transferring control to the NS image – bench scripts should treat that as a regression in the TZ scaffolding, not in the NS ping-pong logic.
Definition at line 49 of file main.c.
Referenced by main().