- Generated by
1.16.1
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ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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Self-contained Non-Secure image at 0x02080000 for the IPC ping-pong demo. More...
Go to the source code of this file.
Enumerations | |
| enum | ns_ipc_const_t : uintptr_t { k_ns_ipc_base = 0x50020000UL , k_ns_ipc_ch0_addr = 0x500200C0UL , k_ns_ipc_ch2_addr = 0x50020100UL } |
| Register layout for the IPC channels CPU0 owns in NS state. More... | |
| enum | ns_ipc_off_t : uint8_t { k_ns_ipc_off_sta = 0x00U , k_ns_ipc_off_set = 0x04U , k_ns_ipc_off_txd = 0x08U , k_ns_ipc_off_rxd = 0x0CU , k_ns_ipc_off_clr = 0x10U } |
| In-channel offsets for STA/ISET/TXD/RXD/CLR. More... | |
| enum | ns_ipc_sta_mask_t : uint32_t { k_ns_ipc_sta_rdy = 0x00010000UL } |
| STA register bits we care about. More... | |
| enum | ns_pingpong_step_t : uint32_t { k_ns_step_bss_zeroed = 1U , k_ns_step_channels_up = 2U , k_ns_step_tx_start = 3U , k_ns_step_tx_done = 5U , k_ns_step_rx_timeout = 6U , k_ns_step_rx_word = 7U } |
| Progress markers written to g_ns_pingpong_step. More... | |
| enum | ns_pingpong_marker_t : uint32_t { k_ns_entry_marker = 0xCAFEBABEUL } |
| Sentinel written to g_ns_pingpong_entry_marker. More... | |
| enum | ns_ipc_clr_mask_t : uint32_t { k_ns_ipc_clr_all = 0x030100FFUL } |
| CLR register bits we use for init / status clear. More... | |
| enum | ns_pingpong_magic_t : uint32_t { k_ns_magic_ping = 0x1234U , k_ns_magic_pong = 0x4321U } |
| Ping-pong handshake words exchanged between CPU0 and CPU1. More... | |
| enum | ns_pingpong_poll_t : uint32_t { k_ns_recv_poll_max = 1000000UL } |
| Receive poll budget per ping-pong iteration. More... | |
Functions | |
| static void | internal_ns_write32 (uintptr_t addr, uint32_t value) |
| 32-bit MMIO write helper. | |
| static uint32_t | internal_ns_read32 (uintptr_t addr) |
| 32-bit MMIO read helper. | |
| static void | internal_ns_ipc_channel_reset (uintptr_t ch_base) |
| Reset one IPC channel's FIFO and clear all sticky status bits. | |
| static void | internal_ns_ipc_send (uintptr_t ch_base, uint32_t msg) |
| Push one 32-bit word onto a channel's transmit FIFO. | |
| static uint32_t | internal_ns_ipc_recv (uintptr_t ch_base, uint32_t *out_word) |
| Bounded RDY poll + single drain of a channel's receive FIFO. | |
| void | ns_reset_handler (void) |
Variables | |
| volatile uint32_t | g_ns_pingpong_match = 0U |
| NS-side HIL liveness counter. | |
| volatile uint32_t | g_ns_pingpong_mismatch = 0U |
| NS-side HIL failure counter. | |
| volatile uint32_t | g_ns_pingpong_step = 0U |
| NS reset-handler progress tracker. | |
| volatile uint32_t | g_ns_pingpong_last_rxd = 0U |
| Most recent word read off the receive channel. | |
| volatile uint32_t | g_ns_pingpong_entry_marker = 0U |
| First word stamped by ns_reset_handler – proves NS state actually entered the image (vs the S fallback path). | |
| uint32_t | g_ra8_ls_ns_bss_start |
| NS world reset handler – entry point of the BLXNS branch. | |
| uint32_t | g_ra8_ls_ns_bss_end |
| uint32_t | g_ra8_ls_ns_stack_top |
| const uint32_t | g_ra8_ns_vector_table [8] |
| NS-world ARMv8-M vector table. | |
Self-contained Non-Secure image at 0x02080000 for the IPC ping-pong demo.
After the S-side trustzone_init programmes the SAU and writes IPCSAR=0x00050000 it BLXNS-es to ns_reset_handler here. Once CPU0 is in NS state the IPCSAR-attributed channels 0 (CPU1->CPU0) and 2 (CPU0->CPU1) become reachable. The S side has already released CPU1 via ra8_cpu1_release before the BLXNS, so CPU1 is fetching its own image and is the IPC peer for the ping-pong loop below.
The NS image is intentionally self-contained: it cannot call any function whose code resides in S MRAM without an NSC veneer, so the IPC accessors are open-coded against the register window. Counters live in NS SRAM and are read externally via SWD (the J-Link debug controller sees both worlds).
| Symbol | Section | Address |
|---|---|---|
| g_ra8_ns_vector_table | .ns_vectors | 0x02080000 |
| ns_reset_handler | .ns_text | 0x02080000+ |
| g_ns_pingpong_* counters | .ns_bss | 0x22100000+ |
Definition in file ns_main.c.
| enum ns_ipc_clr_mask_t : uint32_t |
CLR register bits we use for init / status clear.
| Enumerator | |
|---|---|
| k_ns_ipc_clr_all | RST | RCLR | FCLR | CLR7..CLR0. |
| enum ns_ipc_const_t : uintptr_t |
Register layout for the IPC channels CPU0 owns in NS state.
| Enumerator | |
|---|---|
| k_ns_ipc_base | IPC peripheral base (NS alias). |
| k_ns_ipc_ch0_addr | CPU0 RX from CPU1 (NS alias). |
| k_ns_ipc_ch2_addr | CPU0 TX to CPU1 (NS alias). |
| enum ns_ipc_off_t : uint8_t |
| enum ns_ipc_sta_mask_t : uint32_t |
| enum ns_pingpong_magic_t : uint32_t |
| enum ns_pingpong_marker_t : uint32_t |
Sentinel written to g_ns_pingpong_entry_marker.
Stamped AFTER the .bss zero so the bench can tell "BLXNS reached NS" apart from "the marker happened to land back at 0".
| Enumerator | |
|---|---|
| k_ns_entry_marker | NS entry was reached. |
| enum ns_pingpong_poll_t : uint32_t |
| enum ns_pingpong_step_t : uint32_t |
Progress markers written to g_ns_pingpong_step.
The bench reads this word over J-Link to see how far the NS image got. Values ascend with execution order, so a dump alone says where it stopped.
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static |
Reset one IPC channel's FIFO and clear all sticky status bits.
| [in] | ch_base | Base address of the channel (e.g. k_ns_ipc_ch0_addr). |
Definition at line 281 of file ns_main.c.
References internal_ns_write32(), k_ns_ipc_clr_all, and k_ns_ipc_off_clr.
Referenced by ns_reset_handler().
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static |
Bounded RDY poll + single drain of a channel's receive FIFO.
| [in] | ch_base | Channel base address. |
| [out] | out_word | Receives the dequeued word on success. |
Definition at line 331 of file ns_main.c.
References internal_ns_read32(), k_ns_ipc_off_rxd, k_ns_ipc_off_sta, k_ns_ipc_sta_rdy, k_ns_recv_poll_max, and RA8_INTERNAL.
Referenced by ns_reset_handler().
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static |
Push one 32-bit word onto a channel's transmit FIFO.
| [in] | ch_base | Channel base address. |
| [in] | msg | Word to push. |
Definition at line 304 of file ns_main.c.
References internal_ns_write32(), k_ns_ipc_off_txd, and RA8_INTERNAL.
Referenced by ns_reset_handler().
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inlinestatic |
32-bit MMIO read helper.
| [in] | addr | Physical address. |
Definition at line 259 of file ns_main.c.
References RA8_INTERNAL.
Referenced by internal_ns_ipc_recv().
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inlinestatic |
32-bit MMIO write helper.
| [in] | addr | Physical address. |
| [in] | value | Value to write. |
Definition at line 243 of file ns_main.c.
References RA8_INTERNAL.
Referenced by internal_ns_ipc_channel_reset(), and internal_ns_ipc_send().
| void ns_reset_handler | ( | void | ) |
Definition at line 384 of file ns_main.c.
References g_ns_pingpong_entry_marker, g_ns_pingpong_last_rxd, g_ns_pingpong_match, g_ns_pingpong_mismatch, g_ns_pingpong_step, g_ra8_ls_ns_bss_end, g_ra8_ls_ns_bss_start, internal_ns_ipc_channel_reset(), internal_ns_ipc_recv(), internal_ns_ipc_send(), k_ns_entry_marker, k_ns_ipc_ch0_addr, k_ns_ipc_ch2_addr, k_ns_magic_ping, k_ns_magic_pong, k_ns_step_bss_zeroed, k_ns_step_channels_up, k_ns_step_rx_timeout, k_ns_step_rx_word, k_ns_step_tx_done, and k_ns_step_tx_start.
| volatile uint32_t g_ns_pingpong_entry_marker = 0U |
First word stamped by ns_reset_handler – proves NS state actually entered the image (vs the S fallback path).
If BLXNS in ra8_tz_secure_boot_jump_ns succeeded in transferring control to ns_reset_handler, this counter is stamped to 0xCAFEBABE before any other NS work happens. If it stays at 0 across a bench probe window, BLXNS failed to enter NS state and the boot continued in S.
Definition at line 225 of file ns_main.c.
Referenced by ns_reset_handler().
| volatile uint32_t g_ns_pingpong_last_rxd = 0U |
Most recent word read off the receive channel.
Latched on every successful drain regardless of magic value, so the bench can confirm "CPU1 is talking back" even if the magic comparison disagrees with the expected pong word.
Definition at line 208 of file ns_main.c.
Referenced by ns_reset_handler().
| volatile uint32_t g_ns_pingpong_match = 0U |
NS-side HIL liveness counter.
Increment is one full CPU0->CPU1->CPU0 round-trip where CPU0 sent k_ns_magic_ping on channel 2 and CPU1 returned k_ns_magic_pong on channel 0. Read externally over SWD; the memprobe gate asserts strictly monotonic growth.
Definition at line 169 of file ns_main.c.
Referenced by ns_reset_handler().
| volatile uint32_t g_ns_pingpong_mismatch = 0U |
NS-side HIL failure counter.
Bumped whenever a CPU0 iteration could not complete – RX timed out after k_ns_recv_poll_max polls, or the returned word was not the expected pong magic. Stays at 0 on a healthy bench.
Definition at line 181 of file ns_main.c.
Referenced by ns_reset_handler().
| volatile uint32_t g_ns_pingpong_step = 0U |
NS reset-handler progress tracker.
Definition at line 196 of file ns_main.c.
Referenced by ns_reset_handler().
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extern |
Referenced by ns_reset_handler(), and ns_reset_handler().
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extern |
NS world reset handler – entry point of the BLXNS branch.
Initialises the two channels CPU0 owns (channel 0 for receive, channel 2 for send), then loops ping->pong->bump-counter. The S-side already released CPU1 via ra8_cpu1_release in the trustzone_init path, so CPU1 is online by the time this handler runs.
MSP_NS has been set by the BLXNS prologue in ra8_tz_secure_boot_jump_ns from g_ra8_ns_vector_table[0], so we do not touch the stack pointer here.
BSS is implicitly zero (NS_BSS lives in MRAM at first power-on and each warm reset re-flashes the image), so we do not zero it.
Referenced by ns_reset_handler(), and ns_reset_handler().
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extern |
| const uint32_t g_ra8_ns_vector_table[8] |
NS-world ARMv8-M vector table.
Non-Secure vector table; run-time VMA NS_SRAM_RUN (0x32100000).
Slot 0 = initial MSP_NS, slot 1 = reset entry (Thumb bit set by the linker on function symbols), slots 2..7 reserved.
Slot 0 = initial MSP_NS, slot 1 = ns_reset_handler. Slots 14 (PendSV) and 15 (SysTick) drive the NS-resident ThreadX kernel (#96); fault slots halt. 8-byte aligned per ARMv8-M B3.10 (.ns_vectors aligns to 8).
Slot 0 = initial MSP_NS, slot 1 = ns_reset_handler. Every fault slot halts in ns_nmi_halt. MUST stay exactly 16 entries (64 bytes): the .ns_rot_header the Secure verifier reads is placed immediately after it (see ns_image.ld + k_ra8_tz_ns_rot_header_offset). 8-byte aligned per ARMv8-M B3.10 (.ns_vectors aligns to 8).
1.16.1