emu_exc_scs.c

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#include <stdio.h>
 
#include "board_periph.h"
#include "emu_console.h"
#include "emu_engine.h"
#include "emu_exc.h"
#include "emu_seams.h"

static bool s_reboot_request;

RA8_INTERNAL static void internal_on_scb_ctrl_write(uc_engine*  uc,
                                                    uc_mem_type type,
                                                    uint64_t    addr,
                                                    int         size,
                                                    int64_t     value,
                                                    void*       user)
{
  (void)type;
  (void)size;
  (void)user;
  const uint32_t word = (uint32_t)addr & ~3U;
  if (word == (uint32_t)k_scb_ccr) {
    if (((uint32_t)value & (uint32_t)k_ccr_div_0_trp) != 0U) {
      div0_patch_sites(uc); /* firmware opted in: overwrite the divides with UDF. */
    }
    return;
  }
  if (word != (uint32_t)k_scb_aircr) {
    return; /* an intervening SCB word (VTOR / SCR): not ours. */
  }
  if (((uint32_t)value & (1U << (uint32_t)k_aircr_sysresetreq)) == 0U) {
    return; /* a non-reset AIRCR write (e.g. priority grouping) */
  }
  s_reboot_request = true;
  (void)uc_emu_stop(uc); /* end the chunk; the run loop performs the reboot */
}

RA8_INTERNAL static void internal_on_nvic_en_write(uc_engine*  uc,
                                                   uc_mem_type type,
                                                   uint64_t    addr,
                                                   int         size,
                                                   int64_t     value,
                                                   void*       user)
{
  (void)uc;
  (void)type;
  (void)size;
  (void)user;
  const bool     is_set = (addr >= (uint64_t)k_nvic_iser_base) &&
                          (addr < ((uint64_t)k_nvic_iser_base + (uint64_t)k_nvic_en_span));
  const uint64_t base   = is_set ? (uint64_t)k_nvic_iser_base : (uint64_t)k_nvic_icer_base;
  const uint32_t word   = (uint32_t)((addr - base) / 4U);
  const uint32_t bits   = (uint32_t)value;
  for (uint32_t b = 0U; b < 32U; b++) {
    if ((bits & (1U << b)) != 0U) {
      board_periph_nvic_set_enable((word * 32U) + b, is_set);
    }
  }
}

typedef enum : uint64_t {
  k_dwt_ctrl_addr        = 0xE0001000UL, 
  k_dwt_cyccnt_addr      = 0xE0001004UL, 
  k_dwt_ctrl_cyccntena   = 0x00000001UL, 
  k_dwt_cyccnt_per_chunk = 500000UL,     
} dwt_model_t;

void dwt_cyccnt_advance(uc_engine* uc)
{
  const uint32_t demcr = rd32(uc, (uint64_t)k_scb_demcr_addr);
  if ((demcr & (uint32_t)k_scb_demcr_trcena) == 0U) {
    return; /* Trace subsystem off: CYCCNT does not count. */
  }
  const uint32_t ctrl = rd32(uc, (uint64_t)k_dwt_ctrl_addr);
  if ((ctrl & (uint32_t)k_dwt_ctrl_cyccntena) == 0U) {
    return; /* Cycle counter disabled: leave CYCCNT untouched. */
  }
  const uint32_t next = rd32(uc, (uint64_t)k_dwt_cyccnt_addr) + (uint32_t)k_dwt_cyccnt_per_chunk;
  wr32(uc, (uint64_t)k_dwt_cyccnt_addr, next);
}

void emu_exc_install_scb_nvic(uc_engine* uc)
{
  /* Watch the SCB control words AIRCR..CCR with ONE hook (internal_on_scb_ctrl_write): a
   * SYSRESETREQ store triggers a warm reboot and a CCR.DIV_0_TRP store arms the
   * div-0 trap (which then patches divides -- no per-access cost). Both are PPB
   * RAM, so a write-hook is the only way to observe them. */
  static uc_hook s_h_scb;
  (void)uc_hook_add(uc,
                    &s_h_scb,
                    UC_HOOK_MEM_WRITE,
                    (void*)internal_on_scb_ctrl_write,
                    nullptr,
                    (uint64_t)k_scb_aircr,
                    (uint64_t)k_scb_ccr + 3U);
  /* NVIC ISER / ICER are set-enable / clear-enable: fold each written bit into
   * board_periph's enable shadow so enabling several lines does not clobber the
   * earlier ones (see internal_on_nvic_en_write). The PPB is RAM, so this hook is the
   * only place the W1S/W1C semantics can be applied. */
  static uc_hook s_h_nvic_iser;
  static uc_hook s_h_nvic_icer;
  (void)uc_hook_add(uc,
                    &s_h_nvic_iser,
                    UC_HOOK_MEM_WRITE,
                    (void*)internal_on_nvic_en_write,
                    nullptr,
                    (uint64_t)k_nvic_iser_base,
                    (uint64_t)k_nvic_iser_base + (uint64_t)k_nvic_en_span - 1U);
  (void)uc_hook_add(uc,
                    &s_h_nvic_icer,
                    UC_HOOK_MEM_WRITE,
                    (void*)internal_on_nvic_en_write,
                    nullptr,
                    (uint64_t)k_nvic_icer_base,
                    (uint64_t)k_nvic_icer_base + (uint64_t)k_nvic_en_span - 1U);
}

bool emu_exc_reboot_requested(void)
{
  return s_reboot_request;
}

void emu_exc_clear_reboot_request(void)
{
  s_reboot_request = false;
}