emu_exc.h

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#pragma once
 
#include <stdint.h>
#include <unicorn/unicorn.h>
 
#include "ra8_attributes.h"
 
#ifdef __cplusplus
extern "C" {
#endif
 
/* Cortex-M system control space (architectural, all cores) -- inside the PPB.
 * The PPB is mapped as plain RAM here (not callback MMIO), so SCB/NVIC writes
 * the firmware performs land in memory and read back -- the exception model
 * below polls/edits these words to model what real M-profile hardware would do
 * with the NVIC that Unicorn does not implement. */
typedef enum : uint64_t {
  k_syst_csr          = 0xE000E010UL, 
  k_syst_csr_run      = 0x3UL,        
  k_scb_icsr          = 0xE000ED04UL, 
  k_scb_vtor          = 0xE000ED08UL, 
  k_scb_aircr         = 0xE000ED0CUL, 
  k_aircr_sysresetreq = 2UL,          
  k_scb_shpr2         = 0xE000ED1CUL, 
  k_scb_shpr3         = 0xE000ED20UL, 
  k_mpu_type          = 0xE000ED90UL, 
  k_mpu_type_seed     = 0x00000800UL, 
  k_mpu_ctrl          = 0xE000ED94UL, 
  k_mpu_rnr           = 0xE000ED98UL, 
  k_mpu_rbar          = 0xE000ED9CUL, 
  k_mpu_rlar          = 0xE000EDA0UL, 
  k_scb_ccr           = 0xE000ED14UL, 
  k_ccr_div_0_trp     = 0x10UL,       
  k_scb_cfsr          = 0xE000ED28UL, 
  k_scb_mmfar         = 0xE000ED34UL, 
  k_icsr_pendsvset    = 28UL,         
  k_icsr_pendstset    = 26UL,         
  k_exc_usagefault    = 6UL,          
  k_exc_memmanage     = 4UL,          
  k_exc_svcall        = 11UL,         
  k_exc_pendsv        = 14UL,         
  k_exc_systick       = 15UL,         
  k_nvic_ipr_base     = 0xE000E400UL, 
  k_nvic_ispr_base    = 0xE000E200UL, 
  k_nvic_iser_base    = 0xE000E100UL, 
  k_nvic_icer_base    = 0xE000E180UL, 
  k_nvic_en_words     = 8UL,          
  k_nvic_en_span      = 8UL * 4UL,    
  k_exc_irq_vec0      = 16UL,         
} cortexm_scs_t;
 
/* Armv7E-M / Armv8-M exception model constants (the part Unicorn's Cortex-M33
 * core leaves to software here -- it has no NVIC/exception unit). EXC_RETURN
 * magic values steer the unstack: bit2 picks the return stack (1 = PSP, 0 =
 * MSP), bit3 the return mode (1 = Thread, 0 = Handler), bit4 the frame type
 * (1 = basic 8-word frame, 0 = FP extended frame). On Armv8-M the value also
 * carries bit6 = S (1 = return to Secure, 0 = Non-Secure) and bit5 = DCRS, so a
 * Non-Secure thread return is 0xFFFFFFBC -- NOT one of the Armv7-M 0xFFFFFFF_
 * values. is_exc_return() therefore matches the whole bits[31:7]-set EXC_RETURN
 * prefix (0xFFFFFF80..FF), and exc_enter/exc_return branch on bit4 (FType) to
 * stack/unstack the S0-S15 + FPSCR words whenever an FP extended frame is in
 * play (ThreadX's PendSV mirrors this with its own TST LR,#0x10 on S16-S31). */
typedef enum : uint32_t {
  k_exc_frame_words   = 8U,          
  k_exc_frame_bytes   = 32U,         
  k_exc_ret_v8_mask   = 0xFFFFFF80U, 
  k_exc_ret_ftype     = 0x10U,       
  k_exc_ret_handler   = 0xFFFFFFF1U, 
  k_exc_ret_msp       = 0xFFFFFFF9U, 
  k_exc_ret_psp       = 0xFFFFFFFDU, 
  k_exc_ret_spsel     = 0x4U,        
  k_exc_ret_mode      = 0x8U,        
  k_control_spsel     = 0x2U,        
  k_control_fpca      = 0x4U,        
  k_xpsr_t_bit        = 0x01000000U, 
  k_xpsr_align9       = 0x00000200U, 
  k_xpsr_ipsr_mask    = 0x000001FFU, 
  k_exc_prio_none     = 0x100U,      
  k_exc_prio_max      = 0xFFU,       
  k_exc_nest_max      = 4U,          
  k_byte_bits         = 8U,          
  k_frame_off_r3      = 12U,         
  k_frame_off_lr      = 20U,         
  k_frame_off_pc      = 24U,         
  k_frame_off_xpsr    = 28U,         
  k_fp_frame_extra    = 72U,         
  k_fp_s_words        = 16U,         
  k_frame_off_s0      = 32U,         
  k_frame_off_fpscr   = 96U,         
  k_vector_erased     = 0xFFFFFFFEU, 
  k_nvic_prio_shift   = 4U,          
  k_lo4_mask          = 0xFU,        
  k_armv8m_sg_opcode  = 0xE97FE97FU, 
  k_thumb2_insn_bytes = 4U,          
  k_fpcxtns_push      = 0xCF81ED6DU, 
  k_fpcxtns_pop       = 0xCF81ECFDU, 
  k_word_bytes        = 4U,          
  k_clrm_hw0          = 0xE89FU,     
  k_vscclrm_hw0_s     = 0xEC9FU,     
  k_vscclrm_hw0_d     = 0xECDFU,     
  k_lo16_mask         = 0xFFFFU,     
  k_bkpt_hw_base      = 0xBE00U,     
  k_bkpt_hw_mask      = 0xFF00U,     
  k_thumb_bx_lr       = 0x4770U,     
  k_thumb_hw_bytes    = 2U,          
  k_byte_mask         = 0xFFU,       
} cortexm_exc_t;

uint32_t exc_vector(uc_engine* uc, uint32_t vtor_base, uint32_t exc_num);

void exc_enter(uc_engine* uc, uint32_t exc_num, uint32_t handler);

void exc_return(uc_engine* uc, uint32_t exc_ret);

bool exc_take_pending(uc_engine* uc, uint32_t vtor_base, bool allow_systick);

bool idle_spin_at(uc_engine* uc, uint32_t pc);

void dwt_cyccnt_advance(uc_engine* uc);

void emu_exc_install_core(uc_engine* uc);

void emu_exc_install_scb_nvic(uc_engine* uc);

void emu_exc_arm_systick(void);

bool emu_exc_take_exc_return(uint64_t* out_pc);

void emu_exc_clear_pendsv_stop(void);

bool emu_exc_pendsv_stop(void);

bool emu_exc_bkpt_hit(void);

uint32_t emu_exc_bkpt_pc(void);

bool emu_exc_reboot_requested(void);

void emu_exc_clear_reboot_request(void);

uint32_t emu_exc_systick_fires(void);

uint32_t emu_exc_pendsv_takes(void);

uint32_t emu_exc_svc_takes(void);

void emu_exc_reset(void);
 
#ifdef __cplusplus
}
#endif