27#include <unicorn/unicorn.h>
48typedef enum : uint64_t {
70typedef enum : uint32_t {
91typedef enum : uint32_t {
182uint32_t
decode_escapes(
const char* in, uint8_t* out, uint32_t cap);
uint32_t decode_escapes(const char *in, uint8_t *out, uint32_t cap)
Decode a C-style escaped –input string into a raw byte buffer.
console_cfg_t
Console-UART presentation sizing.
@ k_uart_line_max
Pretty-print line buffer for the [uart] prefix.
void emu_console_reset(void)
Reset the in-flight ITM line (warm-reboot support).
itm_bits_t
ITM enable-bit values and line sizing for the stimulus echo.
@ k_itm_line_max
Max chars buffered before a forced flush.
@ k_itm_tcr_itmena
TCR bit 0: ITM global enable.
@ k_itm_stim_ready
Non-zero STIM0 read = FIFO ready.
@ k_itm_tenr_port0
TENR bit 0: stimulus port 0 enabled.
@ k_sau_type_regs
SAU_TYPE.SREGION: M85 implements 8.
@ k_scb_demcr_trcena
DEMCR bit 24: trace subsystem enable.
void emu_console_install(uc_engine *uc)
Seed ITM "ready" bits and arm the stimulus-port echo hook.
void console_tx_sink(uint8_t channel, uint8_t byte)
SCI TX sink: print each transmitted byte (prefixed line + raw mirror).
itm_addr_t
ITM / debug PPB addresses and TrustZone alias constants.
@ k_sau_type_addr
SAU_TYPE (SREGION = implemented regs).
@ k_itm_tenr_addr
ITM Trace Enable Register (port 0).
@ k_ns_sram2_base
SRAM2 Non-secure alias (bit[28]=1).
@ k_scb_demcr_addr
Debug Exception + Monitor Control.
@ k_itm_tcr_addr
ITM Trace Control Register (ITMENA).
@ k_itm_stim0_addr
ITM stimulus port 0 (byte FIFO).
@ k_ns_alias_bit
IDAU bit[28]: NS alias of a Secure addr.
void console_flush_line(uint8_t channel)
Flush the pending [uart] line to injected output sink with its channel prefix.
Annotation-attribute framework macros for ra8-firmware.