ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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emu_cpu1.h File Reference

Second-core (cpu1, Cortex-M33) engine: release watch, boot, stepping. More...

#include <stdint.h>
#include <unicorn/unicorn.h>
#include "emu_elf.h"
#include "emu_memmap.h"
#include "ra8_attributes.h"
Include dependency graph for emu_cpu1.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Functions

void emu_cpu1_notify_mmio_write (uint64_t mmio_abs, uint64_t value)
 Watch a peripheral MMIO write for the cpu1 release sequence.
void emu_cpu1_init (const emu_elf_source_t *elf, emu_memmap_workspace_t *memory)
 Create the second emulator engine for cpu1, if the image carries one.
void emu_cpu1_close (emu_memmap_workspace_t *memory)
 Detach and close the optional cpu1 engine.
void emu_cpu1_step (void)
 Boot cpu1 on a pending release, then step it one interleave chunk.

Detailed Description

Second-core (cpu1, Cortex-M33) engine: release watch, boot, stepping.

The RA8D2 boots cpu0 (Cortex-M85); the application releases cpu1 (Cortex-M33) by writing CPU1INITVTOR (its vector table) then CPU1ACTCSR.ACTREQ. ra8_emulator emulates cpu1 in a second Unicorn engine that shares the on-chip SRAM with cpu0 (host-backed), so cross-core IPC over shared SRAM actually runs. The MMIO model notifies this module of every peripheral write so the release sequence is captured; the run loop boots and steps the second engine between cpu0 chunks. Inert unless the firmware carries a cpu1 image and asserts ACTREQ.

Split out of the ra8_emulator main translation unit; behaviour unchanged.

Copyright
Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT
Since
0.1.0

Definition in file emu_cpu1.h.

Function Documentation

◆ emu_cpu1_close()

void emu_cpu1_close ( emu_memmap_workspace_t * memory)

Detach and close the optional cpu1 engine.

Parameters
[in,out]memoryBacking supplied to emu_cpu1_init.
Returns
Nothing.
Postcondition
The cpu1 binding no longer participates in publications.
Repeated calls are harmless.
Since
0.1.0

Detach and close the optional cpu1 engine; this step is contained within the emu cpu1 model and uses bounded caller or module-owned storage.

Precondition
Arguments satisfy the ranges documented for emu cpu1 close.
The call executes on the emulator's single owning thread.
Note
The operation is synchronous and does not transfer heap ownership.

Definition at line 183 of file emu_cpu1.c.

References emu_memmap_detach(), s_cpu1_active, s_cpu1_release_req, and s_cpu1_uc.

Referenced by priv_run_cleanup().

◆ emu_cpu1_init()

void emu_cpu1_init ( const emu_elf_source_t * elf,
emu_memmap_workspace_t * memory )

Create the second emulator engine for cpu1, if the image carries one.

Only dual-core firmware (a PT_LOAD segment in the MRAM_CPU1 window) gets a cpu1 engine, so single-core apps pay nothing. The engine maps the same regions as cpu0 but binds the on-chip SRAM (and its NS alias) to the shared authoritative sparse backing so cross-core IPC over shared SRAM is coherent, maps the peripheral windows through the same MMIO model, and loads the full ELF so cpu1 can boot from its own vector table when released. The engine is left idle – emu_cpu1_step() boots it on the CPU1ACTCSR release.

Parameters
[in]elfOpen firmware source carrying cpu0 and optional cpu1 segments.
[in,out]memoryOpen caller-owned backing shared with cpu0.
Returns
Nothing (the engine handle stays module-private).
Precondition
emu_memmap_open() and the cpu0 attach succeeded.
elf is valid and remains open for cpu1 detection and loading.
Postcondition
On a dual-core image a Cortex-M33 engine mirrors cpu0's map with shared SRAM; otherwise no engine exists and stepping is a no-op.
No cpu1 instruction has executed yet (idle until released).
Note
cpu1's PPB / peripheral writes stay private to its engine.
Since
0.1.0

Create the second emulator engine for cpu1, if the image carries one.

Definition at line 178 of file emu_cpu1.c.

References internal_cpu1_engine_init(), and s_cpu1_uc.

Referenced by internal_main_install_run_seams().

◆ emu_cpu1_notify_mmio_write()

void emu_cpu1_notify_mmio_write ( uint64_t mmio_abs,
uint64_t value )

Watch a peripheral MMIO write for the cpu1 release sequence.

Captures CPU1INITVTOR (cpu1's vector-table base) and, on a correctly-keyed CPU1ACTCSR write (HUM Ch 2.9.1.9 "CPU1ACTCSR" p 130: KEY=0xA5 in bits [15:8] plus ACTREQ), latches the release request the run loop consumes. Called by the MMIO write model for every peripheral write; anything but the two CPU_CTRL words is ignored.

Parameters
[in]mmio_absAbsolute peripheral address being written.
[in]valueValue being written.
Returns
Nothing.
Precondition
The MMIO write model dispatches every peripheral write here.
None otherwise.
Postcondition
The vector base / release latch reflect the observed write.
Note
Not thread-safe; the emulator is single-threaded host-side.
See also
emu_cpu1_step() Consumes the release latch.
Since
0.1.0
Postcondition
Ownership of caller-supplied storage is unchanged.

Watch a peripheral MMIO write for the cpu1 release sequence.

Definition at line 68 of file emu_cpu1.c.

References k_cpu1_actcsr_actreq, k_cpu1_actcsr_addr, k_cpu1_actcsr_key, k_cpu1_actcsr_key_mask, k_cpu1_actcsr_key_shift, k_cpu1_initvtor_addr, s_cpu1_initvtor, and s_cpu1_release_req.

Referenced by mmio_write().

◆ emu_cpu1_step()

void emu_cpu1_step ( void )

Boot cpu1 on a pending release, then step it one interleave chunk.

The run loop calls this once per outer chunk. On the latched CPU1ACTCSR release it reads cpu1's SP/PC from the captured CPU1INITVTOR and marks the core active; while active it runs one bounded instruction chunk. cpu1 is a tight poll loop (no interrupts), so a plain stepped run suffices; a cpu1 fault just halts cpu1 (cpu0 keeps running). A no-op without a cpu1 engine.

Returns
Nothing.
Precondition
emu_cpu1_init() ran (engine present or absent as detected).
The run loop is between cpu0 chunks.
Postcondition
cpu1 advanced up to one interleave chunk (or stayed idle/halted).
Note
Not thread-safe; the emulator is single-threaded host-side.
Since
0.1.0
Postcondition
Ownership of caller-supplied storage is unchanged.

Boot cpu1 on a pending release, then step it one interleave chunk.

Definition at line 196 of file emu_cpu1.c.

References k_cpu1_chunk_insns, rd32(), s_cpu1_active, s_cpu1_initvtor, s_cpu1_pc, s_cpu1_release_req, and s_cpu1_uc.

Referenced by internal_run_loop_record().