emu_cpu1.c

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#include "emu_cpu1.h"
 
#include <stdio.h>
#include <string.h>
 
#include "emu_console.h"
#include "emu_elf.h"
#include "emu_engine.h"
#include "emu_host_io_internal.h"
#include "emu_memmap.h"
#include "emu_mmio.h"

typedef enum : uint64_t {
  k_cpu1_initvtor_addr = 0x4000F044UL, 
  k_cpu1_actcsr_addr   = 0x4000F064UL, 
  k_cpu1_mram_base     = 0x020C0000UL, 
  k_cpu1_mram_end      = 0x02100000UL, 
} dual_core_addr_t;
 
typedef enum : uint32_t {
  k_cpu1_actcsr_actreq    = 1U << 0U, 
  k_cpu1_actcsr_key       = 0xA5U,    
  k_cpu1_actcsr_key_shift = 8U,       
  k_cpu1_actcsr_key_mask  = 0xFFU,    
  k_cpu1_chunk_insns      = 100000U,  
} dual_core_bits_t;
 
static uc_engine* s_cpu1_uc;          
static bool       s_cpu1_active;      
static bool       s_cpu1_release_req; 
static uint32_t   s_cpu1_initvtor;    
static uint32_t   s_cpu1_pc;          
 
static uc_engine* s_cpu1_uc;          
static bool       s_cpu1_active;      
static bool       s_cpu1_release_req; 
static uint32_t   s_cpu1_initvtor;    
static uint32_t   s_cpu1_pc;          

void emu_cpu1_notify_mmio_write(uint64_t mmio_abs, uint64_t value)
{
  if (mmio_abs == (uint64_t)k_cpu1_initvtor_addr) {
    s_cpu1_initvtor = (uint32_t)value;
  } else if (mmio_abs == (uint64_t)k_cpu1_actcsr_addr) {
    /* HUM Ch 2.9.1.9 "CPU1ACTCSR" p 130 -- a write is honored only with
     * KEY=0xA5 in bits [15:8]; the firmware writes 0xA501 (KEY | ACTREQ).
     * Model the key gate so a keyless ACTREQ does not release cpu1. */
    const uint32_t key =
      ((uint32_t)value >> (uint32_t)k_cpu1_actcsr_key_shift) & (uint32_t)k_cpu1_actcsr_key_mask;
    if ((key == (uint32_t)k_cpu1_actcsr_key) &&
        (((uint32_t)value & (uint32_t)k_cpu1_actcsr_actreq) != 0U)) {
      s_cpu1_release_req = true;
    }
  }
}

RA8_INTERNAL static bool internal_cpu1_segment(const elf_exec_segment_t* segment, void* opaque)
{
  bool* const present = (bool*)opaque;
  *present =
    (segment->paddr >= (uint32_t)k_cpu1_mram_base) && (segment->paddr < (uint32_t)k_cpu1_mram_end);
  return !*present;
}

RA8_INTERNAL static bool internal_cpu1_image_present(const emu_elf_source_t* elf)
{
  bool present = false;
  (void)elf_foreach_load_segment(elf, internal_cpu1_segment, &present);
  return present;
}

RA8_INTERNAL static uc_engine* internal_cpu1_engine_init(const emu_elf_source_t* elf,
                                                         emu_memmap_workspace_t* memory)
{
  if (!internal_cpu1_image_present(elf)) {
    return nullptr; /* single-core firmware -- no second engine. */
  }
  uc_engine* c1 = nullptr;
  if (uc_open(UC_ARCH_ARM, (uc_mode)(UC_MODE_THUMB | UC_MODE_MCLASS), &c1) != UC_ERR_OK) {
    return nullptr;
  }
  (void)uc_ctl_set_cpu_model(c1, UC_CPU_ARM_CORTEX_M33);
  if ((emu_memmap_attach(memory, c1).status != k_emu_memmap_ok) || (load_elf(c1, elf) != 0)) {
    (void)emu_memmap_detach(memory, c1);
    (void)uc_close(c1);
    return nullptr;
  }
  (void)priv_emu_io_errf("  cpu1 engine   : Cortex-M33, shared SRAM + peripherals (dual-core)\n");
  return c1;
}

void emu_cpu1_init(const emu_elf_source_t* elf, emu_memmap_workspace_t* memory)
{
  s_cpu1_uc = internal_cpu1_engine_init(elf, memory);
}
 
void emu_cpu1_close(emu_memmap_workspace_t* memory)
{
  if (s_cpu1_uc != nullptr) {
    (void)emu_memmap_detach(memory, s_cpu1_uc);
    (void)uc_close(s_cpu1_uc);
    s_cpu1_uc = nullptr;
  }
  s_cpu1_active      = false;
  s_cpu1_release_req = false;
}

void emu_cpu1_step(void)
{
  if (s_cpu1_uc == nullptr) {
    return;
  }
  if (s_cpu1_release_req && !s_cpu1_active) {
    s_cpu1_release_req     = false;
    const uint32_t cpu1_sp = rd32(s_cpu1_uc, (uint64_t)s_cpu1_initvtor);
    s_cpu1_pc              = rd32(s_cpu1_uc, (uint64_t)s_cpu1_initvtor + 4U);
    (void)uc_reg_write(s_cpu1_uc, UC_ARM_REG_SP, &cpu1_sp);
    s_cpu1_active = true;
  }
  if (s_cpu1_active) {
    const uc_err e1 =
      uc_emu_start(s_cpu1_uc, (uint64_t)s_cpu1_pc | 1U, 0, 0, (size_t)k_cpu1_chunk_insns);
    (void)uc_reg_read(s_cpu1_uc, UC_ARM_REG_PC, &s_cpu1_pc);
    if (e1 != UC_ERR_OK) {
      s_cpu1_active = false; /* cpu1 hit a fault -- halt it, cpu0 continues */
    }
  }
}