131 return s->
level[hs_idx] != 0U;
134 if (s->
level[i] != 0U) {
195 if (pre ==
nullptr || mid ==
nullptr || post ==
nullptr) {
350 if (st ==
nullptr || hs_idx ==
nullptr) {
369 bool decoded =
false;
Shared contract for the EK-RA8D2 <-> ESP32-C6 esp-hosted SPI probe.
@ k_c6_sb_count
Side-band pin count.
void c6_probe_vote(const c6_sideband_sample_t *pre, const c6_sideband_sample_t *mid, const c6_sideband_sample_t *post, c6_probe_stats_t *st)
Fold one transaction's three samples into the classification votes.
@ k_c6_probe_gap_ms
Gap between transactions.
@ k_c6_probe_settle_ms
Post-transfer side-band settle.
@ k_c6_probe_sck_hz
Conservative first-light SCK rate.
@ k_c6_probe_cs_hold_ms
Chip-select setup / hold.
void c6_probe_puts(const char *text)
Emit a bounded, NUL-terminated ASCII literal on the console.
void c6_probe_put_u32(uint32_t value)
Emit an unsigned integer in decimal.
void c6_probe_sample_sideband(c6_sideband_sample_t *out)
Read every Pmod1 side-band pin into one sample.
void c6_probe_print_sideband(const char *label, const c6_sideband_sample_t *s)
Print a labelled side-band sample as label P006=1 P402=0 ....
@ k_c6_probe_hs_poll_ms
Delay between handshake polls.
@ k_c6_probe_min_votes
Votes required to claim a mapping.
@ k_c6_probe_xfer_per_mode
Transactions attempted per SPI mode.
@ k_c6_probe_hs_poll_max
Handshake polls before giving up.
uint8_t c6_probe_best(const uint32_t *votes, uint8_t ignore, uint32_t min_votes)
Pick the side-band pin that won the vote outright, or report none.
void c6_probe_decode_header(const uint8_t *buf, c6_hdr_t *out)
Unpack the twelve-byte esp-hosted payload header.
void c6_probe_print_header(const c6_hdr_t *h)
Print the decoded header fields on one console line.
@ k_c6_hdr_off_iface
if_type[3:0] | if_num[7:4].
void c6_probe_dump_payload(const uint8_t *buf, uint16_t len)
Hex-dump the leading payload bytes of a received frame.
@ k_c6_proto_buf_size
Bytes clocked per transaction.
@ k_c6_proto_hdr_size
sizeof(struct esp_payload_header).
c6_frame_kind_t
Classification of one received 1600-byte transaction.
@ k_c6_frame_data
Real frame, checksum verified.
@ k_c6_frame_bad_csum
Header shape sane, checksum mismatched.
@ k_c6_frame_garbage
No recognisable esp-hosted structure.
@ k_c6_frame_idle
The C6's idle filler frame.
c6_frame_kind_t c6_probe_classify(const c6_hdr_t *h)
Judge a decoded header against the upstream receive rules.
@ k_c6_if_max
Idle filler marker.
ra8_err_t c6_probe_spi_pins_init(void)
Route the Pmod1 SPI pins to SCI2 and own the chip-select as GPIO.
static void internal_fill_idle_tx(void)
Stamp the transmit buffer as an esp-hosted idle host frame.
static void internal_cs(ra8_level_t level)
Drive the chip-select and let the line settle.
static bool internal_sample_ready(const c6_sideband_sample_t *s, uint8_t hs_idx)
Decide whether one side-band sample says the C6 is ready.
static c6_frame_kind_t internal_report_frame(c6_probe_stats_t *st)
Decode, classify, tally and narrate the frame in the receive buffer.
bool c6_probe_sweep_mode(ra8_spi_mode_t mode, uint32_t pclka_hz, c6_probe_stats_t *st, uint8_t *hs_idx)
Run the transaction burst for one SPI mode.
static c6_frame_kind_t internal_one_xfer(uint32_t index, uint8_t hs_idx, c6_probe_stats_t *st)
Clock one transaction and report everything it revealed.
static ra8_err_t internal_transfer(c6_sideband_sample_t *pre, c6_sideband_sample_t *mid, c6_sideband_sample_t *post)
Clock one full esp-hosted transaction, sampling the side-band pins.
static uint8_t s_c6_tx[k_c6_proto_buf_size]
Transmit buffer: one full esp-hosted SPI transaction.
static bool internal_wait_ready(uint8_t hs_idx)
Wait, with a bounded poll, for the peripheral-ready condition.
static uint8_t s_c6_rx[k_c6_proto_buf_size]
Receive buffer: one full esp-hosted SPI transaction.
Board-support layer for the Renesas EK-RA8D2 v1 evaluation kit.
@ k_ra8_board_pmod1_sci_channel
Pmod1 (J26) Simple-SPI is SCI2.
@ k_ra8_board_pmod1_spi_copi
Pmod1.2 COPI (MOSI2/TXD2 per UM),P801.
@ k_ra8_board_pmod1_spi_sck
Pmod1.4 SCK (SCK2), P803.
@ k_ra8_board_pmod1_spi_cs
Pmod1.1 CS (SS2/IRQ14), P804.
@ k_ra8_board_pmod1_spi_cipo
Pmod1.3 CIPO (MISO2/RXD2 per UM),P802.
Error Code Definitions for ra8-firmware.
@ k_ra8_ok
Success – operation completed with all postconditions satisfied.
@ k_ra8_err_null_ptr
Pointer was NULL where a valid pointer was required.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
@ k_ra8_psel_sci_async
00100b: SCI async serial (UART).
ra8_port_pin_t
Packed (port << 8) | pin pin identifier.
ra8_level_t
Digital output / input level.
@ k_ra8_level_high
Drive or read 1.
@ k_ra8_level_low
Drive or read 0.
High-level GPIO helpers on top of the PORT + PFS register layer.
ra8_err_t ra8_gpio_output_init(ra8_port_pin_t pin, ra8_level_t init_level)
Configure a pin as a digital output and drive it to an initial level.
ra8_err_t ra8_gpio_write(ra8_port_pin_t pin, ra8_level_t level)
Drive a previously-configured output to the given level.
ra8_err_t ra8_pfs_route_peripheral(ra8_port_pin_t pin, ra8_psel_t psel, const char *owner)
Route a pin to a non-IRQ peripheral function via PFS.PSEL.
SCI Simple-SPI controller-mode driver (polling, full-duplex).
ra8_err_t ra8_sci_spi_xfer(uint8_t channel, const uint8_t *tx, uint8_t *rx, uint32_t len)
Full-duplex multi-byte transfer.
ra8_err_t ra8_sci_spi_init(uint8_t channel, const ra8_sci_spi_cfg_t *cfg)
Bring an SCI channel up as a Simple-SPI controller.
ra8_err_t ra8_sci_spi_deinit(uint8_t channel)
Disable the channel and release its MSTP gate.
SPI_B controller driver (RA8D2 Type-B SPI peripheral).
ra8_spi_mode_t
CPOL / CPHA combinations.
SysTick-based tick counter, delay and timestamp helpers.
void ra8_delay_ms(uint32_t ms)
Busy-wait for at least ms milliseconds.
Decoded esp-hosted payload header plus the locally recomputed sum.
uint16_t len
Payload length claimed by the sender.
Running evidence gathered across every transaction.
uint32_t hs_vote[k_c6_sb_count]
Pin dropped while CS was asserted.
uint32_t attempts
Transactions clocked.
uint32_t idle_frames
Idle filler frames decoded.
uint32_t data_frames
Real frames with a good checksum.
uint32_t bad_csum_frames
Sane shape, checksum mismatched.
One simultaneous reading of every side-band pin.
uint8_t level[k_c6_sb_count]
Per-pin logic level (0 or 1).
Configuration descriptor for ra8_sci_spi_init.