board_periph_i2c.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_console.h"
#include "board_periph.h"
#include "board_periph_block.h"
#include "board_periph_i2c_internal.h"
#include "emu_host_io_internal.h"

typedef enum : uint64_t {
  k_i3c_base        = 0x4035F000UL,  
  k_i3c_span        = 0x214UL,       
  k_i3c_off_msdvad  = 0x018UL,       
  k_i3c_off_cndctl  = 0x140UL,       
  k_i3c_off_ntdtbp0 = 0x158UL,       
  k_i3c_off_bst     = 0x1D0UL,       
  k_i3c_off_ntst    = 0x1E0UL,       
  k_i3c_off_bcst    = 0x210UL,       
  k_i3c_reg_words   = 0x214UL / 4UL, 
} i3c_map_t;

typedef enum : uint32_t {
  k_i3c_cndctl_stcnd = 0x00000001U, 
  k_i3c_cndctl_srcnd = 0x00000002U, 
  k_i3c_cndctl_spcnd = 0x00000004U, 
} i3c_cndctl_bit_t;

typedef enum : uint32_t {
  k_i3c_bst_stcnddf = 0x00000001U, 
  k_i3c_bst_spcnddf = 0x00000002U, 
  k_i3c_bst_nackdf  = 0x00000010U, 
  k_i3c_bst_tendf   = 0x00000100U, 
  k_i3c_bst_alf     = 0x00010000U, 
  k_i3c_bst_todf    = 0x00100000U, 
} i3c_bst_bit_t;

typedef enum : uint32_t {
  k_i3c_ntst_tdbef0 = 0x00000001U, 
  k_i3c_ntst_rdbff0 = 0x00000002U, 
} i3c_ntst_bit_t;

typedef enum : uint32_t {
  k_i3c_bcst_bfref = 0x00000001U, 
} i3c_bcst_bit_t;

typedef enum : uint32_t {
  k_i3c_addr_shift = 1U,    
  k_i3c_addr_rnw   = 0x01U, 
  k_i3c_addr_mask7 = 0x7FU, 
  k_i3c_byte_mask  = 0xFFU, 
  k_i3c_dev_rx_max = 64U,   
  k_i3c_dev_max    = 4U,    
} i3c_addr_t;

typedef enum : uint8_t {
  k_i3c_periph_idle     = 0U, 
  k_i3c_periph_rx_armed = 1U, 
  k_i3c_periph_tx_armed = 2U, 
} i3c_periph_phase_t;

typedef enum : uint32_t {
  k_i3c_periph_seed = 0xA5U, 
  k_i3c_periph_step = 0x11U, 
} i3c_periph_stim_t;

typedef enum : uint16_t {
  k_gt911_reg_command = 0x8040U, 
  k_gt911_reg_product = 0x8140U, 
  k_gt911_reg_status  = 0x814EU, 
  k_gt911_reg_point0  = 0x814FU, 
} gt911_reg_t;

typedef enum : uint32_t {
  k_gt911_addr_7b      = 0x5DU, 
  k_gt911_id0          = 0x39U, 
  k_gt911_id1          = 0x31U, 
  k_gt911_id2          = 0x31U, 
  k_gt911_id3          = 0x00U, 
  k_gt911_status_ready = 0x80U, 
  k_gt911_status_one   = 0x01U, 
  k_gt911_id_bytes     = 4U,    
  k_gt911_point_bytes  = 8U,    
  k_gt911_ptr_bytes    = 2U,    
  k_gt911_press        = 0x20U, 
  k_gt911_seq_max      = 8U,    
} gt911_const_t;

typedef enum : uint32_t {
  k_gt911_pt_track  = 0U, 
  k_gt911_pt_x_lsb  = 1U, 
  k_gt911_pt_x_msb  = 2U, 
  k_gt911_pt_y_lsb  = 3U, 
  k_gt911_pt_y_msb  = 4U, 
  k_gt911_pt_sz_lsb = 5U, 
} gt911_pt_off_t;

typedef struct {
  uint32_t reg[k_i3c_reg_words]; 
  bool     busy;                 
  bool     addr_done;            
  bool     acked;                
  bool     reading;              
  uint8_t  target_7b;            
  uint32_t ntst;                 
  uint32_t bst;                  
  uint8_t  rx[k_i3c_dev_rx_max]; 
  uint32_t rx_len;               
  uint32_t rx_pos;               
  bool     rx_primed;            
  /* Target (peripheral) mode: the model is the EXTERNAL controller. */
  bool     periph_mode;     
  uint8_t  periph_addr_7b;  
  uint8_t  periph_phase;    
  uint8_t  periph_rx_byte;  
  uint32_t periph_xfers;    
  bool     periph_echo_bad; 
} i3c_state_t;

typedef struct {
  uint16_t reg_ptr;                
  uint8_t  ptr_bytes;              
  bool     click_pending;          
  uint16_t click_x;                
  uint16_t click_y;                
  uint32_t reported;               
  uint16_t seq_x[k_gt911_seq_max]; 
  uint16_t seq_y[k_gt911_seq_max]; 
  uint8_t  seq_len;                
  uint8_t  seq_pos;                
} gt911_state_t;
 
/* =============================================================================
 * I2C bus device registry -- map a 7-bit address to a device model.
 * =============================================================================
 */

typedef struct {
  bool    present;                                         
  uint8_t addr_7b;                                         
  void (*write)(void* ctx, uint8_t byte);                  
  uint32_t (*read)(void* ctx, uint8_t* buf, uint32_t max); 
  void (*stop)(void* ctx);                                 
  void* ctx;                                               
} i2c_device_t;
 
static i3c_state_t   s_i3c;
static i2c_device_t  s_i2c_dev[k_i3c_dev_max];
static gt911_state_t s_gt911;

RA8_INTERNAL static i2c_device_t* internal_i2c_device_find(uint8_t addr_7b)
{
  for (uint32_t i = 0U; i < (uint32_t)k_i3c_dev_max; i++) {
    if (s_i2c_dev[i].present && (s_i2c_dev[i].addr_7b == addr_7b)) {
      return &s_i2c_dev[i];
    }
  }
  return nullptr;
}

void priv_i2c_device_register(uint8_t addr_7b,
                              void (*wr)(void*, uint8_t),
                              uint32_t (*rd)(void*, uint8_t*, uint32_t),
                              void (*stop)(void*),
                              void* ctx)
{
  for (uint32_t i = 0U; i < (uint32_t)k_i3c_dev_max; i++) {
    if (!s_i2c_dev[i].present) {
      s_i2c_dev[i] = (i2c_device_t){.present = true,
                                    .addr_7b = addr_7b,
                                    .write   = wr,
                                    .read    = rd,
                                    .stop    = stop,
                                    .ctx     = ctx};
      return;
    }
  }
}
 
/* =============================================================================
 * GT911 touch device model -- 16-bit register pointer, product id, touch frame.
 * =============================================================================
 */
 
void board_periph_touch_inject(uint16_t x, uint16_t y)
{
  s_gt911.click_x       = x;
  s_gt911.click_y       = y;
  s_gt911.click_pending = true;
}
 
void board_periph_touch_seq_reset(void)
{
  s_gt911.seq_len       = 0U;
  s_gt911.seq_pos       = 0U;
  s_gt911.click_pending = false;
}
 
bool board_periph_touch_seq_push(uint16_t x, uint16_t y)
{
  if (s_gt911.seq_len >= (uint8_t)k_gt911_seq_max) {
    return false;
  }
  s_gt911.seq_x[s_gt911.seq_len] = x;
  s_gt911.seq_y[s_gt911.seq_len] = y;
  s_gt911.seq_len++;
  return true;
}

RA8_INTERNAL static void internal_gt911_arm_next_from_seq(gt911_state_t* g)
{
  if (!g->click_pending && (g->seq_pos < g->seq_len)) {
    g->click_x       = g->seq_x[g->seq_pos];
    g->click_y       = g->seq_y[g->seq_pos];
    g->click_pending = true;
    g->seq_pos++;
  }
}
 
uint32_t board_periph_touch_reported(void)
{
  return s_gt911.reported;
}
 
bool board_periph_touch_last(uint16_t* x, uint16_t* y)
{
  if ((x == nullptr) || (y == nullptr) || (s_gt911.reported == 0U)) {
    return false;
  }
  *x = s_gt911.click_x;
  *y = s_gt911.click_y;
  return true;
}

RA8_INTERNAL static void internal_gt911_write(void* ctx, uint8_t byte)
{
  gt911_state_t* g = (gt911_state_t*)ctx;
  if (g->ptr_bytes < (uint8_t)k_gt911_ptr_bytes) {
    /* 16-bit pointer arrives MSB first: byte 0 is the high byte, byte 1 the low. */
    g->reg_ptr = (uint16_t)(((uint32_t)g->reg_ptr << 8U) | (uint32_t)byte);
    g->ptr_bytes++;
    return;
  }
  /* Payload after the pointer: a 0 written to STATUS acks the current frame so
   * the IC can latch the next one (ra8_touch's priv_ack_frame). */
  if ((g->reg_ptr == (uint16_t)k_gt911_reg_status) && (byte == 0U)) {
    g->click_pending = false;
  }
  if (g->reg_ptr == (uint16_t)k_gt911_reg_command) {
    /* Wake / soft-reset commands are accepted (no observable side effect). */
  }
}

RA8_INTERNAL static uint32_t internal_gt911_read_status(gt911_state_t* g, uint8_t* buf)
{
  /* Auto-arm the next queued raw point (multi-tap sequence path) so a status
   * read reports buffer-ready while the FIFO is non-empty. A single-shot
   * --click (seq_len == 0) is unaffected: the arm is a no-op and the directly
   * injected contact still reports ready on its own. */
  internal_gt911_arm_next_from_seq(g);
  buf[0] = g->click_pending ? (uint8_t)(k_gt911_status_ready | k_gt911_status_one) : 0U;
  return 1U;
}

RA8_INTERNAL static uint32_t
internal_gt911_read_point0(gt911_state_t* g, uint8_t* buf, uint32_t max)
{
  if (max < (uint32_t)k_gt911_point_bytes) {
    return 0U;
  }
  for (uint32_t i = 0U; i < (uint32_t)k_gt911_point_bytes; i++) {
    buf[i] = 0U;
  }
  buf[k_gt911_pt_track]  = 0U;
  buf[k_gt911_pt_x_lsb]  = (uint8_t)(g->click_x & (uint16_t)k_i3c_byte_mask);
  buf[k_gt911_pt_x_msb]  = (uint8_t)((uint32_t)g->click_x >> 8U);
  buf[k_gt911_pt_y_lsb]  = (uint8_t)(g->click_y & (uint16_t)k_i3c_byte_mask);
  buf[k_gt911_pt_y_msb]  = (uint8_t)((uint32_t)g->click_y >> 8U);
  buf[k_gt911_pt_sz_lsb] = (uint8_t)k_gt911_press;
  /* The coordinate has now been delivered to the firmware -- count it and drop
   * the contact so the next frame reads "not ready", exactly as the GT911 does
   * once a tap is drained. */
  g->click_pending = false;
  g->reported++;
  return (uint32_t)k_gt911_point_bytes;
}

RA8_INTERNAL static uint32_t internal_gt911_read(void* ctx, uint8_t* buf, uint32_t max)
{
  gt911_state_t* g = (gt911_state_t*)ctx;
  if (g->reg_ptr == (uint16_t)k_gt911_reg_product) {
    const uint8_t  id[k_gt911_id_bytes] = {(uint8_t)k_gt911_id0,
                                           (uint8_t)k_gt911_id1,
                                           (uint8_t)k_gt911_id2,
                                           (uint8_t)k_gt911_id3};
    const uint32_t n = (max < (uint32_t)k_gt911_id_bytes) ? max : (uint32_t)k_gt911_id_bytes;
    for (uint32_t i = 0U; i < n; i++) {
      buf[i] = id[i];
    }
    return n;
  }
  if (g->reg_ptr == (uint16_t)k_gt911_reg_status) {
    return internal_gt911_read_status(g, buf);
  }
  if (g->reg_ptr == (uint16_t)k_gt911_reg_point0) {
    return internal_gt911_read_point0(g, buf, max);
  }
  return 0U;
}

RA8_INTERNAL static void internal_gt911_stop(void* ctx)
{
  gt911_state_t* g = (gt911_state_t*)ctx;
  g->ptr_bytes     = 0U;
}
 
/* =============================================================================
 * LSM6DSO IMU device model -- 8-bit auto-incrementing register file.
 * =============================================================================
 */
 
/* =============================================================================
 * I3C-in-I2C-mode (IIC_B) controller model -- the transfer state machine the
 * ra8_i3c_i2c.c polling driver drives (START / addr / write / read / STOP).
 * =============================================================================
 */

RA8_INTERNAL static uint32_t internal_i3c_word(uint64_t off)
{
  return (uint32_t)(off / 4U);
}

RA8_INTERNAL static void internal_i3c_open_transfer(void)
{
  s_i3c.busy      = true;
  s_i3c.addr_done = false;
  s_i3c.acked     = false;
  s_i3c.reading   = false;
  s_i3c.rx_len    = 0U;
  s_i3c.rx_pos    = 0U;
  s_i3c.rx_primed = false;
  /* TX buffer is empty so the driver can write the address byte; clear stale
   * NACK/TEND so the new address phase reports its own outcome. */
  s_i3c.ntst = (uint32_t)k_i3c_ntst_tdbef0;
  s_i3c.bst &= ~((uint32_t)k_i3c_bst_nackdf | (uint32_t)k_i3c_bst_tendf);
}

typedef enum : uint32_t {
  k_i2c_console_line_cap = 48U, 
} i2c_console_t;

RA8_INTERNAL static void internal_i3c_close_transfer(void)
{
  if (s_i3c.acked) {
    i2c_device_t* dev = internal_i2c_device_find(s_i3c.target_7b);
    if (dev != nullptr) {
      if (dev->stop != nullptr) {
        dev->stop(dev->ctx);
      }
    }
    /* Console I2C tab: one line per completed (ACKed) transaction at STOP --
     * 7-bit address + R/W + read byte count. Bounded to one push per STOP. */
    char ln[k_i2c_console_line_cap];
    if (s_i3c.reading) {
      (void)snprintf(ln,
                     sizeof(ln),
                     "IIC addr=0x%02X R %uB",
                     (unsigned)s_i3c.target_7b,
                     (unsigned)s_i3c.rx_len);
    } else {
      (void)snprintf(ln, sizeof(ln), "IIC addr=0x%02X W", (unsigned)s_i3c.target_7b);
    }
    board_console_push(k_board_console_ch_i2c, ln);
  }
  s_i3c.busy      = false;
  s_i3c.addr_done = false;
  s_i3c.ntst      = (uint32_t)k_i3c_ntst_tdbef0;
}

RA8_INTERNAL static void internal_i3c_address_phase(uint8_t address_byte)
{
  s_i3c.target_7b =
    (uint8_t)((uint32_t)address_byte >> (uint32_t)k_i3c_addr_shift) & (uint8_t)k_i3c_addr_mask7;
  s_i3c.reading   = ((uint32_t)address_byte & (uint32_t)k_i3c_addr_rnw) != 0U;
  s_i3c.addr_done = true;
 
  i2c_device_t* dev = internal_i2c_device_find(s_i3c.target_7b);
  if (dev == nullptr) {
    /* No device at this address: NACK the address (scan reports ack=0). */
    s_i3c.acked = false;
    s_i3c.bst |= (uint32_t)k_i3c_bst_nackdf;
    return;
  }
  s_i3c.acked = true;
  s_i3c.bst |= (uint32_t)k_i3c_bst_tendf; /* address ACKed -> scan sees TENDF */
  if (s_i3c.reading) {
    /* Pre-fetch the device's response for this read so NTDTBP0 reads serve it. */
    s_i3c.rx_len    = dev->read(dev->ctx, s_i3c.rx, (uint32_t)k_i3c_dev_rx_max);
    s_i3c.rx_pos    = 0U;
    s_i3c.rx_primed = false;
    s_i3c.ntst |= (uint32_t)k_i3c_ntst_rdbff0; /* RX data ready */
  } else {
    s_i3c.ntst |= (uint32_t)k_i3c_ntst_tdbef0; /* ready for the first data byte */
  }
}
 
/* =============================================================================
 * Target (peripheral) mode -- the model plays the EXTERNAL I2C controller that
 * drives the firmware's IIC_B target (i3c_i2c_peripheral_demo). The firmware
 * polls NTST and moves bytes through NTDTBP0; the controller path here is idle
 * (the firmware issues no CNDCTL START), so these handlers own NTST/NTDTBP0 for
 * the channel whenever target mode is active. See ::i3c_periph_phase_t.
 * =============================================================================
 */

RA8_INTERNAL static void internal_i3c_periph_open(uint32_t msdvad)
{
  const uint8_t addr =
    (uint8_t)(((uint32_t)msdvad >> (uint32_t)k_i3c_addr_shift) & (uint32_t)k_i3c_addr_mask7);
  s_i3c.periph_addr_7b = addr;
  s_i3c.periph_mode    = (addr != 0U); /* MSDVAD == 0 (close) leaves target mode. */
  s_i3c.periph_phase   = (uint8_t)k_i3c_periph_idle;
}

RA8_INTERNAL static uint32_t internal_i3c_periph_ntst(void)
{
  if (s_i3c.periph_phase == (uint8_t)k_i3c_periph_idle) {
    s_i3c.periph_rx_byte =
      (uint8_t)(((uint32_t)k_i3c_periph_seed + (s_i3c.periph_xfers * (uint32_t)k_i3c_periph_step)) &
                (uint32_t)k_i3c_byte_mask);
    s_i3c.periph_phase = (uint8_t)k_i3c_periph_rx_armed;
  }
  if (s_i3c.periph_phase == (uint8_t)k_i3c_periph_rx_armed) {
    return (uint32_t)k_i3c_ntst_rdbff0; /* controller-written byte is waiting */
  }
  return (uint32_t)k_i3c_ntst_tdbef0; /* tx_armed: controller is reading the echo */
}

RA8_INTERNAL static uint32_t internal_i3c_periph_rx_read(void)
{
  s_i3c.periph_phase = (uint8_t)k_i3c_periph_tx_armed;
  return (uint32_t)s_i3c.periph_rx_byte;
}

RA8_INTERNAL static void internal_i3c_periph_tx_write(uint8_t byte)
{
  if (byte != s_i3c.periph_rx_byte) {
    s_i3c.periph_echo_bad = true;
  }
  s_i3c.periph_xfers++;
  s_i3c.periph_phase = (uint8_t)k_i3c_periph_idle;
}

RA8_INTERNAL static void internal_i3c_ntdtbp0_write(uint32_t value)
{
  const uint8_t byte = (uint8_t)(value & (uint32_t)k_i3c_byte_mask);
  if (s_i3c.periph_mode) {
    /* Target mode: the firmware is the peripheral pushing its echo byte. */
    internal_i3c_periph_tx_write(byte);
    return;
  }
  if (!s_i3c.addr_done) {
    internal_i3c_address_phase(byte);
    return;
  }
  if (!s_i3c.acked) {
    return; /* NACKed address: swallow further writes until STOP */
  }
  i2c_device_t* dev = internal_i2c_device_find(s_i3c.target_7b);
  if ((dev != nullptr) && (dev->write != nullptr)) {
    dev->write(dev->ctx, byte);
  }
  s_i3c.ntst |= (uint32_t)k_i3c_ntst_tdbef0; /* buffer empty again for the next */
}

RA8_INTERNAL static uint32_t internal_i3c_ntdtbp0_read(void)
{
  if (s_i3c.periph_mode) {
    /* Target mode: the firmware is the peripheral draining the written byte. */
    return internal_i3c_periph_rx_read();
  }
  if (!s_i3c.rx_primed) {
    /* FSP's controller RXI handler drops the first RDBFF0 read before real payload. */
    s_i3c.rx_primed = true;
    return 0U;
  }
  uint8_t b = 0U;
  if (s_i3c.rx_pos < s_i3c.rx_len) {
    b = s_i3c.rx[s_i3c.rx_pos];
    s_i3c.rx_pos++;
  }
  s_i3c.ntst |= (uint32_t)k_i3c_ntst_rdbff0; /* keep RX-ready for the next byte */
  return (uint32_t)b;
}

RA8_INTERNAL static void internal_i3c_cndctl_write(uint32_t value)
{
  if ((value & ((uint32_t)k_i3c_cndctl_stcnd | (uint32_t)k_i3c_cndctl_srcnd)) != 0U) {
    internal_i3c_open_transfer();
  } else if ((value & (uint32_t)k_i3c_cndctl_spcnd) != 0U) {
    internal_i3c_close_transfer();
  }
}

RA8_INTERNAL static uint64_t internal_i3c_reg_read(uint64_t off)
{
  if (off == (uint64_t)k_i3c_off_ntst) {
    if (s_i3c.periph_mode) {
      return internal_i3c_periph_ntst();
    }
    return s_i3c.ntst;
  }
  if (off == (uint64_t)k_i3c_off_bst) {
    return s_i3c.bst;
  }
  if (off == (uint64_t)k_i3c_off_bcst) {
    /* BFREF: 1 when the bus is free. The driver gates new transactions on it. */
    return s_i3c.busy ? 0U : (uint32_t)k_i3c_bcst_bfref;
  }
  if (off == (uint64_t)k_i3c_off_ntdtbp0) {
    return internal_i3c_ntdtbp0_read();
  }
  return s_i3c.reg[internal_i3c_word(off)]; /* reflect every other register */
}

RA8_INTERNAL static void internal_i3c_reg_write(uint64_t off, uint32_t value)
{
  s_i3c.reg[internal_i3c_word(off)] = value; /* shadow keeps "configure then verify" working */
  if (off == (uint64_t)k_i3c_off_msdvad) {
    /* Own-address programming = the firmware is coming up as an addressed
     * target. The controller path never writes MSDVAD, so this cleanly selects
     * target mode (the external-controller stimulus in i3c_periph_*). */
    internal_i3c_periph_open(value);
  } else if (off == (uint64_t)k_i3c_off_cndctl) {
    internal_i3c_cndctl_write(value);
  } else if (off == (uint64_t)k_i3c_off_ntdtbp0) {
    internal_i3c_ntdtbp0_write(value);
  } else if (off == (uint64_t)k_i3c_off_bst) {
    /* BST condition / fault flags are write-0-to-clear: keep only bits still
     * written as 1 (the driver clears by reading then masking the bit out). */
    s_i3c.bst &= value;
  }
}

RA8_INTERNAL static uint64_t internal_i3c_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)size;
  return internal_i3c_reg_read(addr - (uint64_t)k_i3c_base);
}

RA8_INTERNAL static void
internal_i3c_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)uc;
  (void)size;
  internal_i3c_reg_write(addr - (uint64_t)k_i3c_base, (uint32_t)value);
}

RA8_INTERNAL static void internal_i3c_reset(void)
{
  s_i3c   = (i3c_state_t){};
  s_gt911 = (gt911_state_t){};
  priv_board_i2c_imu_fuel_reset(); /* lay the IMU + fuel-gauge register files (CLI-set SOC) */
  /* Populate the modelled I2C bus: the EK-RA8D2 carrier's GT911 touch
   * controller answers at its default 7-bit address on I3C/IIC_B channel 0, so
   * the firmware's real ra8_touch -> ra8_i3c_transfer -> GT911 path returns data
   * instead of needing a function-level touch stub. The LSM6DSO IMU answers at
   * 0x6B so imu_lsm6dso_demo's WHO_AM_I probe + sample reads succeed too. */
  for (uint32_t i = 0U; i < (uint32_t)k_i3c_dev_max; i++) {
    s_i2c_dev[i] = (i2c_device_t){};
  }
  priv_i2c_device_register((uint8_t)k_gt911_addr_7b,
                           internal_gt911_write,
                           internal_gt911_read,
                           internal_gt911_stop,
                           &s_gt911);
  /* LSM6DSO IMU at 0x6B + MAX17048-class fuel gauge at 0x36 (battery SOC +
   * charge direction) register themselves from the devices TU. */
  priv_board_i2c_imu_fuel_register();
}

RA8_INTERNAL static void internal_i3c_report(void)
{
  if (s_gt911.reported > 0U) {
    (void)priv_emu_io_errf("  I3C/I2C GT911 : %u touch frame(s) drained via ra8_touch -> I3C\n",
                           s_gt911.reported);
  }
  if (priv_board_i2c_imu_reads() > 0U) {
    (void)priv_emu_io_errf("  I3C/I2C LSM6DSO: %u register read(s) answered (WHO_AM_I + samples)\n",
                           priv_board_i2c_imu_reads());
  }
  if (s_i3c.periph_mode) {
    /* Target mode: report how many controller write+read round-trips the
     * firmware's IIC_B peripheral accepted, and whether every byte it echoed
     * back matched the byte the synthetic controller wrote. */
    const bool echo_ok = (s_i3c.periph_xfers > 0U) && !s_i3c.periph_echo_bad;
    (void)priv_emu_io_errf(
      "  I3C/I2C target: addr=0x%02X %u peripheral write+read xfer(s) accepted,"
      " echo=%s\n",
      (unsigned)s_i3c.periph_addr_7b,
      (unsigned)s_i3c.periph_xfers,
      echo_ok ? "Y" : "N");
  }
}

static const board_periph_block_t s_k_i3c_block = {
  .base   = (uint64_t)k_i3c_base,
  .span   = (uint64_t)k_i3c_span,
  .order  = (uint32_t)k_block_order_i2c,
  .read   = internal_i3c_read,
  .write  = internal_i3c_write,
  .tick   = nullptr,
  .reset  = internal_i3c_reset,
  .report = internal_i3c_report,
  .name   = "I3C/I2C+GT911",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_board_periph_i2c_register(void)
{
  board_periph_register_block(&s_k_i3c_block);
}