board_periph_gptp.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_periph_block.h"
#include "emu_host_io_internal.h"
#include "ra8_ether_regs.h"

typedef enum : uint64_t {
  k_gptp_win_base = (uint64_t)k_ra8_gptp_base_addr, 
  k_gptp_win_span = 0x1000UL,                       
} gptp_win_geom_t;

typedef enum : uint32_t {
  k_gptp_block_order = 59U, 
} gptp_order_t;

typedef enum : uint64_t {
  k_gptp_eswclk_hz    = 250000000ULL,      
  k_gptp_tick_hz      = 1000ULL,           
  k_gptp_clk_per_tick = 250000ULL,         
  k_gptp_subns_shift  = 27ULL,             
  k_gptp_ns_per_sec   = 1000000000ULL,     
  k_gptp_mask_nsec    = 0x3FFFFFFFULL,     
  k_gptp_mask_sec_u   = 0x0000FFFFULL,     
  k_gptp_mask_sec_48  = 0xFFFFFFFFFFFFULL, 
  k_gptp_shift_sec_u  = 32ULL,             
  k_gptp_ipv_reset    = 0x00000003ULL,     
  k_gptp_hz_per_mhz   = 1000000ULL,        
} gptp_time_const_t;

typedef enum : uint32_t {
  k_gptp_reg32_bytes = 4U,    
  k_gptp_byte_mask   = 0xFFU, 
  k_gptp_shift_byte  = 8U,    
} gptp_access_const_t;

typedef struct {
  bool     enabled;      
  uint64_t off_sec;      
  uint32_t off_nsec;     
  uint64_t acc_sec;      
  uint64_t acc_fixed;    
  uint32_t latch_gptp_m; 
  uint32_t latch_gptp_u; 
  uint32_t latch_avtp_u; 
} gptp_timer_t;

typedef struct {
  uint8_t      win[k_gptp_win_span];          
  gptp_timer_t timer[k_ra8_gptp_timer_count]; 
} gptp_state_t;

static gptp_state_t s_gptp;
 
/* ------------------------------------------------------------------------- */
/* Flat config-reflect shadow helpers. */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static uint64_t internal_gptp_shadow_read(uint64_t off, unsigned size)
{
  uint64_t v = 0U;
  for (unsigned i = 0U; (i < size) && ((off + (uint64_t)i) < (uint64_t)k_gptp_win_span); ++i) {
    v |= (uint64_t)s_gptp.win[off + (uint64_t)i] << (k_gptp_shift_byte * i);
  }
  return v;
}

RA8_INTERNAL static void internal_gptp_shadow_write(uint64_t off, unsigned size, uint64_t value)
{
  for (unsigned i = 0U; (i < size) && ((off + (uint64_t)i) < (uint64_t)k_gptp_win_span); ++i) {
    s_gptp.win[off + (uint64_t)i] = (uint8_t)(value >> (k_gptp_shift_byte * i));
  }
}

RA8_INTERNAL static uint32_t internal_gptp_shadow_u32(uint64_t off)
{
  return (uint32_t)internal_gptp_shadow_read(off, k_gptp_reg32_bytes);
}
 
/* ------------------------------------------------------------------------- */
/* Per-timer offset decode. */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static bool
internal_gptp_decode_timer(uint64_t off, uint32_t* out_timer, uint64_t* out_inoff)
{
  if (off < (uint64_t)k_ra8_gptp_off_timer0) {
    return false;
  }
  const uint64_t rel   = off - (uint64_t)k_ra8_gptp_off_timer0;
  const uint32_t timer = (uint32_t)(rel / (uint64_t)k_ra8_gptp_timer_stride);
  if (timer >= (uint32_t)k_ra8_gptp_timer_count) {
    return false;
  }
  *out_timer = timer;
  *out_inoff = rel % (uint64_t)k_ra8_gptp_timer_stride;
  return true;
}
 
/* ------------------------------------------------------------------------- */
/* Free-running counter -> reported (seconds, nanoseconds). */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static void internal_gptp_time_now(uint32_t t, uint64_t* out_sec, uint32_t* out_nsec)
{
  const gptp_timer_t* u = &s_gptp.timer[t];
  if (!u->enabled) {
    /* HUM Ch 35.3.2.1 "PTPTMEC : Timer Enable Configuration Register" p 1927 --
     * a stopped unit's counters read 0. */
    *out_sec  = 0U;
    *out_nsec = 0U;
    return;
  }
  const uint32_t free_ns    = (uint32_t)(u->acc_fixed >> (uint64_t)k_gptp_subns_shift);
  uint64_t       total_nsec = (uint64_t)u->off_nsec + (uint64_t)free_ns;
  uint64_t       carry_sec  = 0U;
  if (total_nsec >= (uint64_t)k_gptp_ns_per_sec) {
    total_nsec -= (uint64_t)k_gptp_ns_per_sec;
    carry_sec = 1U;
  }
  const uint64_t total_sec = (u->off_sec + u->acc_sec + carry_sec) & (uint64_t)k_gptp_mask_sec_48;
  *out_sec                 = total_sec;
  *out_nsec                = (uint32_t)(total_nsec & (uint64_t)k_gptp_mask_nsec);
}

RA8_INTERNAL static void internal_gptp_tick_timer(uint32_t t)
{
  gptp_timer_t* u = &s_gptp.timer[t];
  if (!u->enabled) {
    return;
  }
  const uint64_t tiv_off = (uint64_t)k_ra8_gptp_off_timer0 +
                           ((uint64_t)t * (uint64_t)k_ra8_gptp_timer_stride) +
                           (uint64_t)k_ra8_gptp_off_t_ptptivc;
  /* HUM Ch 35.3.2.3 "PTPTIVCt : Timer t Increment Value Configuration Register
   * (t = 0, 1)" p 1928 -- 5.27 fixed-point nanoseconds per clk. */
  const uint64_t tiv = (uint64_t)internal_gptp_shadow_u32(tiv_off);
  if (tiv == 0U) {
    return;
  }
  u->acc_fixed += tiv * (uint64_t)k_gptp_clk_per_tick;
  const uint64_t one_sec_fixed = (uint64_t)k_gptp_ns_per_sec << (uint64_t)k_gptp_subns_shift;
  const uint64_t whole         = u->acc_fixed / one_sec_fixed;
  u->acc_sec += whole;
  u->acc_fixed -= whole * one_sec_fixed;
}
 
/* ------------------------------------------------------------------------- */
/* Enable / disable / offset commit. */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static void internal_gptp_apply_tmec(uint32_t value)
{
  /* HUM Ch 35.3.2.1 "PTPTMEC : Timer Enable Configuration Register" p 1927 --
   * writing 1 to bit q sets TEq; other bits are unaffected (write-1-to-set). */
  for (uint32_t t = 0U; t < (uint32_t)k_ra8_gptp_timer_count; ++t) {
    if ((value & (1UL << t)) != 0U) {
      s_gptp.timer[t].enabled = true;
    }
  }
}

RA8_INTERNAL static void internal_gptp_apply_tmdc(uint32_t value)
{
  /* HUM Ch 35.3.2.2 "PTPTMDC : Timer Disable Configuration Register" p 1928 --
   * writing 1 to bit q clears TEq; a stopped unit's counters read 0, so a stop
   * is also a clear of the free-running accumulator. */
  for (uint32_t t = 0U; t < (uint32_t)k_ra8_gptp_timer_count; ++t) {
    if ((value & (1UL << t)) != 0U) {
      s_gptp.timer[t].enabled   = false;
      s_gptp.timer[t].acc_sec   = 0U;
      s_gptp.timer[t].acc_fixed = 0U;
    }
  }
}

RA8_INTERNAL static uint32_t internal_gptp_read_tmec(void)
{
  uint32_t v = 0U;
  for (uint32_t t = 0U; t < (uint32_t)k_ra8_gptp_timer_count; ++t) {
    if (s_gptp.timer[t].enabled) {
      v |= (1UL << t);
    }
  }
  return v;
}

RA8_INTERNAL static void internal_gptp_commit_offset(uint32_t t)
{
  const uint64_t base =
    (uint64_t)k_ra8_gptp_off_timer0 + ((uint64_t)t * (uint64_t)k_ra8_gptp_timer_stride);
  /* HUM Ch 35.3.2.6 "PTPTOVCtU : Timer t Offset Value Configuration Register U"
   * p 1930 -- seconds [47:32]. */
  const uint64_t ovcu =
    (uint64_t)internal_gptp_shadow_u32(base + (uint64_t)k_ra8_gptp_off_t_ptptovcu);
  /* HUM Ch 35.3.2.5 "PTPTOVCMt : Timer t Offset Value Configuration Register M"
   * p 1929 -- seconds [31:0]. */
  const uint64_t ovcm =
    (uint64_t)internal_gptp_shadow_u32(base + (uint64_t)k_ra8_gptp_off_t_ptptovcm);
  /* HUM Ch 35.3.2.4 "PTPTOVCtL : Timer t Offset Value Configuration Register L"
   * p 1929 -- nanoseconds [29:0]; this write commits the whole offset. */
  const uint64_t ovcl =
    (uint64_t)internal_gptp_shadow_u32(base + (uint64_t)k_ra8_gptp_off_t_ptptovcl);
  s_gptp.timer[t].off_sec =
    ((ovcu & (uint64_t)k_gptp_mask_sec_u) << (uint64_t)k_gptp_shift_sec_u) | ovcm;
  s_gptp.timer[t].off_nsec = (uint32_t)(ovcl & (uint64_t)k_gptp_mask_nsec);
}
 
/* ------------------------------------------------------------------------- */
/* Monitoring reads (with the L-read M/U latch). */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static bool internal_gptp_read_monitor(uint32_t t, uint64_t inoff, uint32_t* out)
{
  gptp_timer_t* u = &s_gptp.timer[t];
  if (inoff == (uint64_t)k_ra8_gptp_off_t_ptpgptptml) {
    uint64_t sec  = 0U;
    uint32_t nsec = 0U;
    internal_gptp_time_now(t, &sec, &nsec);
    u->latch_gptp_m = (uint32_t)sec;
    u->latch_gptp_u =
      (uint32_t)((sec >> (uint64_t)k_gptp_shift_sec_u) & (uint64_t)k_gptp_mask_sec_u);
    *out = nsec;
    return true;
  }
  if (inoff == (uint64_t)k_ra8_gptp_off_t_ptpgptptmm) {
    *out = u->latch_gptp_m;
    return true;
  }
  if (inoff == (uint64_t)k_ra8_gptp_off_t_ptpgptptmu) {
    *out = u->latch_gptp_u;
    return true;
  }
  if (inoff == (uint64_t)k_ra8_gptp_off_t_ptpavtptml) {
    uint64_t sec  = 0U;
    uint32_t nsec = 0U;
    internal_gptp_time_now(t, &sec, &nsec);
    const uint64_t avtp = (sec * (uint64_t)k_gptp_ns_per_sec) + (uint64_t)nsec;
    u->latch_avtp_u     = (uint32_t)(avtp >> (uint64_t)k_gptp_shift_sec_u);
    *out                = (uint32_t)avtp;
    return true;
  }
  if (inoff == (uint64_t)k_ra8_gptp_off_t_ptpavtptmu) {
    *out = u->latch_avtp_u;
    return true;
  }
  return false;
}
 
/* ------------------------------------------------------------------------- */
/* MMIO dispatch. */
/* ------------------------------------------------------------------------- */

RA8_INTERNAL static uint64_t internal_gptp_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  const uint64_t off = addr - (uint64_t)k_gptp_win_base;
  if (off == (uint64_t)k_ra8_gptp_off_ptpipv) {
    /* HUM Ch 35.3.1.1 "PTPIPV : IP Version Register" p 1927 -- read-only, reset
     * value nonzero; the apps use it as the block-presence probe. */
    return (uint64_t)k_gptp_ipv_reset;
  }
  if (off == (uint64_t)k_ra8_gptp_off_ptptmec) {
    return (uint64_t)internal_gptp_read_tmec();
  }
  if (off == (uint64_t)k_ra8_gptp_off_ptptmdc) {
    /* HUM Ch 35.3.2.2 "PTPTMDC : Timer Disable Configuration Register" p 1928 --
     * write-only; reads back 0. */
    return 0U;
  }
  uint32_t timer = 0U;
  uint64_t inoff = 0U;
  if (internal_gptp_decode_timer(off, &timer, &inoff)) {
    uint32_t val = 0U;
    if (internal_gptp_read_monitor(timer, inoff, &val)) {
      return (uint64_t)val;
    }
  }
  return internal_gptp_shadow_read(off, size);
}

RA8_INTERNAL static void
internal_gptp_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)uc;
  const uint64_t off = addr - (uint64_t)k_gptp_win_base;
  if (off == (uint64_t)k_ra8_gptp_off_ptptmec) {
    internal_gptp_apply_tmec((uint32_t)value);
    return;
  }
  if (off == (uint64_t)k_ra8_gptp_off_ptptmdc) {
    internal_gptp_apply_tmdc((uint32_t)value);
    return;
  }
  if (off == (uint64_t)k_ra8_gptp_off_ptpipv) {
    return; /* PTPIPV is read-only (HUM 35.3.1.1 p 1927) -- drop the write. */
  }
  internal_gptp_shadow_write(off, size, value);
  uint32_t timer = 0U;
  uint64_t inoff = 0U;
  if (internal_gptp_decode_timer(off, &timer, &inoff) &&
      (inoff == (uint64_t)k_ra8_gptp_off_t_ptptovcl)) {
    internal_gptp_commit_offset(timer);
  }
}

RA8_INTERNAL static void internal_gptp_tick(uc_engine* uc)
{
  (void)uc;
  for (uint32_t t = 0U; t < (uint32_t)k_ra8_gptp_timer_count; ++t) {
    internal_gptp_tick_timer(t);
  }
}

RA8_INTERNAL static void internal_gptp_reset(void)
{
  s_gptp = (gptp_state_t){};
}

RA8_INTERNAL static void internal_gptp_report(void)
{
  for (uint32_t t = 0U; t < (uint32_t)k_ra8_gptp_timer_count; ++t) {
    const gptp_timer_t* u = &s_gptp.timer[t];
    if (!u->enabled && (u->acc_sec == 0U) && (u->acc_fixed == 0U)) {
      continue; /* this unit never ran -- stay quiet. */
    }
    uint64_t sec  = 0U;
    uint32_t nsec = 0U;
    internal_gptp_time_now(t, &sec, &nsec);
    (void)priv_emu_io_errf(
      "  GPTP timer%u   : gPTP=%llu.%09u s (ESWCLK %llu MHz free-run)\n",
      (unsigned)t,
      (unsigned long long)sec,
      (unsigned)nsec,
      (unsigned long long)((uint64_t)k_gptp_eswclk_hz / (uint64_t)k_gptp_hz_per_mhz));
  }
}

static const board_periph_block_t s_k_gptp_block = {
  .base   = (uint64_t)k_gptp_win_base,
  .span   = (uint64_t)k_gptp_win_span,
  .order  = (uint32_t)k_gptp_block_order,
  .read   = internal_gptp_read,
  .write  = internal_gptp_write,
  .tick   = internal_gptp_tick,
  .reset  = internal_gptp_reset,
  .report = internal_gptp_report,
  .name   = "GPTP",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_gptp_block_register(void)
{
  board_periph_register_block(&s_k_gptp_block);
}