board_periph_dtc.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_console.h"
#include "board_periph_block.h"
#include "emu_host_io_internal.h"

typedef enum : uint32_t {
  k_dtc_console_line_cap = 48U, 
} dtc_console_t;

typedef enum : uint64_t {
  k_dtc_base       = 0x4000AC00UL, 
  k_dtc_span       = 0x40UL,       
  k_dtc_off_dtccr  = 0x00UL,       
  k_dtc_off_dtcvbr = 0x04UL,       
  k_dtc_off_dtcst  = 0x0CUL,       
  k_dtc_off_dtcsts = 0x0EUL,       
} dtc_geom_t;

typedef enum : uint64_t {
  k_elc_base        = 0x40201000UL, 
  k_elc_span        = 0x100UL,      
  k_elc_off_elsegr0 = 0x04UL,       
} elc_geom_t;

typedef enum : uint32_t {
  k_elc_swevt0_event   = 0x0CCU, 
  k_elc_elsegr_trigger = 0x41U,  
} elc_swevt_t;

typedef enum : uint32_t {
  k_ti_off_mr  = 0U,  
  k_ti_off_sar = 4U,  
  k_ti_off_dar = 8U,  
  k_ti_off_crb = 12U, 
  k_ti_off_cra = 14U, 
} dtc_ti_off_t;

typedef enum : uint32_t {
  k_mr_mra_shift = 24U,   
  k_mr_mrb_shift = 16U,   
  k_mra_md_pos   = 6U,    
  k_mra_sz_pos   = 4U,    
  k_mra_sm_pos   = 2U,    
  k_mrb_dm_pos   = 2U,    
  k_mr_2bit_mask = 0x3U,  
  k_mra_md_block = 0x2U,  
  k_mr_addr_inc  = 0x2U,  
  k_mra_sz_byte  = 0x0U,  
  k_mra_sz_word  = 0x2U,  
  k_mra_sz_half  = 0x1U,  
  k_mr_byte_mask = 0xFFU, 
} dtc_mr_field_t;

typedef enum : uint32_t {
  k_dtc_block_cra_zero = 256U, 
} dtc_count_t;

typedef enum : uint32_t {
  k_dtc_vt_entry_bytes = 4U,          
  k_dtc_ti_addr_mask   = 0xFFFFFFFEU, 
  k_dtc_max_units      = 0x10000U,    
  k_dtc_ielsr_slots    = 96U,         
} dtc_vt_geom_t;

typedef enum : uint32_t {
  k_dtc_block_order = 55U, 
} dtc_order_t;

typedef struct {
  uint8_t  dtccr;       
  uint32_t dtcvbr;      
  uint8_t  dtcst;       
  uint16_t dtcsts;      
  uint32_t activations; 
  uint32_t bytes;       
} dtc_state_t;
 
static dtc_state_t s_dtc;

static uint8_t s_elc[k_elc_span];

RA8_INTERNAL static uint32_t internal_dtc_unit_bytes(uint32_t sz_code)
{
  if (sz_code == (uint32_t)k_mra_sz_word) {
    return 4U;
  }
  if (sz_code == (uint32_t)k_mra_sz_half) {
    return 2U;
  }
  return 1U;
}

RA8_INTERNAL static uint32_t internal_dtc_mem_read(uc_engine* uc, uint64_t addr, uint32_t bytes)
{
  uint32_t v = 0U;
  (void)emu_mem_read(uc, addr, &v, (size_t)bytes);
  return v;
}

typedef struct {
  uint32_t sar; 
  uint32_t dar; 
  uint32_t cra; 
  uint32_t crb; 
  uint32_t md;  
  uint32_t sz;  
  uint32_t sm;  
  uint32_t dm;  
} dtc_ti_t;

RA8_INTERNAL static void internal_dtc_decode_ti(uc_engine* uc, uint32_t ti_addr, dtc_ti_t* out)
{
  const uint32_t mr = internal_dtc_mem_read(uc, (uint64_t)ti_addr + (uint64_t)k_ti_off_mr, 4U);
  out->sar          = internal_dtc_mem_read(uc, (uint64_t)ti_addr + (uint64_t)k_ti_off_sar, 4U);
  out->dar          = internal_dtc_mem_read(uc, (uint64_t)ti_addr + (uint64_t)k_ti_off_dar, 4U);
  out->crb          = internal_dtc_mem_read(uc, (uint64_t)ti_addr + (uint64_t)k_ti_off_crb, 2U);
  out->cra          = internal_dtc_mem_read(uc, (uint64_t)ti_addr + (uint64_t)k_ti_off_cra, 2U);
 
  const uint32_t mra = (mr >> (uint32_t)k_mr_mra_shift) & (uint32_t)k_mr_byte_mask;
  const uint32_t mrb = (mr >> (uint32_t)k_mr_mrb_shift) & (uint32_t)k_mr_byte_mask;
  out->md            = (mra >> (uint32_t)k_mra_md_pos) & (uint32_t)k_mr_2bit_mask;
  out->sz            = (mra >> (uint32_t)k_mra_sz_pos) & (uint32_t)k_mr_2bit_mask;
  out->sm            = (mra >> (uint32_t)k_mra_sm_pos) & (uint32_t)k_mr_2bit_mask;
  out->dm            = (mrb >> (uint32_t)k_mrb_dm_pos) & (uint32_t)k_mr_2bit_mask;
}

RA8_INTERNAL static uint32_t internal_dtc_unit_count(const dtc_ti_t* ti)
{
  uint32_t per_block = ti->cra;
  uint32_t blocks    = 1U;
  if (ti->md == (uint32_t)k_mra_md_block) {
    if (ti->cra == 0U) {
      per_block = (uint32_t)k_dtc_block_cra_zero;
    }
    blocks = (ti->crb == 0U) ? 1U : ti->crb;
  }
  const uint32_t units = per_block * blocks;
  return (units > (uint32_t)k_dtc_max_units) ? 0U : units;
}

RA8_INTERNAL static void
internal_dtc_copy_units(uc_engine* uc, const dtc_ti_t* ti, uint32_t units, uint32_t unit)
{
  uint64_t       local_addr = (uint64_t)ti->sar;
  uint64_t       d_addr     = (uint64_t)ti->dar;
  const uint64_t local_step = (ti->sm == (uint32_t)k_mr_addr_inc) ? (uint64_t)unit : 0U;
  const uint64_t d_step     = (ti->dm == (uint32_t)k_mr_addr_inc) ? (uint64_t)unit : 0U;
  for (uint32_t i = 0U; i < units; ++i) {
    uint8_t tmp[4] = {};
    (void)emu_mem_read(uc, local_addr, tmp, (size_t)unit);
    (void)emu_mem_write(uc, d_addr, tmp, (size_t)unit);
    local_addr += local_step;
    d_addr += d_step;
  }
}

RA8_INTERNAL static void internal_dtc_run_transfer(uc_engine* uc, uint32_t ti_addr)
{
  dtc_ti_t ti = {};
  internal_dtc_decode_ti(uc, ti_addr, &ti);
 
  const uint32_t units = internal_dtc_unit_count(&ti);
  if (units == 0U) {
    return;
  }
  const uint32_t unit = internal_dtc_unit_bytes(ti.sz);
  internal_dtc_copy_units(uc, &ti, units, unit);
 
  s_dtc.activations++;
  s_dtc.bytes = units * unit;
  /* Console DMA tab: one line per DTC activation (the DTC shares the DMA tab
   * with the DMAC). Reports the unit count and unit size. */
  char ln[k_dtc_console_line_cap];
  (void)snprintf(ln, sizeof(ln), "DTC %u units x %uB", (unsigned)units, (unsigned)unit);
  board_console_push(k_board_console_ch_dma, ln);
}

RA8_INTERNAL static void internal_dtc_activate_swevt0(uc_engine* uc)
{
  if (s_dtc.dtcvbr == 0U) {
    return; /* Vector base not programmed: nothing to activate. */
  }
  const uint32_t slot = board_periph_icu_dtc_slot((uint16_t)k_elc_swevt0_event);
  if (slot >= (uint32_t)k_dtc_ielsr_slots) {
    return; /* No IELSR slot links the event with DTCE set. */
  }
  const uint64_t vt_entry =
    (uint64_t)s_dtc.dtcvbr + ((uint64_t)slot * (uint64_t)k_dtc_vt_entry_bytes);
  const uint32_t ti_addr = internal_dtc_mem_read(uc, vt_entry, 4U) & (uint32_t)k_dtc_ti_addr_mask;
  if (ti_addr == 0U) {
    return; /* No TI registered for the slot. */
  }
  internal_dtc_run_transfer(uc, ti_addr);
  /* Real silicon clears the slot's DTCE and asserts its CPU interrupt on the
   * last transfer (HUM Figure 18.5 p 801). The demo gates on the destination
   * settling (a direct poll), not the ISR, so the model performs the copy and
   * leaves interrupt delivery to the firmware's own polling path -- pending the
   * NVIC line here is unnecessary for the transfer contract and depends on the
   * app's vector wiring. The transfer (the modelled behaviour) is what flips the
   * demo to match=Y. */
}

RA8_INTERNAL static void internal_dtc_reset(void)
{
  s_dtc = (dtc_state_t){};
  for (uint32_t i = 0U; i < (uint32_t)k_elc_span; ++i) {
    s_elc[i] = 0U;
  }
}

RA8_INTERNAL static uint64_t internal_dtc_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)size;
  const uint64_t off = addr - (uint64_t)k_dtc_base;
  if (off == (uint64_t)k_dtc_off_dtccr) {
    return s_dtc.dtccr;
  }
  if (off == (uint64_t)k_dtc_off_dtcvbr) {
    return s_dtc.dtcvbr;
  }
  if (off == (uint64_t)k_dtc_off_dtcst) {
    return s_dtc.dtcst;
  }
  if (off == (uint64_t)k_dtc_off_dtcsts) {
    return s_dtc.dtcsts;
  }
  return 0U;
}

RA8_INTERNAL static void
internal_dtc_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)uc;
  (void)size;
  const uint64_t off = addr - (uint64_t)k_dtc_base;
  if (off == (uint64_t)k_dtc_off_dtccr) {
    s_dtc.dtccr = (uint8_t)value;
  } else if (off == (uint64_t)k_dtc_off_dtcvbr) {
    s_dtc.dtcvbr = (uint32_t)value;
  } else if (off == (uint64_t)k_dtc_off_dtcst) {
    s_dtc.dtcst = (uint8_t)value;
  } else if (off == (uint64_t)k_dtc_off_dtcsts) {
    s_dtc.dtcsts = (uint16_t)value;
  }
}

RA8_INTERNAL static uint64_t internal_elc_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  const uint64_t off = addr - (uint64_t)k_elc_base;
  uint64_t       v   = 0U;
  for (unsigned i = 0U; (i < size) && ((off + (uint64_t)i) < (uint64_t)k_elc_span); ++i) {
    v |= (uint64_t)s_elc[off + (uint64_t)i] << (8U * i);
  }
  return v;
}

RA8_INTERNAL static void
internal_elc_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  const uint64_t off = addr - (uint64_t)k_elc_base;
  for (unsigned i = 0U; (i < size) && ((off + (uint64_t)i) < (uint64_t)k_elc_span); ++i) {
    s_elc[off + (uint64_t)i] = (uint8_t)(value >> (8U * i));
  }
  /* The third write of the unlock/arm/trigger sequence (SEG=1) on ELSEGR0 fires
   * software event 0, which activates the DTC if a DTCE-enabled slot links it. */
  if ((off == (uint64_t)k_elc_off_elsegr0) &&
      (((uint8_t)value & (uint8_t)k_elc_elsegr_trigger) == (uint8_t)k_elc_elsegr_trigger)) {
    internal_dtc_activate_swevt0(uc);
  }
}

RA8_INTERNAL static void internal_dtc_report(void)
{
  if (s_dtc.activations == 0U) {
    return; /* Untouched: stay quiet. */
  }
  (void)priv_emu_io_errf("  DTC           : activations=%u last_bytes=%u DTCVBR=0x%08X\n",
                         s_dtc.activations,
                         s_dtc.bytes,
                         s_dtc.dtcvbr);
}

static const board_periph_block_t s_k_dtc_block = {
  .base   = (uint64_t)k_dtc_base,
  .span   = (uint64_t)k_dtc_span,
  .order  = (uint32_t)k_dtc_block_order,
  .read   = internal_dtc_read,
  .write  = internal_dtc_write,
  .tick   = nullptr,
  .reset  = internal_dtc_reset,
  .report = internal_dtc_report,
  .name   = "DTC",
};

static const board_periph_block_t s_k_elc_block = {
  .base   = (uint64_t)k_elc_base,
  .span   = (uint64_t)k_elc_span,
  .order  = (uint32_t)k_dtc_block_order,
  .read   = internal_elc_read,
  .write  = internal_elc_write,
  .tick   = nullptr,
  .reset  = nullptr,
  .report = nullptr,
  .name   = "ELC/DTC-trig",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_dtc_block_register(void)
{
  board_periph_register_block(&s_k_dtc_block);
  board_periph_register_block(&s_k_elc_block);
}