trustzone_init.c

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#include "trustzone_init.h"
 
#include <stdint.h>
 
#include "ra8_board_ek_ra8d2.h"
#include "ra8_cgc.h"
#include "ra8_err.h"
#include "ra8_gpio_constants.h"
#include "ra8_pin_validator.h"
#include "ra8_port_constants.h"
#include "ra8_port_utils.h"
#include "ra8_tz_secure_boot.h"
 
/* Bounds of the NSC veneer stubs (.gnu.sgstubs) in this (Secure) image. */
extern uint32_t g_ra8_ls_sgstubs_start; 
extern uint32_t g_ra8_ls_sgstubs_end;   

typedef enum : uintptr_t {
  k_tz_ns_load_base = 0x02080000U, 
#ifdef RA8_EREADER_NS_XIP
  k_tz_ns_run_base = 0x90000000U, 
#else
  k_tz_ns_run_base = 0x32100000U, 
#endif
  k_tz_ns_copy_size = 0x00030000U, 
} tz_ns_image_t;
 
#ifdef RA8_TRUSTZONE_ENABLE

typedef enum : uintptr_t {
  k_tz_sau_ctrl_addr   = 0xE000EDD0U, 
  k_tz_sau_type_addr   = 0xE000EDD4U, 
  k_tz_sau_rnr_addr    = 0xE000EDD8U, 
  k_tz_sau_rbar_addr   = 0xE000EDDCU, 
  k_tz_sau_rlar_addr   = 0xE000EDE0U, 
  k_tz_sramsabar0_addr = 0x40008400U, 
  k_tz_prcr_s_addr     = 0x4001E3FAU, 
  k_tz_psarb_addr      = 0x40204004U, 
} tz_reg_addr_t;

typedef enum : uint32_t {
  k_tz_sau_ctrl_enable      = 0x00000001U, 
  k_tz_sau_rlar_enable      = 0x00000001U, 
  k_tz_sau_rlar_nsc         = 0x00000002U, 
  k_tz_sau_limit_mask       = 0xFFFFFFE0U, 
  k_tz_sau_type_mask        = 0x000000FFU, 
  k_tz_psarb_usbfs_ns       = 0x00000800U, 
  k_tz_psarb_usbhs_ns       = 0x00001000U, 
  k_tz_psarb_usb_ns         = 0x00001800U, 
  k_tz_psarb_readback_spins = 1000U,       
} tz_field_t;

typedef enum : uint16_t {
  k_tz_usb_pin_vbus = ((uint16_t)k_ra8_port_4 << 8) | (uint16_t)k_ra8_pin_7, 
  k_tz_usb_pin_vbusen =
    ((uint16_t)k_ra8_port_5 << 8) | (uint16_t)k_ra8_pin_0,                  
  k_tz_usb_pin_dp = ((uint16_t)k_ra8_port_8 << 8) | (uint16_t)k_ra8_pin_14, 
  k_tz_usb_pin_dm = ((uint16_t)k_ra8_port_8 << 8) | (uint16_t)k_ra8_pin_15, 
  k_tz_usb_pin_hs_vbus = ((uint16_t)k_ra8_port_4 << 8) | (uint16_t)k_ra8_pin_8,
  k_tz_usb_pin_hs_pwr = ((uint16_t)k_ra8_port_13 << 8) | (uint16_t)k_ra8_pin_7, 
} tz_usb_pin_t;

volatile uint32_t g_tz_usb_psarb_readback;

volatile uint32_t g_tz_usb_pins_err;

volatile uint32_t g_tz_usb_expander_err;

volatile uint32_t g_tz_jump_ns_err;

typedef enum : uint16_t {
  k_tz_prcr_s_open  = 0xA510U, 
  k_tz_prcr_s_close = 0xA500U, 
} tz_prcr_t;

typedef enum : uint32_t {
  k_tz_sau_min_regions = 4U,          
  k_tz_ns_code_base    = 0x10000000U, 
  k_tz_ns_code_limit   = 0x1FFFFFE0U, 
  k_tz_ns_sram_base    = 0x30000000U, 
  k_tz_ns_sram_limit   = 0x3FFFFFE0U, 
  k_tz_ns_per_base     = 0x50000000U, 
  k_tz_ns_per_limit    = 0xDFFFFFE0U, 
  k_tz_sramsabar0_val  = 0x00080000U, 
  k_tz_sramsabar1_val  = 0x00100000U, 
  k_tz_sramsabar2_val  = 0x00100000U, 
  k_tz_sramsabar3_val  = 0x001A0000U, 
} tz_partition_t;

typedef enum : uint8_t {
  k_tz_region_nsc     = 0U, 
  k_tz_region_ns_code = 1U, 
  k_tz_region_ns_sram = 2U, 
  k_tz_region_ns_per  = 3U, 
} tz_region_t;

static inline void tz_write32(uintptr_t addr, uint32_t value)
{
  /* HUM Ch 51.3.3.3 "Secure Attribution Unit (SAU)" p 3266 -- generic
   * secure-MMIO store; SAU / CPSCU callers cite their own page below. */
  *(volatile uint32_t*)addr = value;
}

static inline uint32_t tz_read32(uintptr_t addr)
{
  /* HUM Ch 51.3.3.3 "Secure Attribution Unit (SAU)" p 3266 */
  return *(volatile uint32_t*)addr;
}

static void tz_sau_set_region(uint8_t region, uint32_t base, uint32_t limit, bool is_nsc)
{
  /* HUM Ch 51.3.3.3 "Secure Attribution Unit (SAU)" p 3266 */
  tz_write32(k_tz_sau_rnr_addr, (uint32_t)region);
  tz_write32(k_tz_sau_rbar_addr, base & (uint32_t)k_tz_sau_limit_mask);
  uint32_t rlar = (limit & (uint32_t)k_tz_sau_limit_mask) | (uint32_t)k_tz_sau_rlar_enable;
  if (is_nsc) {
    rlar |= (uint32_t)k_tz_sau_rlar_nsc;
  }
  tz_write32(k_tz_sau_rlar_addr, rlar);
}

static void tz_sram_ns_boundary(void)
{
  /* Open PRC4 so the CPSCU SRAMSABAR writes below land. */
  /* HUM Ch 13.2.1 "PRCR_S" p 521 */
  *(volatile uint16_t*)k_tz_prcr_s_addr = (uint16_t)k_tz_prcr_s_open;
 
  /* HUM Ch 58.2 "SRAMSABARn : SRAM Security Attribute Boundary Address
   * Register" p 3527 -- boundary = start address of the NS region; below
   * = Secure, at/above = Non-secure. */
  tz_write32(k_tz_sramsabar0_addr + (0U * sizeof(uint32_t)), (uint32_t)k_tz_sramsabar0_val);
  tz_write32(k_tz_sramsabar0_addr + (1U * sizeof(uint32_t)), (uint32_t)k_tz_sramsabar1_val);
  tz_write32(k_tz_sramsabar0_addr + (2U * sizeof(uint32_t)), (uint32_t)k_tz_sramsabar2_val);
  tz_write32(k_tz_sramsabar0_addr + (3U * sizeof(uint32_t)), (uint32_t)k_tz_sramsabar3_val);
 
  /* Re-lock PRC4 (restore CPSCU write-protect). */
  /* HUM Ch 13.2.1 "PRCR_S" p 521 */
  *(volatile uint16_t*)k_tz_prcr_s_addr = (uint16_t)k_tz_prcr_s_close;
}

static ra8_err_t tz_sau_program(void)
{
  /* HUM Ch 51.3.3.3 "Secure Attribution Unit (SAU)" p 3266 -- need at
   * least 4 implemented regions for this layout. */
  const uint32_t sau_type = tz_read32(k_tz_sau_type_addr);
  if ((sau_type & (uint32_t)k_tz_sau_type_mask) < (uint32_t)k_tz_sau_min_regions) {
    return k_ra8_err_not_supported;
  }
 
  /* RLAR limit is the LAST byte of the veneer block (end - 1); the helper
   * masks it to the 32-byte SAU region quantum. */
  const uint32_t nsc_base  = (uint32_t)(uintptr_t)&g_ra8_ls_sgstubs_start;
  const uint32_t nsc_limit = (uint32_t)(uintptr_t)&g_ra8_ls_sgstubs_end - 1U;
  tz_sau_set_region((uint8_t)k_tz_region_nsc, nsc_base, nsc_limit, /*is_nsc=*/true);
  tz_sau_set_region((uint8_t)k_tz_region_ns_code,
                    (uint32_t)k_tz_ns_code_base,
                    (uint32_t)k_tz_ns_code_limit,
                    /*is_nsc=*/false);
  tz_sau_set_region((uint8_t)k_tz_region_ns_sram,
                    (uint32_t)k_tz_ns_sram_base,
                    (uint32_t)k_tz_ns_sram_limit,
                    /*is_nsc=*/false);
  tz_sau_set_region((uint8_t)k_tz_region_ns_per,
                    (uint32_t)k_tz_ns_per_base,
                    (uint32_t)k_tz_ns_per_limit,
                    /*is_nsc=*/false);
 
  __asm__ volatile("dsb 0xF" ::: "memory");
  /* Enable the SAU with ALLNS = 0 (default-deny). */
  /* HUM Ch 51.3.3.3 "Secure Attribution Unit (SAU)" p 3266 */
  tz_write32(k_tz_sau_ctrl_addr, (uint32_t)k_tz_sau_ctrl_enable);
  __asm__ volatile("dsb 0xF" ::: "memory");
  __asm__ volatile("isb" ::: "memory");
  return k_ra8_ok;
}
 
/* The NS image copy exists only for the SRAM-run configuration. Under
 * RA8_EREADER_NS_XIP the NS .text/.rodata execute in place from the OSPI NS
 * alias, ra8_trustzone_init() takes the #ifdef arm that does no copy, and this
 * routine has no call site at all -- so it is compiled out rather than defined
 * and excused. An unreferenced static is exactly what -Wunused-function is for,
 * and this file is built with -Werror. */
#ifndef RA8_EREADER_NS_XIP
static void tz_copy_ns_image(void)
{
  /* Driven through tz_read32 / tz_write32 rather than open-coded casts: those
   * two are the unit's only integer-to-pointer conversions, and both are
   * `static inline`, so the emitted loop is the same word copy. */
  const uintptr_t load_base = (uintptr_t)k_tz_ns_load_base;
  const uintptr_t run_base  = (uintptr_t)k_tz_ns_run_base;
  for (uintptr_t off = 0U; off < (uintptr_t)k_tz_ns_copy_size; off += sizeof(uint32_t)) {
    tz_write32(run_base + off, tz_read32(load_base + off));
  }
}
#endif /* !RA8_EREADER_NS_XIP */

static ra8_err_t tz_usb_route_pins(void)
{
  /* Establish the pin-validator baseline. The Secure boot never runs
   * ra8_infrastructure_init (its main() is dead -- BLXNS does not return), so
   * the validator bitmap is in an uninitialised-contract state and warm
   * resets leave stale claims (SRAM survives SYSRESETREQ; PFS does not), which
   * would make the USB-pin claims spuriously conflict. Reset it first. */
  ra8_pin_validator_reset();
 
  /* Route the USB-FS pins as the DEVICE (Secure owns PFS). P5_00 LOW = dev. */
  ra8_err_t err = ra8_pfs_route_peripheral((ra8_port_pin_t)k_tz_usb_pin_vbus,
                                           k_ra8_psel_usb_fs,
                                           "tz_usb.fs_vbus");
  if (err == k_ra8_ok) {
    err = ra8_gpio_output_init((ra8_port_pin_t)k_tz_usb_pin_vbusen, k_ra8_level_low);
  }
  if (err == k_ra8_ok) {
    err =
      ra8_pfs_route_peripheral((ra8_port_pin_t)k_tz_usb_pin_dp, k_ra8_psel_usb_fs, "tz_usb.fs_dp");
  }
  if (err == k_ra8_ok) {
    err =
      ra8_pfs_route_peripheral((ra8_port_pin_t)k_tz_usb_pin_dm, k_ra8_psel_usb_fs, "tz_usb.fs_dm");
  }
 
  /* USBHS host pins: PD07 HIGH (U18 supplies J7 VBUS), route P4_08
   * USBHS_VBUS. (The host-mode mux is the U15 expander -- handled later.) */
  if (err == k_ra8_ok) {
    err = ra8_gpio_output_init((ra8_port_pin_t)k_tz_usb_pin_hs_pwr, k_ra8_level_high);
  }
  if (err == k_ra8_ok) {
    err = ra8_pfs_route_peripheral((ra8_port_pin_t)k_tz_usb_pin_hs_vbus,
                                   k_ra8_psel_usb_hs,
                                   "tz_usb.hs_vbus");
  }
 
  /* Enable the USBHS UTMI PLL (Secure CGC; PLL1 already locked). A warm
   * reset leaves the CGC PLL domain running, so a re-enable reports
   * k_ra8_err_busy ("already locked"); the clock is up either way, so treat
   * busy as success. */
  if (err == k_ra8_ok) {
    const ra8_err_t pll_err = ra8_cgc_usbhs_pll_enable();
    if ((pll_err != k_ra8_ok) && (pll_err != k_ra8_err_busy)) {
      err = pll_err;
    }
  }
  return err;
}

static void tz_usb_mark_ns(void)
{
  /* HUM Ch 51.8.1 "PSARB : Peripheral Security Attribution Register B" p 3284
   * -- PSARB11 = USBFS0, PSARB12 = USBHS (+ their MSTPCRB.MSTPB11/12 bits);
   * 0 = Secure, 1 = Non-secure. PSARx share the PRCR_S.PRC4 write gate with
   * SRAMSABARn (HUM Ch 13.2.1 "Association between PRCR bits and use of
   * registers" p 521), so the gate must be open across the write; HUM "Security
   * or Privilege Bit Write Timing" p 3301 then requires reading back until the
   * value matches. */
  /* Open PRC4. HUM Ch 13.2.1 "PRCR_S" p 521 */
  *(volatile uint16_t*)k_tz_prcr_s_addr = (uint16_t)k_tz_prcr_s_open;
  const uint32_t want                   = tz_read32(k_tz_psarb_addr) | (uint32_t)k_tz_psarb_usb_ns;
  tz_write32(k_tz_psarb_addr, want);
  uint32_t seen = 0U;
  for (uint32_t spin = 0U; spin < (uint32_t)k_tz_psarb_readback_spins; spin += 1U) {
    seen = tz_read32(k_tz_psarb_addr);
    if (seen == want) {
      break;
    }
  }
  /* Re-lock PRC4. HUM Ch 13.2.1 "PRCR_S" p 521 */
  *(volatile uint16_t*)k_tz_prcr_s_addr = (uint16_t)k_tz_prcr_s_close;
  g_tz_usb_psarb_readback               = seen;
}

static void tz_usb_handoff_prepare(void)
{
  /* 1+2+3. Route USB pins (FS device + HS host) and enable the USBHS PLL. */
  const ra8_err_t pins_err = tz_usb_route_pins();
  g_tz_usb_pins_err        = (uint32_t)pins_err;
 
  /* 4. Set the U15 I/O-expander to USBHS host mode (SW4-8 -> Host). Decoupled
   *    from the deterministic setup above and best-effort: on a cold boot the
   *    single I2C write lands (probe -> success); after a warm reset RIIC1's
   *    BBSY can still be set, reporting k_ra8_err_busy. The external PI4IOE
   *    latches its host-mode output, so the USBHS host role persists across the
   *    MCU warm reset -- the self-loop still enumerates (the HIL gate proves
   *    it). A retry cannot help here: the expander claims the SCL1/SDA1 pins on
   *    the first try and a second try would fault the pin validator. */
  const ra8_err_t exp_err = ra8_board_io_expander_set_usbhs_host_mode();
  g_tz_usb_expander_err   = (uint32_t)exp_err;
 
  /* 5. Mark BOTH USB controllers Non-secure in PSARB (bits 11 + 12). */
  tz_usb_mark_ns();
}
 
#endif /* RA8_TRUSTZONE_ENABLE */
 
void ra8_trustzone_init(void)
{
#ifdef RA8_TRUSTZONE_ENABLE
  /* 0. Hand USB-FS (pins + PSARB NS attribution) to the NS world. */
  tz_usb_handoff_prepare();
 
  /* 1. Carve the SRAM2 NS aperture via the runtime SRAMSABAR boundary. */
  tz_sram_ns_boundary();
 
  /* 2. Programme the bit[28] SAU (NSC veneers + IDAU-NS ranges), enable. */
  if (tz_sau_program() != k_ra8_ok) {
    return; /* Fall through to the S-side main() fallback. */
  }
 
#ifdef RA8_EREADER_NS_XIP
  /* 3. XIP: no image copy. .text/.rodata execute in place from the OSPI NS
   *    alias (0x9000_0000); ns_reset_handler copies only .data into SRAM.
   *    ra8_emulator maps the OSPI window unconditionally, so the fake proof needs
   *    no controller arming here.
   *    TODO(OSPI XIP arming on silicon): before this BLXNS, call
   *    ra8_xspi_xip_enter(instance, enter_code, exit_code) with the EK-RA8D2
   *    OSPI flash's real XIP enter/exit opcodes so the 0x8000_0000/0x9000_0000
   *    window returns flash on hardware, and add a SAU region marking the OSPI
   *    NS alias Non-secure (the IDAU bit[28] alias alone is overridden Secure by
   *    the default SAU). Both are unnecessary in ra8_emulator. */
#else
  /* 3. Copy the NS image into the now-Non-secure SRAM alias. */
  tz_copy_ns_image();
#endif
 
  /* 4. Clear the Secure PRIMASK before handing off. SystemInit masked IRQs
   *    (CPSID i) for secure bring-up; a set PRIMASK_S boosts the execution
   *    priority and masks NON-secure exceptions too, so the NS ThreadX
   *    PendSV / SysTick would never fire. The NS side cannot clear PRIMASK_S
   *    (it is Secure-banked), so do it here, right before BLXNS. */
  __asm__ volatile("cpsie i" ::: "memory");
 
  /* 5. BLXNS into the NS reset vector (slot 1 of the NS vector table at the
   *    fixed run base 0x3210_0000). Does not return on hardware. */
  const ra8_err_t jump_err =
    ra8_tz_secure_boot_jump_ns((const uint32_t*)(uintptr_t)k_tz_ns_run_base);
  if (jump_err != k_ra8_ok) {
    /* Reached on hardware ONLY when the NS image was DENIED (vector-table
     * validation or the root-of-trust gate failed). Latch the verdict for a
     * J-Link probe and fall through to the S-side main() fallback -- never
     * treat the NS world as live. */
    g_tz_jump_ns_err = (uint32_t)jump_err;
    return;
  }
 
  /* On host (RA8_OFF_TARGET) the library stubs BLXNS and returns
   * k_ra8_ok; on target this point is unreachable. */
#endif
}