ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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ra8_vreg_regs.h
Go to the documentation of this file.
1
44
45#pragma once
46
47#ifdef __cplusplus
48extern "C" {
49#endif
50
51#include <stdint.h>
52
63typedef enum : uintptr_t {
66
82typedef enum : uintptr_t {
87
112
131
155
172
188
215
228static inline volatile uint8_t* ra8_vreg_dcdcctl(void)
229{
230 return (volatile uint8_t*)((uintptr_t)k_ra8_vreg_sysc_base_addr +
231 (uintptr_t)k_ra8_vreg_off_dcdcctl);
232}
233
238static inline volatile uint8_t* ra8_vreg_vccsel(void)
239{
240 return (volatile uint8_t*)((uintptr_t)k_ra8_vreg_sysc_base_addr +
241 (uintptr_t)k_ra8_vreg_off_vccsel);
242}
243
248static inline volatile uint8_t* ra8_vreg_lvocr(void)
249{
250 return (volatile uint8_t*)((uintptr_t)k_ra8_vreg_sysc_base_addr +
251 (uintptr_t)k_ra8_vreg_off_lvocr);
252}
253
254#ifdef __cplusplus
255}
256#endif
static volatile uint8_t * ra8_vreg_vccsel(void)
Get a volatile pointer to the 8-bit VCCSEL register.
ra8_vreg_dcdcctl_bit_t
DCDCCTL bit positions (mirrors FSP R_SYSTEM_DCDCCTL_*_Pos).
@ k_ra8_vreg_bit_fst
DCDC fast-startup mode.
@ k_ra8_vreg_bit_pd
DCDC VREF generate disable.
@ k_ra8_vreg_bit_dcdcon
LDO/DCDC on/off control.
@ k_ra8_vreg_bit_ocpen
DCDC over-current protection enable.
@ k_ra8_vreg_bit_stopza
DCDC IO buffer power control.
@ k_ra8_vreg_bit_lcboost
LDO charge-pump boost (subosc mode).
ra8_vreg_addr_t
SYSC base address that hosts every VREG register.
@ k_ra8_vreg_sysc_base_addr
R_SYSTEM (SYSC) base.
static volatile uint8_t * ra8_vreg_dcdcctl(void)
Get a volatile pointer to the 8-bit DCDCCTL register.
ra8_vreg_off_t
Byte offsets of every VREG-related register inside SYSC.
@ k_ra8_vreg_off_vccsel
VCCSEL offset.
@ k_ra8_vreg_off_lvocr
LVOCR offset.
@ k_ra8_vreg_off_dcdcctl
DCDCCTL offset.
ra8_vreg_dcdcctl_step_t
Pre-baked DCDCCTL values used by the LDO->DCDC handshake.
@ k_ra8_vreg_dcdc_step_fast_on
STOPZA + DCDCON + OCPEN + FST – fast.
@ k_ra8_vreg_dcdc_step_lp_vref
STOPZA only – low-power Vref step.
@ k_ra8_vreg_dcdc_step_dcdc_on
STOPZA + DCDCON – LDO off, DCDC on.
@ k_ra8_vreg_dcdc_step_with_ocp
STOPZA + DCDCON + OCPEN – final DCDC.
ra8_vreg_timing_us_t
Stabilisation delays prescribed by the LPM chapter for every documented DCDC <-> LDO transition.
@ k_ra8_vreg_delay_vref_us
Vref stabilisation.
@ k_ra8_vreg_delay_fast_us
DCDC fast-startup total.
@ k_ra8_vreg_delay_iobuf_us
STOPZA -> Vref handshake soak.
@ k_ra8_vreg_delay_dcdc_us
DCDC switch-on settle.
@ k_ra8_vreg_delay_ldo_us
LDO stabilisation after DCDC->LDO.
static volatile uint8_t * ra8_vreg_lvocr(void)
Get a volatile pointer to the 8-bit LVOCR register.
ra8_vreg_lvocr_mask_t
LVOCR low-voltage-operation enables.
@ k_ra8_vreg_mask_lvo_all
Union of every LVOCR writable bit.
@ k_ra8_vreg_mask_lvo1e
LVO1E – low-voltage profile 1 enable.
@ k_ra8_vreg_mask_lvo0e
LVO0E – low-voltage profile 0 enable.
ra8_vreg_vccsel_t
VCCSEL[1:0] supply-voltage range selection (DCDC mode only).
@ k_ra8_vreg_vccsel_3v0_to_3v6
3.0 V <= VCC <= 3.6 V.
@ k_ra8_vreg_vccsel_mask
2-bit field mask.
@ k_ra8_vreg_vccsel_2v4_to_2v7
2.4 V <= VCC < 2.7 V.
@ k_ra8_vreg_vccsel_2v7_to_3v0
2.7 V <= VCC < 3.0 V.
ra8_vreg_dcdcctl_mask_t
DCDCCTL bit masks.
@ k_ra8_vreg_mask_fst
Bit 6.
@ k_ra8_vreg_mask_lcboost
Bit 5.
@ k_ra8_vreg_mask_dcdcctl_all
Union of all writable bits (0,1,4,5,6,7).
@ k_ra8_vreg_mask_pd
Bit 7.
@ k_ra8_vreg_mask_ocpen
Bit 1.
@ k_ra8_vreg_mask_stopza
Bit 4.
@ k_ra8_vreg_mask_dcdcon
Bit 0.