39typedef enum : uint8_t {
53typedef enum : uint8_t {
ra8_err_t ra8_dac_b_set_output_enable(uint8_t channel, bool enable)
Toggle output-enable for one channel at runtime.
ra8_err_t ra8_dac_b_deinit(void)
Tear down the DAC_B peripheral.
ra8_err_t ra8_dac_b_init(void)
Legacy init – zero every DAC_B register + enable MSTP.
ra8_dac_b_vref_t
VREFH operating-mode selection (DACR2.OFSSEL bit 8).
@ k_ra8_dac_b_vref_low
OFSSEL=1: VREFH < 2.7V.
@ k_ra8_dac_b_vref_normal
OFSSEL=0: VREFH >= 2.7V (default).
ra8_err_t ra8_dac_b_write(uint8_t channel, uint16_t value)
Programme a DAC channel with a 12-bit code.
ra8_dac_b_data_format_t
Data placement selection (DACR1.DPSEL bit 16).
@ k_ra8_dac_b_format_right
DPSEL=0: right-justified (default).
@ k_ra8_dac_b_format_left
DPSEL=1: left-justified.
ra8_err_t ra8_dac_b_init_configured(const ra8_dac_b_cfg_t *cfg)
Initialise DAC_B with a full config descriptor.
ra8_err_t ra8_dac_b_get_status(uint8_t *out_mask)
Read the DACR output-enable / DAE mask.
ra8_err_t ra8_dac_b_clear_status(void)
Clear DAE + DAOE bits (disable DAC outputs).
ra8_err_t ra8_dac_b_exit_stop(void)
Exit MSTP-gated stop.
void ra8_dac_b_dispatch_update(uint8_t channel)
Dispatch a DAC-update event – fire the registered callback.
ra8_err_t ra8_dac_b_set_vref(ra8_dac_b_vref_t vref)
Change the DAC voltage reference at runtime.
ra8_err_t ra8_dac_b_enter_stop(void)
Put DAC_B into MSTP-gated stop.
void(* ra8_dac_b_update_fn_t)(void *ctx, uint8_t channel)
DAC update (conversion done) event callback.
ra8_err_t ra8_dac_b_attach_handler(ra8_dac_b_update_fn_t fn, void *ctx)
Attach a DAC-update callback.
Error Code Definitions for ra8-firmware.
ra8_err_codes_t ra8_err_t
Canonical error-return type used by every ra8-firmware API.
Configuration descriptor for ra8_dac_b_init_configured.
ra8_dac_b_vref_t vref
VREFH range (DACR2.OFSSEL).
bool enable_channel1
Initial DACEN1 state.
ra8_dac_b_data_format_t data_format
Data placement (DACR1.DPSEL).
bool internal_output_enabled
Drive internal route (clears DAOUTDIS).
bool enable_channel0
Initial DACEN0 state.