ra8_boot_intrinsics.h File Reference

Tiny MMIO / barrier intrinsics shared by the boot files. More...

#include <stdint.h>

Include dependency graph for ra8_boot_intrinsics.h:

Go to the source code of this file.

Functions
static uint32_t	ra8_boot_read32 (uintptr_t addr)
	Volatile 32-bit MMIO read.
static void	ra8_boot_write32 (uintptr_t addr, uint32_t value)
	Volatile 32-bit MMIO write.
static void	ra8_boot_dsb (void)
	Data synchronisation barrier (no-op under RA8_OFF_TARGET).
static void	ra8_boot_isb (void)
	Instruction synchronisation barrier (no-op under RA8_OFF_TARGET).
static void	ra8_boot_disable_irq (void)
	Mask IRQs / set PRIMASK (no-op under RA8_OFF_TARGET).

Detailed Description

Tiny MMIO / barrier intrinsics shared by the boot files.

Tag

[Ring 1 / BSP] {World: S}

One documented home for the volatile MMIO accessors and CPU barriers that the shared boot translation units (system_init.c, trustzone_init.c) both need, so the helpers are not duplicated and documented per file. All are static inline – each including TU gets its own internal-linkage copy, so there is no shared state.

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file ra8_boot_intrinsics.h.

Function Documentation

ra8_boot_disable_irq()

void ra8_boot_disable_irq ( void )

inlinestatic

Mask IRQs / set PRIMASK (no-op under RA8_OFF_TARGET).

Disables maskable interrupt delivery for the critical boot window.

Precondition

Running on the target core (or the host fake).

Called early in Reset before handlers are armed.

Postcondition

Maskable interrupts are disabled (PRIMASK=1).

No data state is mutated.

Note

ISR-safe.

Since

0.1.0

Definition at line 104 of file ra8_boot_intrinsics.h.

ra8_boot_dsb()

void ra8_boot_dsb ( void )

inlinestatic

Data synchronisation barrier (no-op under RA8_OFF_TARGET).

Completes all prior memory accesses before continuing.

Precondition

Running on the target core (or the host fake).

Used after an MMIO write that must take effect before the next step.

Postcondition

All earlier explicit memory accesses have completed.

Subsequent instructions observe those effects.

Note

ISR-safe.

Since

0.1.0

Definition at line 70 of file ra8_boot_intrinsics.h.

ra8_boot_isb()

void ra8_boot_isb ( void )

inlinestatic

Instruction synchronisation barrier (no-op under RA8_OFF_TARGET).

Flushes the pipeline so later instructions see prior context changes.

Precondition

Running on the target core (or the host fake).

A system-control register affecting fetch/exec was just written.

Postcondition

The pipeline is flushed; later instructions use the new context.

No data state is mutated.

Note

ISR-safe.

Since

0.1.0

Definition at line 87 of file ra8_boot_intrinsics.h.

ra8_boot_read32()

uint32_t ra8_boot_read32 ( uintptr_t addr )

inlinestatic

Volatile 32-bit MMIO read.

Single volatile load; the cast fixes the access width.

Parameters

[in]

addr

Absolute MMIO address (must be 4-byte aligned).

Returns

The 32-bit word at addr.

Return values

value

Little-endian word read from addr.

Precondition

addr is a mapped, 4-byte-aligned MMIO address.

The owning peripheral's bus clock is enabled.

Postcondition

No state is mutated.

The read has completed (volatile, not reordered).

Note

Thread-safe (pure read).

Since

0.1.0

Definition at line 38 of file ra8_boot_intrinsics.h.

ra8_boot_write32()

void ra8_boot_write32 ( uintptr_t addr, uint32_t value )

inlinestatic

Volatile 32-bit MMIO write.

Single volatile store of value to addr.

Parameters

[in]	addr	Absolute MMIO address (must be 4-byte aligned).
[in]	value	32-bit word to store.

Precondition

addr is a mapped, 4-byte-aligned MMIO address.

The owning peripheral's bus clock is enabled.

Postcondition

addr holds value.

The store has been issued (volatile).

Note

Not thread-safe; callers serialise during single-threaded boot.

Since

0.1.0

Definition at line 55 of file ra8_boot_intrinsics.h.