trustzone_init.c

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#include "trustzone_init.h"
 
#include <stdint.h>
 
#ifdef RA8_TRUSTZONE_ENABLE
 
/* =============================================================================
 * SAU register addresses (System Control Space, secure alias)
 * =============================================================================
 */
 
typedef enum : uintptr_t {
  k_ra8_sau_ctrl_addr = 0xE000EDD0UL, 
  k_ra8_sau_type_addr = 0xE000EDD4UL, 
  k_ra8_sau_rnr_addr  = 0xE000EDD8UL, 
  k_ra8_sau_rbar_addr = 0xE000EDDCUL, 
  k_ra8_sau_rlar_addr = 0xE000EDE0UL, 
  k_ra8_sfsr_addr     = 0xE000EDE4UL, 
} ra8_tz_sau_addr_t;

typedef enum : uint32_t {
  k_ra8_sau_ctrl_enable = 1UL << 0, 
  k_ra8_sau_ctrl_allns  = 1UL << 1, 
} ra8_tz_sau_ctrl_bit_t;

typedef enum : uint32_t {
  k_ra8_sau_rlar_enable = 1UL << 0, 
  k_ra8_sau_rlar_nsc    = 1UL << 1, 
} ra8_tz_sau_rlar_bit_t;

typedef enum : uint32_t {
  k_ra8_tz_ns_mram_base    = 0x02080000UL, 
  k_ra8_tz_ns_mram_limit   = 0x020FFFE0UL, 
  k_ra8_tz_ns_sram_base    = 0x22100000UL, 
  k_ra8_tz_ns_sram_limit   = 0x221FFFE0UL, 
  k_ra8_tz_ns_sdram_base   = 0x6A000000UL, 
  k_ra8_tz_ns_sdram_limit  = 0x6BFFFFE0UL, 
  k_ra8_tz_nsc_veneer_base = 0x10000000UL, 
  k_ra8_tz_nsc_veneer_lim  = 0x100FFFE0UL, 
} ra8_tz_partition_t;
 
/* =============================================================================
 * Internal helpers
 * =============================================================================
 */
 
static inline void internal_dsb(void)
{
  __asm__ volatile("dsb 0xF" ::: "memory");
}
 
static inline void internal_isb(void)
{
  __asm__ volatile("isb 0xF" ::: "memory");
}
 
/* SAU (RNR / RBAR / RLAR / TYPE / CTRL) is an Arm v8-M architectural block in
 * the PPB window, described by the Arm v8-M Architecture Reference Manual and
 * not by the RA8D2 Hardware User's Manual -- a HUM citation here would name a
 * chapter that does not describe these registers. Route every access through
 * one named accessor rather than casting at each use, exactly as ra8_scb_reg
 * does for the System Control Block. */
static inline volatile uint32_t* internal_sau_reg(uintptr_t addr)
{
  return (volatile uint32_t*)addr;
}
 
static void internal_write32(uintptr_t addr, uint32_t value)
{
  *internal_sau_reg(addr) = value;
}
 
static uint32_t internal_read32(uintptr_t addr)
{
  return *internal_sau_reg(addr);
}

static void internal_sau_set_region(uint32_t region, uint32_t base, uint32_t limit, bool is_nsc)
{
  internal_write32(k_ra8_sau_rnr_addr, region);
  internal_write32(k_ra8_sau_rbar_addr, base);
  uint32_t rlar = limit | (uint32_t)k_ra8_sau_rlar_enable;
  if (is_nsc) {
    rlar |= (uint32_t)k_ra8_sau_rlar_nsc;
  }
  internal_write32(k_ra8_sau_rlar_addr, rlar);
}
 
/* =============================================================================
 * Public entry point
 * =============================================================================
 */
 
#endif /* RA8_TRUSTZONE_ENABLE */
 
void ra8_trustzone_init(void)
{
#ifdef RA8_TRUSTZONE_ENABLE
  /* Sanity check: SAU_TYPE.SREGION must report >= 4 implemented
   * regions for our partition to fit. The Cortex-M85 always has 8,
   * but a chip-specific override could trim the count. */
  const uint32_t sau_type = internal_read32(k_ra8_sau_type_addr);
  if ((sau_type & 0xFFU) < 4U) {
    /* Refuse to bring up TrustZone on an SAU we cannot use. The
     * caller will see SAU_CTRL.ENABLE clear and fall back to the
     * single-world model. */
    return;
  }
 
  /* Region 0: NS upper MRAM */
  internal_sau_set_region(0U,
                          (uint32_t)k_ra8_tz_ns_mram_base,
                          (uint32_t)k_ra8_tz_ns_mram_limit,
                          /*is_nsc=*/false);
 
  /* Region 1: NS upper SRAM */
  internal_sau_set_region(1U,
                          (uint32_t)k_ra8_tz_ns_sram_base,
                          (uint32_t)k_ra8_tz_ns_sram_limit,
                          /*is_nsc=*/false);
 
  /* Region 2: NS upper SDRAM */
  internal_sau_set_region(2U,
                          (uint32_t)k_ra8_tz_ns_sdram_base,
                          (uint32_t)k_ra8_tz_ns_sdram_limit,
                          /*is_nsc=*/false);
 
  /* Region 3: NSC veneer alias ( will place .gnu.sgstubs
   * here via the linker script). */
  internal_sau_set_region(3U,
                          (uint32_t)k_ra8_tz_nsc_veneer_base,
                          (uint32_t)k_ra8_tz_nsc_veneer_lim,
                          /*is_nsc=*/true);
 
  /* Enable the SAU. Leave ALLNS clear: anything we have not
   * explicitly carved out stays secure (default-deny). */
  internal_dsb();
  internal_write32(k_ra8_sau_ctrl_addr, (uint32_t)k_ra8_sau_ctrl_enable);
  internal_dsb();
  internal_isb();
#endif
}