main.c File Reference

HIL gate for the ra8_reset driver – software-reset round-trip. More...

#include <stdint.h>
#include "ra8_attributes.h"
#include "ra8_boot_entry.h"
#include "ra8_err.h"
#include "ra8_isr.h"
#include "ra8_log.h"
#include "ra8_reset.h"
#include "ra8_time.h"

Include dependency graph for main.c:

Go to the source code of this file.

Enumerations
enum	reset_cause_demo_const_t : uint32_t {   k_reset_cause_cpu_hz_at_reset = 8400000U ,   k_reset_cause_settle_ms = 200U ,   k_reset_cause_loop_period_ms = 50U }
	Internal constants for the reset-cause demo. More...

Functions
static void	internal_reset_cause_panic_halt (void)
	Park the CPU forever in WFI – used after the SW reset write or if HAL init fails.
void	main (void)
	The application entry point Reset_Handler hands control to.

Variables
volatile uint32_t	g_reset_cause_loop = 0U
	HIL-probed counter – advances only after the second (software-cause) boot.
volatile uint32_t	g_reset_cause_initial = 0U
	Decoded reset cause observed on this boot, captured as soon as ra8_reset_init returns.

Detailed Description

HIL gate for the ra8_reset driver – software-reset round-trip.

Tag

[Ring 6 / APP] {World: S}

Exercises the ra8_reset HAL end-to-end on the bench:

1. POR / cold boot lands here with RSTSR1.SWRF == 0 and the decoded cause is k_ra8_reset_cause_power_on (or some other pre-reset cause, depending on how the chip woke up).
2. The app waits briefly, then calls ra8_reset_software_reset() which writes AIRCR.SYSRESETREQ and the chip reboots.
3. The post-reset boot sees cause == k_ra8_reset_cause_software; the app drops into a tight loop that increments g_reset_cause_loop at ~20 Hz.

The HIL gate uses jlink_memprobe mode (see hil.conf) to sample g_reset_cause_loop twice over a 5 s window and assert it advanced by at least 3. The counter only advances on the second (software-cause) boot, so a passing probe proves:

• ra8_reset_init / ra8_reset_get_cause decode the SWRF flag.
• ra8_reset_software_reset actually triggers SYSRESETREQ.
• The Reset_Handler / SystemInit / main path is alive after a SW reset.

The counter and the captured initial cause are both volatile non-static globals so the linker keeps them visible to J-Link.

Author

Brighton Sikarskie

Date

2026-06-01

Copyright

Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since

0.1.0

Definition in file main.c.

Enumeration Type Documentation

reset_cause_demo_const_t

enum reset_cause_demo_const_t : uint32_t

Internal constants for the reset-cause demo.

Enumerator
k_reset_cause_cpu_hz_at_reset	MOCO ~8.4 MHz before CGC bring-up.
k_reset_cause_settle_ms	Pause before triggering SW reset.
k_reset_cause_loop_period_ms	20 Hz advance for HIL probe.

Definition at line 53 of file main.c.

Function Documentation

internal_reset_cause_panic_halt()

void internal_reset_cause_panic_halt ( void )

static

Park the CPU forever in WFI – used after the SW reset write or if HAL init fails.

Compiled into a tight WFI loop so the chip is idle but observable from J-Link.

Precondition

Caller has finished any work that must happen before park.

IRQs are either disabled or harmless.

Postcondition

CPU spins in WFI; g_reset_cause_loop is no longer advancing.

No further C-level state changes.

Note

Not thread-safe (single CPU).

Since

0.1.0

Definition at line 105 of file main.c.

References RA8_INTERNAL.

Referenced by main().

main()

void main

(

void

)

The application entry point Reset_Handler hands control to.

Returns void, not int. This is a freestanding image: there is no hosted C environment, no process and nothing to report an exit status to. ISO C fixes main at int only for a hosted implementation; for a freestanding one (C23 5.1.2.1) the startup function's name and type are implementation-defined, and this is that definition. Reset_Handler discards no value because there is none to discard, and if main ever does return, startup halts the CPU rather than resuming anything.

The firmware lane is compiled -ffreestanding (see cmake/ra8_add_app.cmake) and the flag and this signature travel together: without it both GCC and clang reject a non-int main (-Wmain / -Wmain-return-type). Do not remove one without the other.

That coupling is why the declaration sits behind __STDC_HOSTED__ == 0, which -ffreestanding sets and a hosted build does not. The guard is not defensive dressing: this header is reachable from host builds (the unit tests compile ra8_core natively), and an unguarded void main(void); makes every hosted translation unit that includes it fail with conflicting types for 'main' against its own ISO int main. The declaration therefore exists exactly where its contract does.

Hosted first-party code – everything under tests/ and tools/ – uses the ISO int main(...) contract instead, because it genuinely does run under an OS that reads the exit status. scripts/checks/check_entry_points.py holds each domain to its own contract (#707).

Declared here, once, for the same reason SystemInit is: every vector_table.c used to restate it as a local extern int32_t main(void);, sixteen copies that no compiler ever compared against the definition – and roughly thirty of them had silently drifted out of agreement with the main they called.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has configured the clock tree and VTOR.

Postcondition

Control does not return; the image runs until reset or halt.

Any value the application wanted to report has been logged, not returned.

Note

Not thread-safe; single-threaded startup context only.

Warning

Only valid while the translation unit is compiled -ffreestanding. A hosted build rejects this signature.

See also

SystemInit()

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + BSP audio then plays blocks.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the playback loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + GPT triple, runs sweep.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the sweep loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART + RMII pins, then ThreadX.

Precondition

Reset_Handler has copied .data and zeroed .bss.

Postcondition

On clean entry the kernel runs the worker thread once.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up clocks + UART, then enters ThreadX.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the kernel runs the worker thread forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up LED, console, SDHI pins, then ThreadX.

Precondition

Reset_Handler has copied .data + zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

CPUCLK0 is raised to the PLL1 target before the kernel starts.

On clean entry the SD card thread runs forever.

On any HAL init failure the function halts in __WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up CGC + USB-FS + UAC1, then enters the iso-IN feed loop forever.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the iso-IN feed loop forever.

On any HAL init failure the function halts in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

SystemInit set VTOR / FPU / priority grouping.

The application entry point Reset_Handler hands control to.

See file header.

Precondition

Boot init has completed.

The secure-boot library's BLXNS into NS image either failed or was skipped (the call site in ra8_trustzone_init is a no-op on host builds).

Postcondition

Diagnostic counter latched, CPU parked in a halt loop.

Function never returns.

Note

Single-threaded entry.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success g_eoh_chapters / g_eoh_crc hold the parsed results, the banner is emitted, and g_eoh_heartbeat advances once per frame.

On any failure g_eoh_err is non-zero and the CPU parks (no heartbeat).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The chapters/ch0-CRC banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success the g_etoc_* result globals hold the parsed TOC values, the banner is emitted, and g_etoc_heartbeat advances once per frame.

On any failure g_etoc_err is non-zero and the CPU parks (no heartbeat).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss; SystemInit set VTOR/FPU.

Postcondition

The shelf scans on the panel; taps open books, browse, and read.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The slab/arena/tile/vmem banner is emitted; the CPU then loops in WFI.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

On success the cache globals are latched and g_pc_heartbeat advances.

On any failure g_pc_err is non-zero and the CPU parks (no heartbeat).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Profiles power modes once a second.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On clean entry the CPU stays in the profile + blink loop.

On any HAL hard error LED2 latches ON.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler has copied .data and zeroed .bss.

The shared board boot files installed the vector table.

Postcondition

The demo has run once and its verdict banner is streaming steadily.

The CPU idles re-emitting the banner (or halts after a fatal init error).

Since

0.1.0

The application entry point Reset_Handler hands control to.

Brings up the clocks, console, SPI, and SD card, then runs the shared ra8_io VFS round-trip over the SD-over-SPI block device. On success it prints the exact PASS banner the HIL runner and ra8_emulator smoke gate scrape for; on any failure it prints FAIL and parks the core.

Precondition

Reset_Handler has copied .data and zeroed .bss.

SystemInit has set VTOR, FPU, and priority grouping.

Postcondition

On a clean run the CPU loops forever after the PASS banner.

On any failure the function prints FAIL and halts in WFI.

Note

Not thread-safe; this is the single-threaded app entry.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Initialises logging and the console, brings up the OSPI NOR volume, runs the erase-before-write round-trip, and prints a single PASS/FAIL verdict line over SCI8 before parking in an infinite loop.

Precondition

SystemInit configured VTOR / FPU / priority grouping.

The OSPI NOR array is present (modelled in ra8_emulator, real on silicon).

Postcondition

Exactly one PASS or FAIL verdict line has been queued on SCI8.

Control parks in an infinite loop; the function never returns.

Note

Single-threaded; runs to the park loop on the main stack.

Since

0.1.0

The application entry point Reset_Handler hands control to.

Precondition

Reset_Handler copied .data and zeroed .bss.

SystemInit set VTOR / FPU / priority grouping.

Postcondition

The page-count + render-hash banner is emitted; the CPU loops in WFI.

Since

0.1.0

Definition at line 112 of file main.c.

References g_reset_cause_initial, g_reset_cause_loop, internal_reset_cause_panic_halt(), k_ra8_ok, k_ra8_reset_cause_software, k_ra8_reset_cause_unknown, k_reset_cause_cpu_hz_at_reset, k_reset_cause_loop_period_ms, k_reset_cause_settle_ms, ra8_delay_ms(), ra8_isr_globals_enable(), ra8_log_info_val, ra8_reset_get_cause(), ra8_reset_init(), ra8_reset_software_reset(), and ra8_time_init().

Variable Documentation

g_reset_cause_initial

volatile uint32_t g_reset_cause_initial = 0U

Decoded reset cause observed on this boot, captured as soon as ra8_reset_init returns.

Cold boot writes the POR value (or whatever cause the chip woke up with); after the SW reset path, this reads k_ra8_reset_cause_software. Useful for debugging a failing HIL probe over J-Link.

Note

Read externally by J-Link only.

Since

0.1.0

Definition at line 88 of file main.c.

Referenced by main().

g_reset_cause_loop

volatile uint32_t g_reset_cause_loop = 0U

HIL-probed counter – advances only after the second (software-cause) boot.

Read externally by hil_jlink_memprobe.sh to assert that the software-reset path completed and the post-reset boot reached the loop in main(). volatile keeps the increment out of the optimiser's hands; non-static keeps the symbol in nm.

Note

Read externally by J-Link only; firmware never reads back.

Since

0.1.0

Definition at line 73 of file main.c.

Referenced by main().