ra8-firmware 0.1.0
Bare-metal firmware for the Renesas RA8 family (RA8D2 / RA8P1)
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esp_heap_caps.h File Reference

ESP-IDF capability-flag compatibility for the esp-hosted port. More...

#include <stdint.h>
Include dependency graph for esp_heap_caps.h:
This graph shows which files directly or indirectly include this file:

Go to the source code of this file.

Enumerations

enum  ra8_esp_hosted_malloc_cap_t : uint32_t {
  MALLOC_CAP_EXEC = 0x00000001U ,
  MALLOC_CAP_32BIT = 0x00000002U ,
  MALLOC_CAP_8BIT = 0x00000004U ,
  MALLOC_CAP_DMA = 0x00000008U ,
  MALLOC_CAP_SPIRAM = 0x00000400U ,
  MALLOC_CAP_INTERNAL = 0x00000800U ,
  MALLOC_CAP_DEFAULT = 0x00001000U
}
 Allocation capability bits, at their ESP-IDF bit positions. More...

Detailed Description

ESP-IDF capability-flag compatibility for the esp-hosted port.

Tag
[Ring 4 / PORT] {World: NS}

ESP-IDF splits an ESP chip's address space into regions with different properties – internal versus external, DMA-reachable or not – and its allocator takes a bitmask saying which properties the caller needs. host/drivers/transport/transport_util.c passes those flags through when it maps esp-hosted's hosted_mem_cap_t onto a concrete allocation.

The RA8D2 has no such split for this port's purposes. Every buffer the transport allocates comes from one fixed ThreadX byte pool carved out of a static array in .bss, which is internal SRAM and is reachable by both the DMAC and the SCI peripheral. So on this target every capability request is satisfiable by the one pool, and the flags are carried for source compatibility rather than steering an allocator decision.

That is stated rather than hidden: the values below keep the upstream bit positions so a flag word logged on this host means the same thing an ESP-IDF reader would expect, and the port's allocator documents that it ignores them.

ESP-IDF also declares heap_caps_malloc here. On this host that function is a static inline in port_esp_hosted_host_os.h instead, because it has to be defined after the g_h vtable declaration and after HOSTED_MEM_ALIGNMENT_64, both of which live there; defining it here would mean a second spelling of the sixty-four-byte cache-line alignment. Every vendored translation unit that calls it reaches that header, so the resolution is the same one an ESP-IDF host gets.

Since
0.1.0

Definition in file esp_heap_caps.h.

Enumeration Type Documentation

◆ ra8_esp_hosted_malloc_cap_t

enum ra8_esp_hosted_malloc_cap_t : uint32_t

Allocation capability bits, at their ESP-IDF bit positions.

Only the bits the vendored tree actually names are defined. Keeping the upstream positions matters because the flags are combined with bitwise or at the call sites and are occasionally logged; a re-numbered set would still compile and would still be wrong in a trace.

The enumerator spellings are fixed by ESP-IDF, so they do not follow the project's k_ prefix convention.

Invariant
Each value is a single distinct bit.
Example:
void *p = allocate(size, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
@ MALLOC_CAP_DMA
Reachable by a DMA engine.
@ MALLOC_CAP_INTERNAL
On-chip SRAM.
See also
ra8_esp_hosted_port_init
Since
0.1.0
Enumerator
MALLOC_CAP_EXEC 

Memory the core can fetch from.

MALLOC_CAP_32BIT 

Word-accessible only.

MALLOC_CAP_8BIT 

Byte-accessible.

MALLOC_CAP_DMA 

Reachable by a DMA engine.

MALLOC_CAP_SPIRAM 

Off-chip PSRAM on an ESP part.

MALLOC_CAP_INTERNAL 

On-chip SRAM.

MALLOC_CAP_DEFAULT 

No particular requirement.

Definition at line 68 of file esp_heap_caps.h.