Shared engine-access table definition (see emu_engine.h). More...

#include "emu_engine.h"

Include dependency graph for emu_engine.c:

Functions
void	emu_seam_request_relaunch (void)
	Implementation of emu_seam_request_relaunch() – set the latch.
bool	emu_seam_take_relaunch (void)
	Implementation of emu_seam_take_relaunch() – read + clear.

Variables
const int	k_arm_reg_id [16]
	ARM register index (0..15) -> Unicorn register id.
static bool	s_seam_relaunch
	Set by a C-seam to relaunch WITHOUT consuming a chunk.

Detailed Description

Shared engine-access table definition (see emu_engine.h).

Holds the one definition of the ARM register-index -> Unicorn register-id mapping the instruction seams share; the inline accessors live entirely in emu_engine.h.

Copyright: Copyright (c) 2026 Brighton Sikarskie SPDX-License-Identifier: MIT

Since: 0.1.0

Definition in file emu_engine.c.

Function Documentation

◆ emu_seam_request_relaunch()

void emu_seam_request_relaunch ( void )

Implementation of emu_seam_request_relaunch() – set the latch.

Mark the pending engine stop as a zero-time seam relaunch.

Definition at line 52 of file emu_engine.c.

References s_seam_relaunch.

Referenced by emulate_div0_patched(), and internal_on_sdmmc_read_block().

◆ emu_seam_take_relaunch()

bool emu_seam_take_relaunch ( void )

Implementation of emu_seam_take_relaunch() – read + clear.

Consume the zero-time seam-relaunch latch.

Definition at line 58 of file emu_engine.c.

References s_seam_relaunch.

Referenced by internal_run_inner_check_stops().

Variable Documentation

◆ k_arm_reg_id

const int k_arm_reg_id[16]

Initial value:

                       = {
  UC_ARM_REG_R0,
  UC_ARM_REG_R1,
  UC_ARM_REG_R2,
  UC_ARM_REG_R3,
  UC_ARM_REG_R4,
  UC_ARM_REG_R5,
  UC_ARM_REG_R6,
  UC_ARM_REG_R7,
  UC_ARM_REG_R8,
  UC_ARM_REG_R9,
  UC_ARM_REG_R10,
  UC_ARM_REG_R11,
  UC_ARM_REG_R12,
  UC_ARM_REG_SP,
  UC_ARM_REG_LR,
  UC_ARM_REG_PC,
}

ARM register index (0..15) -> Unicorn register id.

Unicorn's UC_ARM_REG_* enum is NOT contiguous (UC_ARM_REG_R0 + n != UC_ARM_REG_Rn), so every instruction seam that decodes a 4-bit register field maps it through this table. PC(15)/SP(13)/LR(14) are never CSx destinations in practice but are mapped for completeness.

Note: Read-only lookup table; safe to share across every module.

Warning: Do not index with a value above 15 (a decoded 4-bit field cannot produce one).

Since: 0.1.0

Definition at line 17 of file emu_engine.c.

Referenced by emulate_div0_patched(), emulate_long_shift_reg(), internal_emulate_cond_select(), internal_emulate_lob(), internal_long_shift_amount(), internal_long_shift_begin(), internal_long_shift_commit(), and internal_mve_mem_exec().

◆ s_seam_relaunch

bool s_seam_relaunch

static

Set by a C-seam to relaunch WITHOUT consuming a chunk.

A block-serve or emulated-instruction seam stops emulation to return to the caller; left alone the inner run loop would treat that clean stop as a full instruction budget elapsing and advance SysTick + charge a chunk. This latch marks the stop as a zero-time seam relaunch – the inner loop just re-enters at the returned PC, exactly like the exception-return path.

Note: Single-threaded run loop only; cleared by each take.

Warning: Producers must stop the engine right after setting it.

Since: 0.1.0

Definition at line 49 of file emu_engine.c.

Referenced by emu_seam_request_relaunch(), and emu_seam_take_relaunch().

Functions