board_periph_timer.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_periph_block.h"
#include "emu_host_io_internal.h"

typedef enum : uint64_t {
  k_agt_base    = 0x40221000UL,   
  k_agt_stride  = 0x100UL,        
  k_agt_count   = 10UL,           
  k_agt_span    = 0x100UL * 10UL, 
  k_agt_off_agt = 0x00UL,         
  k_agt_off_cma = 0x02UL,         
  k_agt_off_cmb = 0x04UL,         
  k_agt_off_cr  = 0x08UL,         
  k_agt_off_mr1 = 0x09UL,         
} agt_map_t;

typedef enum : uint64_t {
  k_gpt_base      = 0x40322000UL,   
  k_gpt_stride    = 0x100UL,        
  k_gpt_count     = 14UL,           
  k_gpt_span      = 0x100UL * 14UL, 
  k_gpt_off_gtstr = 0x04UL,         
  k_gpt_off_gtstp = 0x08UL,         
  k_gpt_off_gtclr = 0x0CUL,         
  k_gpt_off_gtcr  = 0x2CUL,         
  k_gpt_off_gtst  = 0x3CUL,         
  k_gpt_off_gtcnt = 0x48UL,         
  k_gpt_off_gtpr  = 0x64UL,         
} gpt_map_t;

typedef enum : uint32_t {
  k_u16_max = 0xFFFFU, 
} timer_field_t;

typedef enum : uint32_t {
  k_agtcr_tstart = 0x01U, 
  k_agtcr_tcstf  = 0x02U, 
  k_agtcr_tundf  = 0x20U, 
  k_agtcr_tcmaf  = 0x40U, 
  k_agtcr_tcmbf  = 0x80U, 
} agtcr_bit_t;

typedef enum : uint32_t {
  k_gtcr_cst   = 0x00000001U, 
  k_gtst_tcfa  = 0x00000001U, 
  k_gtst_tcfpo = 0x00000040U, 
  k_gtst_tcfpu = 0x00000080U, 
} gpt_bit_t;

typedef enum : uint16_t {
  k_event_gpt0_ovf = 0x0C1U, 
  k_event_agt0_int = 0x0DFU, 
} elc_event_t;

typedef enum : uint32_t {
  k_agt_step_per_chunk = 0x0800U,     
  k_gpt_step_per_chunk = 0x00004001U, 
} timer_tune_t;

typedef struct {
  uint16_t counter;    
  uint16_t reload;     
  uint16_t cmpa;       
  uint16_t cmpb;       
  uint8_t  cr;         
  uint8_t  mr1;        
  uint32_t underflows; 
} agt_state_t;

typedef struct {
  uint32_t cnt;       
  uint32_t period;    
  uint32_t cr;        
  uint32_t st;        
  uint32_t overflows; 
} gpt_state_t;
 
static agt_state_t s_agt[k_agt_count];
static gpt_state_t s_gpt[k_gpt_count];
 
/* =============================================================================
 * AGT timer model -- 16-bit reloading down-counter (ra8_agt.c semantics).
 * =============================================================================
 */

RA8_INTERNAL static uint64_t internal_agt_reg_read(uint32_t ch, uint64_t off)
{
  const agt_state_t* a = &s_agt[ch];
  if (off == (uint64_t)k_agt_off_agt) {
    return a->counter;
  }
  if (off == (uint64_t)k_agt_off_cma) {
    return a->cmpa;
  }
  if (off == (uint64_t)k_agt_off_cmb) {
    return a->cmpb;
  }
  if (off == (uint64_t)k_agt_off_cr) {
    return a->cr;
  }
  if (off == (uint64_t)k_agt_off_mr1) {
    return a->mr1;
  }
  return 0U;
}

RA8_INTERNAL static void internal_agt_reg_write(uint32_t ch, uint64_t off, uint32_t value)
{
  agt_state_t* a = &s_agt[ch];
  if (off == (uint64_t)k_agt_off_agt) {
    a->counter = (uint16_t)value; /* AGT write both reloads and seeds count */
    a->reload  = (uint16_t)value;
  } else if (off == (uint64_t)k_agt_off_cma) {
    a->cmpa = (uint16_t)value;
  } else if (off == (uint64_t)k_agt_off_cmb) {
    a->cmpb = (uint16_t)value;
  } else if (off == (uint64_t)k_agt_off_cr) {
    /* TUNDF/TCMAF/TCMBF are write-0-to-clear (ra8_agt clears by writing 0);
     * TSTART is RW. TCSTF tracks TSTART. */
    const uint8_t status_keep =
      (uint8_t)(a->cr & (uint8_t)value & (uint8_t)(k_agtcr_tundf | k_agtcr_tcmaf | k_agtcr_tcmbf));
    const uint8_t start = (uint8_t)(value & (uint8_t)k_agtcr_tstart);
    a->cr = (uint8_t)(start | (start != 0U ? (uint8_t)k_agtcr_tcstf : 0U) | status_keep);
  } else if (off == (uint64_t)k_agt_off_mr1) {
    a->mr1 = (uint8_t)value;
  }
}

RA8_INTERNAL static void internal_agt_tick_channel(uc_engine* uc, uint32_t ch)
{
  agt_state_t* a = &s_agt[ch];
  if ((a->cr & (uint8_t)k_agtcr_tstart) == 0U) {
    return; /* stopped: counter holds */
  }
  const uint32_t step = (uint32_t)k_agt_step_per_chunk;
  if (a->counter > step) {
    a->counter = (uint16_t)(a->counter - step);
    return;
  }
  /* Underflow: reload and set TUNDF (and TCMAF if compare-match A is armed). */
  const uint32_t span    = (uint32_t)a->reload + 1U;
  const uint32_t deficit = step - a->counter;
  a->counter             = (uint16_t)(a->reload - ((deficit - 1U) % span));
  a->cr |= (uint8_t)k_agtcr_tundf;
  a->underflows++;
  if (ch == 0U) {
    board_periph_icu_raise_event(uc, (uint16_t)k_event_agt0_int);
  }
}

RA8_INTERNAL static uint64_t internal_agt_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)size;
  const uint32_t ch = (uint32_t)((addr - (uint64_t)k_agt_base) / (uint64_t)k_agt_stride);
  return internal_agt_reg_read(ch, (addr - (uint64_t)k_agt_base) % (uint64_t)k_agt_stride);
}

RA8_INTERNAL static void
internal_agt_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)uc;
  (void)size;
  const uint32_t ch = (uint32_t)((addr - (uint64_t)k_agt_base) / (uint64_t)k_agt_stride);
  internal_agt_reg_write(ch,
                         (addr - (uint64_t)k_agt_base) % (uint64_t)k_agt_stride,
                         (uint32_t)value);
}
 
/* =============================================================================
 * GPT timer model -- 32-bit saw up-counter (ra8_gpt.c semantics).
 * =============================================================================
 */

RA8_INTERNAL static uint64_t internal_gpt_reg_read(uint32_t ch, uint64_t off)
{
  const gpt_state_t* g = &s_gpt[ch];
  if (off == (uint64_t)k_gpt_off_gtcnt) {
    return g->cnt;
  }
  if (off == (uint64_t)k_gpt_off_gtpr) {
    return g->period;
  }
  if (off == (uint64_t)k_gpt_off_gtcr) {
    return g->cr;
  }
  if (off == (uint64_t)k_gpt_off_gtst) {
    return g->st;
  }
  return 0U; /* GTWP / GTSTR / GTSTP / GTCLR read as 0 in this model */
}

RA8_INTERNAL static void internal_gpt_reg_write(uint32_t ch, uint64_t off, uint32_t value)
{
  gpt_state_t* g = &s_gpt[ch];
  if (off == (uint64_t)k_gpt_off_gtcnt) {
    g->cnt = value;
  } else if (off == (uint64_t)k_gpt_off_gtpr) {
    g->period = value;
  } else if (off == (uint64_t)k_gpt_off_gtcr) {
    g->cr = value; /* CST (bit0) starts / stops the count */
  } else if (off == (uint64_t)k_gpt_off_gtstr) {
    if ((value & 1U) != 0U) {
      g->cr |= (uint32_t)k_gtcr_cst;
    }
  } else if (off == (uint64_t)k_gpt_off_gtstp) {
    if ((value & 1U) != 0U) {
      g->cr &= ~(uint32_t)k_gtcr_cst;
    }
  } else if (off == (uint64_t)k_gpt_off_gtclr) {
    if ((value & 1U) != 0U) {
      g->cnt = 0U;
    }
  } else if (off == (uint64_t)k_gpt_off_gtst) {
    /* GTST bits are cleared by writing the value back with target bits zero
     * (ra8_gpt_clear_status), so the model keeps only bits still set. */
    g->st &= value;
  }
}

RA8_INTERNAL static void internal_gpt_tick_channel(uc_engine* uc, uint32_t ch)
{
  gpt_state_t* g = &s_gpt[ch];
  if ((g->cr & (uint32_t)k_gtcr_cst) == 0U) {
    return; /* stopped */
  }
  const uint32_t period = (g->period == 0U) ? (uint32_t)k_u16_max : g->period;
  const uint32_t step   = (uint32_t)k_gpt_step_per_chunk;
  if ((g->cnt + step) <= period) {
    g->cnt += step;
    return;
  }
  /* Overflow past GTPR in saw mode: wrap and set TCFPO. */
  g->cnt = (uint32_t)((g->cnt + step) - period - 1U);
  g->st |= (uint32_t)k_gtst_tcfpo;
  g->overflows++;
  if (ch == 0U) {
    board_periph_icu_raise_event(uc, (uint16_t)k_event_gpt0_ovf);
  }
}

RA8_INTERNAL static uint64_t internal_gpt_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)size;
  const uint32_t ch = (uint32_t)((addr - (uint64_t)k_gpt_base) / (uint64_t)k_gpt_stride);
  return internal_gpt_reg_read(ch, (addr - (uint64_t)k_gpt_base) % (uint64_t)k_gpt_stride);
}

RA8_INTERNAL static void
internal_gpt_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)uc;
  (void)size;
  const uint32_t ch = (uint32_t)((addr - (uint64_t)k_gpt_base) / (uint64_t)k_gpt_stride);
  internal_gpt_reg_write(ch,
                         (addr - (uint64_t)k_gpt_base) % (uint64_t)k_gpt_stride,
                         (uint32_t)value);
}
 
/* =============================================================================
 * Shared tick / reset / report for both timer families (AGT then GPT).
 * =============================================================================
 */

RA8_INTERNAL static void internal_timer_tick(uc_engine* uc)
{
  for (uint32_t ch = 0U; ch < (uint32_t)k_agt_count; ch++) {
    internal_agt_tick_channel(uc, ch);
  }
  for (uint32_t ch = 0U; ch < (uint32_t)k_gpt_count; ch++) {
    internal_gpt_tick_channel(uc, ch);
  }
}

RA8_INTERNAL static void internal_timer_reset(void)
{
  for (uint32_t i = 0U; i < (uint32_t)k_agt_count; i++) {
    s_agt[i] = (agt_state_t){};
  }
  for (uint32_t i = 0U; i < (uint32_t)k_gpt_count; i++) {
    s_gpt[i] = (gpt_state_t){};
  }
}

RA8_INTERNAL static void internal_timer_report(void)
{
  for (uint32_t ch = 0U; ch < (uint32_t)k_agt_count; ch++) {
    if (s_agt[ch].underflows > 0U) {
      (void)priv_emu_io_errf("  AGT%u          : counter=0x%04X underflows=%u (running=%s)\n",
                             ch,
                             s_agt[ch].counter,
                             s_agt[ch].underflows,
                             (s_agt[ch].cr & (uint8_t)k_agtcr_tstart) ? "yes" : "no");
    }
  }
  for (uint32_t ch = 0U; ch < (uint32_t)k_gpt_count; ch++) {
    if (s_gpt[ch].overflows > 0U) {
      (void)priv_emu_io_errf("  GPT%u          : cnt=0x%08X period=0x%08X overflows=%u\n",
                             ch,
                             s_gpt[ch].cnt,
                             s_gpt[ch].period,
                             s_gpt[ch].overflows);
    }
  }
}
 
/* The AGT descriptor carries the tick / reset / report that cover BOTH timer
 * families, so the historical AGT-then-GPT order is preserved; the GPT
 * descriptor only owns its own register window. Both share the timer tick
 * order, and registration order between them is irrelevant. */

static const board_periph_block_t s_k_agt_block = {
  .base   = (uint64_t)k_agt_base,
  .span   = (uint64_t)k_agt_span,
  .order  = (uint32_t)k_block_order_timer,
  .read   = internal_agt_read,
  .write  = internal_agt_write,
  .tick   = internal_timer_tick,
  .reset  = internal_timer_reset,
  .report = internal_timer_report,
  .name   = "AGT",
};

static const board_periph_block_t s_k_gpt_block = {
  .base   = (uint64_t)k_gpt_base,
  .span   = (uint64_t)k_gpt_span,
  .order  = (uint32_t)k_block_order_timer,
  .read   = internal_gpt_read,
  .write  = internal_gpt_write,
  .tick   = nullptr,
  .reset  = nullptr,
  .report = nullptr,
  .name   = "GPT",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_board_periph_timer_register(void)
{
  board_periph_register_block(&s_k_agt_block);
  board_periph_register_block(&s_k_gpt_block);
}