board_periph_npu.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_console.h"
#include "board_periph_block.h"
#include "emu_host_io_internal.h"
#include "ra8_npu_fake_cmd.h"

typedef enum : uint64_t {
  k_npu_base       = 0x40140000UL,   
  k_npu_span       = 0x1000UL,       
  k_npu_words      = 0x1000UL / 4UL, 
  k_npu_off_id     = 0x0000UL,       
  k_npu_off_status = 0x0004UL,       
  k_npu_off_cmd    = 0x0008UL,       
  k_npu_off_reset  = 0x000CUL,       
  k_npu_off_qbase  = 0x0010UL,       
  k_npu_off_qsize  = 0x0020UL,       
  k_npu_off_basep0 = 0x0080UL,       
} npu_map_t;

typedef enum : uint32_t {
  k_npu_reg_hi_off   = 0x0004U, 
  k_npu_basep_stride = 0x0008U, 
  k_npu_region_count = 8U,      
  k_npu_addr_hi_pos  = 32U,     
} npu_geom_t;

typedef enum : uint32_t {
  k_npu_cmd_run_bit       = 0U, 
  k_npu_cmd_clear_irq_bit = 1U, 
  k_npu_status_state_bit  = 0U, 
  k_npu_status_irq_bit    = 1U, 
  k_npu_status_buserr_bit = 2U, 
  k_npu_status_reset_bit  = 3U, 
  k_npu_status_parse_bit  = 4U, 
  k_npu_status_cmdend_bit = 5U, 
} npu_bit_t;

typedef enum : uint32_t {
  k_npu_id_arch_major_pos = 28U, 
  k_npu_id_arch_minor_pos = 20U, 
  k_npu_id_arch_patch_pos = 16U, 
  k_npu_id_product_pos    = 12U, 
} npu_id_pos_t;

typedef enum : uint32_t {
  k_npu_id_arch_major  = 1U, 
  k_npu_id_arch_minor  = 0U, 
  k_npu_id_arch_patch  = 6U, 
  k_npu_id_product_u55 = 0U, 
} npu_id_val_t;

typedef enum : uint32_t {
  k_npu_event_irq   = 0x067U, 
  k_npu_block_order = 15U,    
} npu_misc_t;

typedef enum : uint32_t {
  k_npu_chunk_bytes = 256U,        
  k_npu_max_chunks  = 16U,         
  k_npu_fnv_offset  = 0x811C9DC5U, 
  k_npu_fnv_prime   = 0x01000193U, 
  k_npu_line_cap    = 64U,         
} npu_exec_const_t;

typedef enum : uint8_t {
  k_npu_dec_ok    = 0U, 
  k_npu_dec_parse = 1U, 
  k_npu_dec_bus   = 2U, 
} npu_dec_t;

typedef struct {
  uint32_t op;    
  uint32_t src;   
  uint32_t dst;   
  uint32_t count; 
  uint32_t konst; 
} npu_cmd_t;

typedef struct {
  uint32_t reg[k_npu_words]; 
  uint32_t status;           
  uint32_t jobs;             
  uint32_t faults;           
  uint32_t last_op;          
  uint32_t last_bytes;       
  uint32_t last_check;       
  uint32_t reads;            
  uint32_t writes;           
} npu_state_t;
 
static npu_state_t s_npu;

static const uint32_t s_npu_id =
  ((uint32_t)k_npu_id_arch_major << (uint32_t)k_npu_id_arch_major_pos) |
  ((uint32_t)k_npu_id_arch_minor << (uint32_t)k_npu_id_arch_minor_pos) |
  ((uint32_t)k_npu_id_arch_patch << (uint32_t)k_npu_id_arch_patch_pos) |
  ((uint32_t)k_npu_id_product_u55 << (uint32_t)k_npu_id_product_pos);

RA8_INTERNAL static uint32_t internal_npu_word(uint64_t off)
{
  return (uint32_t)(off >> 2U);
}

RA8_INTERNAL static uint64_t internal_npu_reg64(uint64_t lo_off)
{
  const uint32_t lo = s_npu.reg[internal_npu_word(lo_off)];
  const uint32_t hi = s_npu.reg[internal_npu_word(lo_off + (uint64_t)k_npu_reg_hi_off)];
  return (uint64_t)lo | ((uint64_t)hi << (uint32_t)k_npu_addr_hi_pos);
}

RA8_INTERNAL static uint64_t internal_npu_region_base(uint32_t idx)
{
  const uint64_t lo_off =
    (uint64_t)k_npu_off_basep0 + ((uint64_t)idx * (uint64_t)k_npu_basep_stride);
  return internal_npu_reg64(lo_off);
}

RA8_INTERNAL static bool internal_npu_guest_word(uc_engine* uc, uint64_t addr, uint32_t* out)
{
  uint8_t b[4] = {};
  if (emu_mem_read(uc, addr, b, sizeof(b)) != UC_ERR_OK) {
    return false;
  }
  /* Little-endian assembly over the fixed 4-byte buffer -- the loop keeps the
   * byte shift a named multiple (i * 8U) instead of a bare 24U high-byte
   * literal, and is statically bounded by sizeof(b) (NASA P10 Rule 2). */
  *out = 0U;
  for (uint32_t i = 0U; i < sizeof(b); ++i) {
    *out |= (uint32_t)b[i] << (i * 8U);
  }
  return true;
}

RA8_INTERNAL static void internal_npu_fault(uint32_t status_bit)
{
  s_npu.status = ((uint32_t)1U << status_bit) | ((uint32_t)1U << (uint32_t)k_npu_status_irq_bit);
  s_npu.faults++;
}

RA8_INTERNAL static npu_dec_t internal_npu_decode(uc_engine* uc, npu_cmd_t* out)
{
  const uint64_t qbase = internal_npu_reg64((uint64_t)k_npu_off_qbase);
  const uint32_t qsize = s_npu.reg[internal_npu_word((uint64_t)k_npu_off_qsize)];
  if (qsize < (uint32_t)k_ra8_npu_fake_header_bytes) {
    return k_npu_dec_parse;
  }
  uint32_t w[k_ra8_npu_fake_word_num] = {};
  for (uint32_t i = 0U; i < (uint32_t)k_ra8_npu_fake_word_num; i++) {
    if (!internal_npu_guest_word(uc, qbase + ((uint64_t)i * 4UL), &w[i])) {
      return k_npu_dec_bus;
    }
  }
  if ((w[k_ra8_npu_fake_word_op] & (uint32_t)k_ra8_npu_fake_magic_mask) !=
      (uint32_t)k_ra8_npu_fake_magic) {
    return k_npu_dec_parse; /* Real Vela stream / not ours: cannot interpret. */
  }
  out->op    = w[k_ra8_npu_fake_word_op] & (uint32_t)k_ra8_npu_fake_op_mask;
  out->src   = w[k_ra8_npu_fake_word_src];
  out->dst   = w[k_ra8_npu_fake_word_dst];
  out->count = w[k_ra8_npu_fake_word_count];
  out->konst = w[k_ra8_npu_fake_word_const];
  const bool bad_region =
    (out->src >= (uint32_t)k_npu_region_count) || (out->dst >= (uint32_t)k_npu_region_count);
  const bool bad_count = (out->count == 0U) || (out->count > (uint32_t)k_ra8_npu_fake_max_bytes);
  if (bad_region || bad_count) {
    return k_npu_dec_parse;
  }
  return k_npu_dec_ok;
}

RA8_INTERNAL static bool internal_npu_apply(uc_engine*       uc,
                                            const npu_cmd_t* c,
                                            uint64_t         src,
                                            uint64_t         dst,
                                            uint32_t*        out_check)
{
  uint8_t  buf[k_npu_chunk_bytes] = {};
  uint32_t check                  = (uint32_t)k_npu_fnv_offset;
  uint32_t done                   = 0U;
  for (uint32_t chunk = 0U; chunk < (uint32_t)k_npu_max_chunks; chunk++) {
    if (done >= c->count) {
      break;
    }
    uint32_t n = c->count - done;
    if (n > (uint32_t)k_npu_chunk_bytes) {
      n = (uint32_t)k_npu_chunk_bytes;
    }
    if (emu_mem_read(uc, src + done, buf, n) != UC_ERR_OK) {
      return false;
    }
    if (c->op == (uint32_t)k_ra8_npu_fake_op_addk) {
      for (uint32_t i = 0U; i < n; i++) {
        buf[i] = (uint8_t)((buf[i] + c->konst) & (uint32_t)k_ra8_npu_fake_byte_mask);
      }
    }
    if (emu_mem_write(uc, dst + done, buf, n) != UC_ERR_OK) {
      return false;
    }
    for (uint32_t i = 0U; i < n; i++) {
      check = (check ^ (uint32_t)buf[i]) * (uint32_t)k_npu_fnv_prime;
    }
    done += n;
  }
  *out_check = check;
  return true;
}

RA8_INTERNAL static const char* internal_npu_op_name(uint32_t op)
{
  if (op == (uint32_t)k_ra8_npu_fake_op_copy) {
    return "copy";
  }
  if (op == (uint32_t)k_ra8_npu_fake_op_addk) {
    return "add-const";
  }
  return "unknown";
}

RA8_INTERNAL static void internal_npu_console_job(const npu_cmd_t* c, uint32_t check)
{
  char ln[k_npu_line_cap];
  (void)snprintf(ln,
                 sizeof(ln),
                 "NPU %s r%u->r%u %uB check=0x%08X",
                 internal_npu_op_name(c->op),
                 (unsigned)c->src,
                 (unsigned)c->dst,
                 (unsigned)c->count,
                 (unsigned)check);
  board_console_push(k_board_console_ch_dma, ln);
}

RA8_INTERNAL static void internal_npu_execute(uc_engine* uc)
{
  npu_cmd_t       c   = {};
  const npu_dec_t dec = internal_npu_decode(uc, &c);
  if (dec == k_npu_dec_bus) {
    internal_npu_fault((uint32_t)k_npu_status_buserr_bit);
    return;
  }
  if (dec != k_npu_dec_ok) {
    internal_npu_fault((uint32_t)k_npu_status_parse_bit);
    return;
  }
  const uint64_t src = internal_npu_region_base(c.src);
  const uint64_t dst = internal_npu_region_base(c.dst);
  if ((src == 0U) || (dst == 0U)) {
    internal_npu_fault((uint32_t)k_npu_status_parse_bit);
    return;
  }
  uint32_t check = 0U;
  if (!internal_npu_apply(uc, &c, src, dst, &check)) {
    internal_npu_fault((uint32_t)k_npu_status_buserr_bit);
    return;
  }
  s_npu.status = ((uint32_t)1U << (uint32_t)k_npu_status_cmdend_bit) |
                 ((uint32_t)1U << (uint32_t)k_npu_status_irq_bit);
  s_npu.jobs++;
  s_npu.last_op    = c.op;
  s_npu.last_bytes = c.count;
  s_npu.last_check = check;
  board_periph_icu_raise_event(uc, (uint16_t)k_npu_event_irq);
  internal_npu_console_job(&c, check);
}

RA8_INTERNAL static void internal_npu_on_cmd(uc_engine* uc, uint32_t value)
{
  if ((value & ((uint32_t)1U << (uint32_t)k_npu_cmd_clear_irq_bit)) != 0U) {
    s_npu.status &= ~((uint32_t)1U << (uint32_t)k_npu_status_irq_bit);
  }
  if ((value & ((uint32_t)1U << (uint32_t)k_npu_cmd_run_bit)) != 0U) {
    internal_npu_execute(uc);
  }
}

RA8_INTERNAL static uint64_t internal_npu_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)size;
  const uint64_t off = addr - (uint64_t)k_npu_base;
  if (off >= (uint64_t)k_npu_span) {
    return 0U;
  }
  s_npu.reads++;
  if (off == (uint64_t)k_npu_off_id) {
    return (uint64_t)s_npu_id;
  }
  if (off == (uint64_t)k_npu_off_status) {
    return (uint64_t)s_npu.status; /* STATUS.reset stays 0: reset is instant. */
  }
  return (uint64_t)s_npu.reg[internal_npu_word(off)];
}

RA8_INTERNAL static void
internal_npu_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)size;
  const uint64_t off = addr - (uint64_t)k_npu_base;
  if (off >= (uint64_t)k_npu_span) {
    return;
  }
  s_npu.writes++;
  s_npu.reg[internal_npu_word(off)] = (uint32_t)value;
  if (off == (uint64_t)k_npu_off_cmd) {
    internal_npu_on_cmd(uc, (uint32_t)value);
    return;
  }
  if (off == (uint64_t)k_npu_off_reset) {
    s_npu.status = 0U; /* Reset discards job state; STATUS.reset reads 0. */
  }
}

RA8_INTERNAL static void internal_npu_reset(void)
{
  s_npu = (npu_state_t){};
}

RA8_INTERNAL static void internal_npu_report(void)
{
  if ((s_npu.jobs == 0U) && (s_npu.faults == 0U)) {
    if ((s_npu.reads != 0U) || (s_npu.writes != 0U)) {
      (void)priv_emu_io_errf("  NPU(Ethos-U55): window touched r=%u w=%u -- no job kicked\n",
                             s_npu.reads,
                             s_npu.writes);
    }
    return;
  }
  (void)priv_emu_io_errf("  NPU(Ethos-U55): jobs=%u faults=%u last=%s bytes=%u check=0x%08X"
                         " (ra8_emulator stand-in, not Vela)\n",
                         s_npu.jobs,
                         s_npu.faults,
                         internal_npu_op_name(s_npu.last_op),
                         s_npu.last_bytes,
                         s_npu.last_check);
}

static const board_periph_block_t s_k_npu_block = {
  .base   = (uint64_t)k_npu_base,
  .span   = (uint64_t)k_npu_span,
  .order  = (uint32_t)k_npu_block_order,
  .read   = internal_npu_read,
  .write  = internal_npu_write,
  .tick   = nullptr,
  .reset  = internal_npu_reset,
  .report = internal_npu_report,
  .name   = "NPU",
  .device = k_board_block_dev_ra8p1,
};

[[gnu::constructor]] RA8_INTERNAL static void internal_npu_block_register(void)
{
  board_periph_register_block(&s_k_npu_block);
}