board_periph_ipc.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_periph_block.h"
#include "emu_host_io_internal.h"

typedef enum : uint32_t {
  k_ipc_block_order = 62U, 
} ipc_order_t;

typedef enum : uint64_t {
  k_ipc_base = 0x40020000UL, 
  k_ipc_span = 0x140UL,      
} ipc_geom_t;

typedef enum : uint64_t {
  k_ipc_ch0_off   = 0xC0UL, 
  k_ipc_ch_stride = 0x20UL, 
  k_ipc_reg_sta   = 0x00UL, 
  k_ipc_reg_iset  = 0x04UL, 
  k_ipc_reg_txd   = 0x08UL, 
  k_ipc_reg_rxd   = 0x0CUL, 
  k_ipc_reg_clr   = 0x10UL, 
} ipc_reg_off_t;

typedef enum : uint32_t {
  k_ipc_ch_count   = 4U, 
  k_ipc_unit_split = 2U, 
  k_ipc_fifo_depth = 4U, 
} ipc_chan_t;

typedef enum : uint32_t {
  k_ipc_sta_irq_mask = 0x000000FFU, 
  k_ipc_sta_rdy      = 0x00010000U, 
  k_ipc_sta_full     = 0x00020000U, 
  k_ipc_sta_rerr     = 0x01000000U, 
  k_ipc_sta_ferr     = 0x02000000U, 
  k_ipc_clr_rst      = 0x00010000U, 
  k_ipc_clr_rclr     = 0x01000000U, 
  k_ipc_clr_fclr     = 0x02000000U, 
  k_ipc0_irq_event   = 0x05BU,      
  k_ipc1_irq_event   = 0x05CU,      
} ipc_status_t;

typedef struct {
  uint32_t word[k_ipc_fifo_depth]; 
  uint32_t rd;                     
  uint32_t count;                  
  bool     rerr;                   
  bool     ferr;                   
} ipc_fifo_t;

typedef struct {
  uint32_t   sta[k_ipc_ch_count];  
  ipc_fifo_t fifo[k_ipc_ch_count]; 
  uint32_t   sends;                
  uint32_t   wakes;                
  uint32_t   pushes;               
  uint32_t   pops;                 
} ipc_state_t;

static ipc_state_t s_ipc;
 
/* =============================================================================
 * Channel / register decode.
 * =============================================================================
 */

RA8_INTERNAL static bool internal_ipc_decode(uint64_t off, uint32_t* ch, uint32_t* reg)
{
  if (off < (uint64_t)k_ipc_ch0_off) {
    return false;
  }
  const uint64_t rel     = off - (uint64_t)k_ipc_ch0_off;
  const uint32_t channel = (uint32_t)(rel / (uint64_t)k_ipc_ch_stride);
  if (channel >= (uint32_t)k_ipc_ch_count) {
    return false;
  }
  *ch  = channel;
  *reg = (uint32_t)(rel % (uint64_t)k_ipc_ch_stride);
  return true;
}
 
/* =============================================================================
 * MMIO read / write.
 * =============================================================================
 */

RA8_INTERNAL static uint32_t internal_ipc_sta_value(uint32_t ch)
{
  const ipc_fifo_t* f   = &s_ipc.fifo[ch];
  uint32_t          sta = s_ipc.sta[ch];
  if (f->count > 0U) {
    sta |= (uint32_t)k_ipc_sta_rdy;
  }
  if (f->count >= (uint32_t)k_ipc_fifo_depth) {
    sta |= (uint32_t)k_ipc_sta_full;
  }
  if (f->rerr) {
    sta |= (uint32_t)k_ipc_sta_rerr;
  }
  if (f->ferr) {
    sta |= (uint32_t)k_ipc_sta_ferr;
  }
  return sta;
}

RA8_INTERNAL static uint32_t internal_ipc_fifo_pop(uint32_t ch)
{
  ipc_fifo_t* f = &s_ipc.fifo[ch];
  if (f->count == 0U) {
    f->rerr = true; /* read-while-empty: latch RERR, data undefined (0). */
    return 0U;
  }
  const uint32_t w = f->word[f->rd];
  f->rd            = (f->rd + 1U) % (uint32_t)k_ipc_fifo_depth;
  f->count--;
  s_ipc.pops++;
  return w;
}

RA8_INTERNAL static uint64_t internal_ipc_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)size;
  const uint64_t off = addr - (uint64_t)k_ipc_base;
  uint32_t       ch  = 0U;
  uint32_t       reg = 0U;
  if (internal_ipc_decode(off, &ch, &reg)) {
    if (reg == (uint32_t)k_ipc_reg_sta) {
      return (uint64_t)internal_ipc_sta_value(ch);
    }
    if (reg == (uint32_t)k_ipc_reg_rxd) {
      return (uint64_t)internal_ipc_fifo_pop(ch);
    }
  }
  /* Semaphores and the NMI window are not modelled: read as 0. */
  return 0U;
}

RA8_INTERNAL static void internal_ipc_fifo_push(uint32_t ch, uint32_t value)
{
  ipc_fifo_t* f = &s_ipc.fifo[ch];
  if (f->count >= (uint32_t)k_ipc_fifo_depth) {
    f->ferr = true; /* write-while-full: latch FERR, drop the word. */
    return;
  }
  f->word[(f->rd + f->count) % (uint32_t)k_ipc_fifo_depth] = value;
  f->count++;
  s_ipc.pushes++;
}

RA8_INTERNAL static void internal_ipc_clr_write(uint32_t ch, uint32_t value)
{
  s_ipc.sta[ch] &= ~(value & (uint32_t)k_ipc_sta_irq_mask);
  ipc_fifo_t* f = &s_ipc.fifo[ch];
  if ((value & (uint32_t)k_ipc_clr_rst) != 0U) {
    f->rd    = 0U;
    f->count = 0U; /* FIFO reset also drops RDY + FULL (they are computed). */
  }
  if ((value & (uint32_t)k_ipc_clr_rclr) != 0U) {
    f->rerr = false;
  }
  if ((value & (uint32_t)k_ipc_clr_fclr) != 0U) {
    f->ferr = false;
  }
}

RA8_INTERNAL static void
internal_ipc_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)size;
  const uint64_t off = addr - (uint64_t)k_ipc_base;
  uint32_t       ch  = 0U;
  uint32_t       reg = 0U;
  if (!internal_ipc_decode(off, &ch, &reg)) {
    return; /* semaphore / NMI window write: benign no-op */
  }
  if (reg == (uint32_t)k_ipc_reg_iset) {
    const uint32_t bits = (uint32_t)value & (uint32_t)k_ipc_sta_irq_mask;
    if (bits == 0U) {
      return;
    }
    s_ipc.sta[ch] |= bits;
    s_ipc.sends++;
    /* Raise the receiving core's ELC event: the core's ICU walks its IELSR
     * shadow, pends the mapped NVIC line, and the M85 takes it on its next
     * instruction boundary (cpu1 never drains, so an IPC1 raise is inert). */
    const uint16_t event =
      (ch < (uint32_t)k_ipc_unit_split) ? (uint16_t)k_ipc0_irq_event : (uint16_t)k_ipc1_irq_event;
    board_periph_icu_raise_event(uc, event);
    s_ipc.wakes++;
    if (board_periph_trace()) {
      (void)priv_emu_io_errf("  IPC           : ch%u ISET 0x%02X -> raise 0x%03X\n",
                             ch,
                             bits,
                             (unsigned)event);
    }
    return;
  }
  if (reg == (uint32_t)k_ipc_reg_txd) {
    internal_ipc_fifo_push(ch, (uint32_t)value);
    return;
  }
  if (reg == (uint32_t)k_ipc_reg_clr) {
    internal_ipc_clr_write(ch, (uint32_t)value);
  }
}
 
/* =============================================================================
 * Reset / report.
 * =============================================================================
 */

RA8_INTERNAL static void internal_ipc_reset(void)
{
  s_ipc = (ipc_state_t){};
}

RA8_INTERNAL static void internal_ipc_report(void)
{
  if ((s_ipc.sends == 0U) && (s_ipc.wakes == 0U) && (s_ipc.pushes == 0U) && (s_ipc.pops == 0U)) {
    return;
  }
  (void)priv_emu_io_errf("  IPC           : sends=%u wakes=%u fifo pushes=%u pops=%u\n",
                         s_ipc.sends,
                         s_ipc.wakes,
                         s_ipc.pushes,
                         s_ipc.pops);
}

static const board_periph_block_t s_k_ipc_block = {
  .base   = (uint64_t)k_ipc_base,
  .span   = (uint64_t)k_ipc_span,
  .order  = (uint32_t)k_ipc_block_order,
  .read   = internal_ipc_read,
  .write  = internal_ipc_write,
  .tick   = nullptr,
  .reset  = internal_ipc_reset,
  .report = internal_ipc_report,
  .name   = "IPC",
};

[[gnu::constructor]] RA8_INTERNAL static void internal_board_periph_ipc_register(void)
{
  board_periph_register_block(&s_k_ipc_block);
}