board_periph_glcdc.c

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#include <stdint.h>
#include <stdio.h>
 
#include "board_periph.h"
#include "board_periph_block.h"
#include "emu_host_io_internal.h"

typedef enum : uint64_t {
  k_glcdc_base = 0x40342000ULL, 
  k_glcdc_span = 0x1500ULL,     
} glcdc_geom_t;

typedef enum : uint64_t {
  k_glcdc_off_bg_en = 0x1000ULL, 
 
  k_glcdc_off_gr1_flmrd = 0x1104ULL, 
  k_glcdc_off_gr1_saddr = 0x110CULL, 
  k_glcdc_off_gr1_flm3  = 0x1110ULL, 
  k_glcdc_off_gr1_line  = 0x1118ULL, 
  k_glcdc_off_gr1_fmt   = 0x111CULL, 
 
  k_glcdc_off_gr2_flmrd = 0x1204ULL, 
  k_glcdc_off_gr2_saddr = 0x120CULL, 
  k_glcdc_off_gr2_flm3  = 0x1210ULL, 
  k_glcdc_off_gr2_line  = 0x1218ULL, 
  k_glcdc_off_gr2_fmt   = 0x121CULL, 
} glcdc_off_t;

typedef enum : uint32_t {
  k_glcdc_bg_en_bit      = (1U << 0U), 
  k_glcdc_flmrd_renb_bit = (1U << 0U), 
  k_glcdc_fmt_shift      = 28U,        
  k_glcdc_fmt_mask       = 0x7U,       
  k_glcdc_stride_shift   = 16U,        
  k_glcdc_stride_mask    = 0xFFFFU,    
  k_glcdc_lnnum_shift    = 16U,        
  k_glcdc_lnnum_mask     = 0x7FFU,     
} glcdc_field_t;

typedef enum : uint8_t {
  k_glcdc_fmt_argb8888 = 0x0U, 
  k_glcdc_fmt_rgb888   = 0x1U, 
  k_glcdc_fmt_rgb565   = 0x2U, 
  k_glcdc_fmt_argb1555 = 0x3U, 
  k_glcdc_fmt_argb4444 = 0x4U, 
  k_glcdc_fmt_clut8    = 0x5U, 
  k_glcdc_fmt_clut4    = 0x6U, 
  k_glcdc_fmt_clut1    = 0x7U, 
} glcdc_fmt_t;

typedef enum : uint8_t {
  k_glcdc_bpp_32 = 4U, 
  k_glcdc_bpp_16 = 2U, 
  k_glcdc_bpp_8  = 1U, 
} glcdc_bpp_t;

typedef enum : uint32_t {
  k_glcdc_dtcm_base  = 0x20000000U, 
  k_glcdc_dtcm_end   = 0x20010000U, 
  k_glcdc_sram_base  = 0x22000000U, 
  k_glcdc_sram_end   = 0x22200000U, 
  k_glcdc_sdram_base = 0x68000000U, 
  k_glcdc_sdram_end  = 0x6C000000U, 
} glcdc_ram_window_t;

typedef enum : uint32_t {
  k_glcdc_fnv_offset = 2166136261U, 
  k_glcdc_fnv_prime  = 16777619U,   
} glcdc_fnv_t;

typedef enum : uint32_t {
  k_glcdc_read_chunk   = 4096U,     
  k_glcdc_max_fb_bytes = 0x800000U, 
  k_glcdc_max_dim      = 4096U,     
} glcdc_bound_t;

typedef struct {
  uint32_t saddr; 
  uint32_t flm3;  
  uint32_t flm5;  
  uint32_t fmt;   
  bool     flmrd; 
} glcdc_layer_t;

typedef struct {
  glcdc_layer_t gr1;   
  glcdc_layer_t gr2;   
  bool          bg_on; 
  uc_engine*    uc;    
} glcdc_state_t;
 
static glcdc_state_t s_glcdc;

RA8_INTERNAL static uint32_t internal_glcdc_bpp_for_format(uint8_t fmt)
{
  switch (fmt) {
    case (uint8_t)k_glcdc_fmt_argb8888:
    case (uint8_t)k_glcdc_fmt_rgb888:
      return (uint32_t)k_glcdc_bpp_32;
    case (uint8_t)k_glcdc_fmt_rgb565:
    case (uint8_t)k_glcdc_fmt_argb1555:
    case (uint8_t)k_glcdc_fmt_argb4444:
      return (uint32_t)k_glcdc_bpp_16;
    default:
      return (uint32_t)k_glcdc_bpp_8; /* CLUT8 / CLUT4 / CLUT1. */
  }
}

RA8_INTERNAL static bool internal_glcdc_addr_is_ram(uint32_t addr)
{
  const bool in_dtcm = (addr >= (uint32_t)k_glcdc_dtcm_base) && (addr < (uint32_t)k_glcdc_dtcm_end);
  const bool in_sram = (addr >= (uint32_t)k_glcdc_sram_base) && (addr < (uint32_t)k_glcdc_sram_end);
  const bool in_sdram =
    (addr >= (uint32_t)k_glcdc_sdram_base) && (addr < (uint32_t)k_glcdc_sdram_end);
  return in_dtcm || in_sram || in_sdram;
}

RA8_INTERNAL static bool
internal_glcdc_layer_decode(const glcdc_layer_t* layer, uint8_t num, board_glcdc_fb_t* out)
{
  if (!layer->flmrd || !internal_glcdc_addr_is_ram(layer->saddr)) {
    return false;
  }
  const uint32_t stride =
    (layer->flm3 >> (uint32_t)k_glcdc_stride_shift) & (uint32_t)k_glcdc_stride_mask;
  const uint32_t lnnum =
    (layer->flm5 >> (uint32_t)k_glcdc_lnnum_shift) & (uint32_t)k_glcdc_lnnum_mask;
  const uint8_t fmt =
    (uint8_t)((layer->fmt >> (uint32_t)k_glcdc_fmt_shift) & (uint32_t)k_glcdc_fmt_mask);
  const uint32_t bpp    = internal_glcdc_bpp_for_format(fmt);
  const uint32_t height = lnnum + 1U;
  const uint32_t width  = stride / bpp;
  if ((stride == 0U) || (width == 0U) || (width > (uint32_t)k_glcdc_max_dim) ||
      (height > (uint32_t)k_glcdc_max_dim)) {
    return false;
  }
  out->base    = layer->saddr;
  out->width   = width;
  out->height  = height;
  out->stride  = stride;
  out->format  = fmt;
  out->layer   = num;
  out->enabled = s_glcdc.bg_on;
  return true;
}
 
bool board_periph_glcdc_get_framebuffer(board_glcdc_fb_t* out)
{
  if (out == nullptr) {
    return false;
  }
  /* GR1 is the upper layer the e-reader and glcdc_render draw into; prefer it,
   * then fall back to GR2 when only the lower layer is fetching. */
  if (internal_glcdc_layer_decode(&s_glcdc.gr1, 1U, out)) {
    return true;
  }
  return internal_glcdc_layer_decode(&s_glcdc.gr2, 2U, out);
}

RA8_INTERNAL static void internal_glcdc_snoop(uint64_t off, uint32_t value)
{
  switch (off) {
    /* HUM Ch 63 "BG_EN" p 3759 */ /* background-plane operation enable. */
    case (uint64_t)k_glcdc_off_bg_en:
      s_glcdc.bg_on = ((value & (uint32_t)k_glcdc_bg_en_bit) != 0U);
      break;
 
    /* HUM Ch 63 "GR1_FLM2.BASE" p 3744 */ /* layer-1 framebuffer base address. */
    case (uint64_t)k_glcdc_off_gr1_saddr:
      s_glcdc.gr1.saddr = value;
      break;
    /* HUM Ch 63 "GR1_FLM3.LNOFF" p 3744 */ /* layer-1 line stride (bytes). */
    case (uint64_t)k_glcdc_off_gr1_flm3:
      s_glcdc.gr1.flm3 = value;
      break;
    /* HUM Ch 63 "GR1_FLM5.LNNUM" p 3744 */ /* layer-1 line count minus one. */
    case (uint64_t)k_glcdc_off_gr1_line:
      s_glcdc.gr1.flm5 = value;
      break;
    /* HUM Ch 63 "GR1_FLM6.FORMAT" p 3744 */ /* layer-1 pixel format code. */
    case (uint64_t)k_glcdc_off_gr1_fmt:
      s_glcdc.gr1.fmt = value;
      break;
    /* HUM Ch 63 "GR1_FLMRD.RENB" p 3744 */ /* layer-1 framebuffer read enable. */
    case (uint64_t)k_glcdc_off_gr1_flmrd:
      s_glcdc.gr1.flmrd = ((value & (uint32_t)k_glcdc_flmrd_renb_bit) != 0U);
      break;
 
    /* HUM Ch 63 "GR2_FLM2.BASE" p 3744 */ /* layer-2 framebuffer base address. */
    case (uint64_t)k_glcdc_off_gr2_saddr:
      s_glcdc.gr2.saddr = value;
      break;
    /* HUM Ch 63 "GR2_FLM3.LNOFF" p 3744 */ /* layer-2 line stride (bytes). */
    case (uint64_t)k_glcdc_off_gr2_flm3:
      s_glcdc.gr2.flm3 = value;
      break;
    /* HUM Ch 63 "GR2_FLM5.LNNUM" p 3744 */ /* layer-2 line count minus one. */
    case (uint64_t)k_glcdc_off_gr2_line:
      s_glcdc.gr2.flm5 = value;
      break;
    /* HUM Ch 63 "GR2_FLM6.FORMAT" p 3744 */ /* layer-2 pixel format code. */
    case (uint64_t)k_glcdc_off_gr2_fmt:
      s_glcdc.gr2.fmt = value;
      break;
    /* HUM Ch 63 "GR2_FLMRD.RENB" p 3744 */ /* layer-2 framebuffer read enable. */
    case (uint64_t)k_glcdc_off_gr2_flmrd:
      s_glcdc.gr2.flmrd = ((value & (uint32_t)k_glcdc_flmrd_renb_bit) != 0U);
      break;
 
    default:
      break; /* Other GLCDC registers: shadowed by the caller's sparse model. */
  }
}

RA8_INTERNAL static void
internal_glcdc_write(uc_engine* uc, uint64_t addr, unsigned size, uint64_t value)
{
  (void)size;
  s_glcdc.uc = uc; /* stash for the report's framebuffer read */
  internal_glcdc_snoop(addr - (uint64_t)k_glcdc_base, (uint32_t)value);
}

RA8_INTERNAL static uint64_t internal_glcdc_read(uc_engine* uc, uint64_t addr, unsigned size)
{
  (void)uc;
  (void)addr;
  (void)size;
  return 0U;
}

RA8_INTERNAL static void internal_glcdc_tick(uc_engine* uc)
{
  s_glcdc.uc = uc;
}

RA8_INTERNAL static void internal_glcdc_reset(void)
{
  s_glcdc = (glcdc_state_t){};
}

RA8_INTERNAL static bool internal_glcdc_hash_framebuffer(const board_glcdc_fb_t* fb,
                                                         uint32_t*               out_crc)
{
  if (s_glcdc.uc == nullptr) {
    return false;
  }
  const uint32_t bpp        = internal_glcdc_bpp_for_format(fb->format);
  const uint64_t line_bytes = (uint64_t)fb->width * (uint64_t)bpp;
  const uint64_t total      = line_bytes * (uint64_t)fb->height;
  if ((total == 0U) || (total > (uint64_t)k_glcdc_max_fb_bytes)) {
    return false;
  }
  uint32_t hsh = (uint32_t)k_glcdc_fnv_offset;
  uint8_t  buf[k_glcdc_read_chunk];
  /* Hash the visible pixels row by row (skipping any inter-line stride padding)
   * so the witness matches a contiguous width*bpp*height framebuffer hash. */
  for (uint32_t row = 0U; row < fb->height; ++row) {
    const uint64_t row_base = (uint64_t)fb->base + ((uint64_t)row * (uint64_t)fb->stride);
    uint64_t       done     = 0U;
    while (done < line_bytes) {
      uint64_t want = line_bytes - done;
      if (want > (uint64_t)k_glcdc_read_chunk) {
        want = (uint64_t)k_glcdc_read_chunk;
      }
      if (emu_mem_read(s_glcdc.uc, row_base + done, buf, (size_t)want) != UC_ERR_OK) {
        return false;
      }
      for (uint64_t i = 0U; i < want; ++i) {
        hsh = (hsh ^ (uint32_t)buf[i]) * (uint32_t)k_glcdc_fnv_prime;
      }
      done += want;
    }
  }
  *out_crc = hsh;
  return true;
}

RA8_INTERNAL static const char* internal_glcdc_format_name(uint8_t fmt)
{
  switch (fmt) {
    case (uint8_t)k_glcdc_fmt_argb8888:
      return "argb8888";
    case (uint8_t)k_glcdc_fmt_rgb888:
      return "rgb888";
    case (uint8_t)k_glcdc_fmt_rgb565:
      return "rgb565";
    case (uint8_t)k_glcdc_fmt_argb1555:
      return "argb1555";
    case (uint8_t)k_glcdc_fmt_argb4444:
      return "argb4444";
    default:
      return "clut";
  }
}

RA8_INTERNAL static void internal_glcdc_report(void)
{
  board_glcdc_fb_t fb = {};
  if (!board_periph_glcdc_get_framebuffer(&fb)) {
    return; /* No graphics layer programmed: stay quiet. */
  }
  uint32_t    crc    = 0U;
  const bool  hashed = internal_glcdc_hash_framebuffer(&fb, &crc);
  const char* enab   = fb.enabled ? "scanning" : "idle";
  if (hashed) {
    (void)priv_emu_io_errf("  GLCDC         : layer%u fb=0x%08X %ux%u %s stride=%u crc=%08X (%s)\n",
                           (unsigned)fb.layer,
                           fb.base,
                           fb.width,
                           fb.height,
                           internal_glcdc_format_name(fb.format),
                           fb.stride,
                           crc,
                           enab);
  } else {
    (void)priv_emu_io_errf("  GLCDC         : layer%u fb=0x%08X %ux%u %s stride=%u (%s)\n",
                           (unsigned)fb.layer,
                           fb.base,
                           fb.width,
                           fb.height,
                           internal_glcdc_format_name(fb.format),
                           fb.stride,
                           enab);
  }
}

typedef enum : uint32_t {
  k_glcdc_block_order = 165U, 
} glcdc_order_t;

static const board_periph_block_t s_k_glcdc_block = {
  .base    = (uint64_t)k_glcdc_base,
  .span    = (uint64_t)k_glcdc_span,
  .order   = (uint32_t)k_glcdc_block_order,
  .read    = internal_glcdc_read,
  .write   = internal_glcdc_write,
  .tick    = internal_glcdc_tick,
  .reset   = internal_glcdc_reset,
  .report  = internal_glcdc_report,
  .name    = "GLCDC",
  .observe = true,
};

[[gnu::constructor]] RA8_INTERNAL static void internal_glcdc_block_register(void)
{
  board_periph_register_block(&s_k_glcdc_block);
}