Bug Index¶
All 23 bugs encountered during the MR18 OpenWrt JTAG flash project, from first power-on to successful failsafe boot.
Summary Table¶
| Bug # | Title | Category | Related Doc | One-line Summary |
|---|---|---|---|---|
| 1 | Wrong Binary (ar71xx vs ath79) | Toolchain | address-map | ar71xx lzma-loader zeroes BSS before relocation, wiping LZMA data. |
| 2 | OpenOCD Startup Timing | JTAG/PRACC | script-reference | OpenOCD started before power-on; no live TAP during init scan. |
| 3 | Socket Buffer Contamination | JTAG/PRACC | script-reference | Hardcoded 0.5s socket timeout caused _drain() to return before load_image finished. |
| 4 | PRACC Write Bit Errors | JTAG/PRACC | mips-memory-model | PRACC handshake protocol errors caused 18 single-bit flips per 45 KB sample. |
| 5 | Hardware Watchdog | Boot/kernel | address-map | AR9344 hardware watchdog continues counting during JTAG halt. |
| 6 | Named Pipe EOF | Toolchain | script-reference | Named pipe "w" mode sends EOF on close, killing scpi-repl. |
| 7 | Flush Trampoline Timeout | Cache coherency | mips-memory-model | CACHE instruction exception when running from KSEG1 with Nandloader exception vectors. |
| 8 | Phantom Verify Errors | Verification | mips-memory-model | PRACC reads inherit the same bit-flip rate as writes, producing phantom corrections. |
| 9 | Trampoline Overlaps Binary | Verification | address-map | TRAMPOLINE_ADDR inside loaded binary range overwrote XOR program during chunk rewrite. |
| 10 | XOR Cancellation | Verification | mips-memory-model | Two corrupt words with matching XOR deltas cancelled, passing full-binary checksum. |
| 11 | D-Cache Stale Data | Cache coherency | mips-memory-model | D-cache held stale Cisco data; KSEG1 verification saw correct RAM, KSEG0 execution got stale bytes. |
| 12 | BEQ vs BNE Encoding | Verification | mips-memory-model | 1-bit opcode error (op=4 vs op=5) caused flush loop to run once instead of 4096 times. |
| 13 | Flush Ordering | Cache coherency | mips-memory-model | Post-load flush evicted dirty Cisco D-cache lines back to DRAM, overwriting OpenWrt binary. |
| 14 | Ethernet Silent | Boot/kernel | script-reference | Meraki NAND overlay mounted over initramfs, running Cisco userspace instead of OpenWrt. |
| 15 | Meraki NAND Overlay | Failsafe | script-reference | OpenWrt preinit mounted Meraki NAND overlay; Meraki management frames appeared instead of OpenWrt. |
| 16 | Failsafe Timing | Failsafe | script-reference | GPIO17 asserted at t=30s, but failsafe window closed at t=18s. |
| 17 | Missing Resume | JTAG/PRACC | address-map | mdw halts CPU for PRACC read; CPU stayed halted through entire GPIO hammer loop. |
| 18 | mdw/mww Require Halt | JTAG/PRACC | address-map | After resume, mdw returns ERROR_TARGET_NOT_HALTED silently; GPIO reads returned nothing useful. |
| 19 | GPIO vs Pull-up | Hardware/electrical | address-map | External pull-ups (5 kohm effective) overpower AR934x GPIO drive strength. |
| 20 | Reset Supervisor IC | Hardware/electrical | prerequisites | Dedicated reset supervisor IC drives GPIO17 HIGH with strong CMOS output (10-50 mA). |
| 21 | Manual Prompt Too Late | Failsafe | script-reference | Useless JTAG hammer consumed 25s before printing prompt; failsafe window already closed. |
| 22 | Resistor Wrong Side | Hardware/electrical | prerequisites | 100 ohm between GPIO17 net and EN transistor caused voltage drop on wrong side. |
| 23 | EN Before Boot | Failsafe | script-reference | EN assertion at t=12s released before kernel finished LZMA decompression at t=18-25s. |
Bug Category Distribution¶
pie title Bug Categories
"JTAG/PRACC" : 6
"Cache coherency" : 3
"Verification" : 4
"Failsafe" : 4
"Toolchain" : 2
"Boot/kernel" : 2
"Hardware/electrical" : 3
Category Breakdown¶
- JTAG/PRACC (6): Bugs 2, 3, 4, 17, 18—protocol-level issues with EJTAG PRACC memory access and OpenOCD communication.
- Verification (4): Bugs 8, 9, 10, 12—errors in the verify-and-correct pipeline (phantom reads, trampoline placement, XOR cancellation, instruction encoding).
- Failsafe (4): Bugs 15, 16, 21, 23—timing and trigger issues getting OpenWrt into failsafe mode.
- Cache coherency (3): Bugs 7, 11, 13—MIPS D-cache stale data and flush ordering relative to JTAG load.
- Hardware/electrical (3): Bugs 19, 20, 22—physical signal contention between GPIO, pull-ups, reset supervisor IC, and EN wiring.
- Toolchain (2): Bugs 1, 6—wrong firmware target and named pipe file mode.
- Boot/kernel (2): Bugs 5, 14—hardware watchdog and NAND overlay issues during kernel boot.