118 app(s) in this tier:

App	Description
`acmphs_compare`	Polls the High-Speed Analog Comparator on channel 0 and routes the decision to the board LEDs: LED1 toggles while the output reads high, LED2 while it reads low, LED3 on an init failure. No UART ...
`adc_b_demo`	Samples ADC_B channel AN000 in 12-bit software-triggered mode, scales the raw code to millivolts against the board's 3.3 V VREFH, and logs each conversion over the J-Link OB console. LED1 is the ...
`agt_cascade_demo`	Chains AGT0 and AGT1 into one 32-bit virtual counter, toggling LED1 and logging the running tick count on every AGT1 underflow.
`agt_periodic`	Runs AGT0 free-running and toggles LED1 on every counter underflow, logging a tick line over the J-Link OB console. The smallest thing that proves the AGT counts and that its underflow reaches ...
`agt_pulse_demo`	Runs AGT0 in pulse-output mode with compare-match A driving the AGTOAn pin (HUM Ch 24.3.4 "Pulse Output Mode" p 1177), toggling LED1 and logging the tick count on every underflow.
`app_launch_demo`	Exercises the ra8_app registry, the per-app lifecycle vtable and the navigation back-stack end to end on the real Cortex-M85 image (issue #146). There is deliberately no display and no widgets, so ...
`app_shell_demo`	The chrome / launcher increment of the ra8_app framework (issue #146). It builds on app_launch_demo by adding what a home screen actually needs: a launcher that enumerates the registry and starts an ...
`blink`	Toggles user LED1 (P600, blue) at a clean 1 Hz off SysTick, with no busy-wait.
`blink_hal`	The same 1 Hz blink as blink, driven through ra8_gpio_ and ra8_time_ instead of raw register writes, across all three user LEDs.
`blink_m33`	The canonical "put the work on the M33" template (issue #152). The Cortex-M85 does the minimum – release the Cortex-M33, then sleep – and the M33 owns the application. Here that application is ...
`bscan_selftest`	Self-test for the JTAG / IEEE-1149.1 boundary-scan bookkeeping driver ra8_bscan (#138). No panel, SD card, touch or external JTAG fixture needed.
`cac_accuracy_demo`	Uses the Clock Frequency Accuracy Measurement Circuit to count edges of the 24 MHz main oscillator inside one window of the LOCO reference divided by 32, and flags a frequency error if the crystal is ...
`cache_coherency_hil`	Proves the Cortex-M85 and Cortex-M33 stay coherent across shared on-chip SRAM with the M85 data cache enabled, by routing every cross-core hand-off through the boot's non-cacheable MPU region.
`cache_mpu_hil`	Boots with the L1 I-cache, D-cache and the five-region MPU enabled (RA8_BOOT_ENABLE_CACHE_MPU) and proves the Cortex-M85 still runs correctly with them on. Single-core, and the on-silicon arm of the ...
`camera_capture`	Captures one live VGA frame from the OV5640 on the Camera Expansion Board through the RA8D2 Capture Engine Unit, converts it to RGB in firmware, and reports a plausibility verdict over the console. ...
`can_classic_loopback`
`canfd_filter_demo`	Exercises the CAN-FD acceptance filter in internal loopback with three sub-rounds per iteration: an exact-ID match (0x100), a masked match (0x110 under mask 0x7F0), and an ID that must be filtered ...
`canfd_loopback`	Puts CANFD0 into Self-test 1 internal loopback (CFDC[0].CTR.CTME = 1, CTMS = 11b) at 500 kbps and round-trips an 8-byte frame at standard ID 0x123 once a second. LED1 toggles on a completed ...
`clock_check`	Brings the chip from the reset-default MOCO up to its rated CPUCLK0 through ra8_cgc_init() – HOCO start, PLL1 lock, clock mux, peripheral dividers – then walks a table of clock IDs (CPUCLK0, ICLK, ...
`cpu1_pingpong`	Dual-core round-trip: the M85 releases the M33, writes a ping word into a fixed shared-SRAM message struct, and the M33 replies with a pong. g_cpu1_pingpong_match advances per verified round-trip and ...
`crc_demo`	Cross-checks the on-chip CRC engine against a bit-serial software reference over the same buffer, once a second, and reports whether they agree. LED1 toggles on a match and LED2 on a mismatch, which ...
`crypto_aes_demo`	Round-trips a fixed plaintext through AES-128-GCM via the ra8_psa_crypto facade once a second – import key, AEAD-encrypt with a fixed nonce and AAD, decrypt, compare byte-for-byte. LED1 toggles on a ...
`dac_b_demo`	Sweeps DAC_B channel 0 in 12-bit normal-vref mode from 0 V up to about 3.3 V and back, stepping every 20 ms. dac_waveform drives a triangle over the same channel; this one is a deterministic DC ramp, ...
`dac_waveform`	Drives DAC_B channel 0 with a triangle spanning the full 12-bit code range, 64 steps at 1 ms each, so one up-and-down period is about 128 ms (roughly 8 Hz). Probe the DAC0 output pad with an ...
`dfu_bootloader`	The immutable first 128 KiB of code-MRAM. It never erases itself. At every reset it either boots a valid application slot – software A/B select plus copy-to-run – or, when no slot is bootable or an ...
`dfu_copy_to_run`	Unattended proof of the dfu_bootloader's copy-to-run scheme (issue #97): an image linked once at the SRAM run base runs from wherever it is staged, so there is no per-slot build and no "which slot am ...</td></tr> <tr><td><a href="dir_c23cbb27c40c6c1199a481db111a7b39.html"><code>dfu_selftest_boot</code></a></td><td></td></tr> <tr><td><a href="dir_b467f67bc93b70f83529caf2c38d74fc.html"><code>dfu_selftest_fs_host</code></a></td><td></td></tr> <tr><td><a href="dir_0cd5f0d830e824ac5432eddf68bd5a1f.html"><code>dfu_selftest_hs_host</code></a></td><td></td></tr> <tr><td><a href="dir_90d97772f009d64738469cc869c80a4b.html"><code>dma_coherency_hil</code></a></td><td>Proves the clean-before / invalidate-after DMA cache-maintenance pattern keeps a DMAC0 mem-to-mem copy coherent with the M85 L1 D-cache turned on. Built with RA8_BOOT_ENABLE_CACHE_MPU, and both ...</td></tr> <tr><td><a href="dir_520520294e43c9ea0c94808697188aab.html"><code>dma_memcopy_demo</code></a></td><td>Fills a 1 KB buffer with a deterministic pattern, copies it SRAM-to-SRAM with DMAC0 channel 0 (32-bit wide, increment both, software-triggered), waits for the transfer count to drain, and verifies ...</td></tr> <tr><td><a href="dir_2dab77a7dcd365593da227b400fba354.html"><code>dma_memcopy_hal</code></a></td><td>The same 1 KB SRAM-to-SRAM DMAC block copy and verify as dma_memcopy_demo, driven entirely through the ra8_dmac HAL: ra8_dmac_software_trigger() and ra8_dmac_wait_idle() instead of poking DMREQ.SWREQ ...</td></tr> <tr><td><a href="dir_37e59cb98e62257a4f03a181804ba9bf.html"><code>doc_demo</code></a></td><td></td></tr> <tr><td><a href="dir_7a64d37ad31eaa48719d20d7fe926702.html"><code>dotf_selftest_demo</code></a></td><td>Brings up the DOTF (Decryption On The Fly) block and runs its built-in AES self-test on both channels without ever arming one (#127). LED1 toggles while healthy and LED2 on a fault; g_dotf_ok, ...</td></tr> <tr><td><a href="dir_59fe8af5b11777002d1c8bfe79e2fb6d.html"><code>drw_blend_demo</code></a></td><td>Composites three layers into a small ARGB8888 framebuffer in SRAM -- an opaque background fill, an opaque sprite fill over it, then a source-over alpha blend at global alpha -- and folds an FNV-1a-32 ...</td></tr> <tr><td><a href="dir_062149706661f24d8d6fe781137202c4.html"><code>drw_dlist_demo</code></a></td><td>Builds one DRW display list in SRAM that clears a small ARGB8888 framebuffer and fills a rectangle in it, kicks the list, waits for the display-list reader to go idle, and hashes the framebuffer. ...</td></tr> <tr><td><a href="dir_e0d33134fe39e4150c921e653c392397.html"><code>drw_fill_demo</code></a></td><td>Clears a small ARGB8888 framebuffer in SRAM, has the DRW fill a rectangle into it through ra8_drw_fill_rect, waits for the engine, then checks the result byte-exact: the centre pixel must be filled ...</td></tr> <tr><td><a href="dir_ef9f670be4ee0a329ce91928976d3dd4.html"><code>dtc_coherency_hil</code></a></td><td>Proves the DTC descriptor cache-coherency wiring holds with the Cortex-M85 L1 D-cache ON. The app builds with RA8_BOOT_ENABLE_CACHE_MPU, so the shared SystemInit programs the MPU and enables the ...</td></tr> <tr><td><a href="dir_39d3e651d3fbd38b2b1bc0eea994a03f.html"><code>dtc_transfer_demo</code></a></td><td>SRAM-to-SRAM block copy through the Data Transfer Controller, verified against the source pattern once a second -- the DTC counterpart to dma_memcopy_demo. LED1 toggles on a good copy and LED2 on a ...</td></tr> <tr><td><a href="dir_d74e29c25af89b9563d924a1b11d8034.html"><code>dualcore_background_m33</code></a></td><td>The producer/consumer dual-core pattern: the Cortex-M85 releases the Cortex-M33 and then does nothing but wait while the M33 runs a counting loop entirely on its own, publishing progress into a ...</td></tr> <tr><td><a href="dir_ed2b5e169609a2d61d40fc2d48f6e207.html"><code>dualcore_mailbox</code></a></td><td>Two independently compiled images -- one Cortex-M85, one Cortex-M33 -- stitched into a single flashable image, with both cores running at once and exchanging messages through a shared-SRAM mailbox. ...</td></tr> <tr><td><a href="dir_4a94f7c481bdd93250cbf4ffe93e61a7.html"><code>ecc_monitor_demo</code></a></td><td>Enables full ECC ("with-check") SECDED on a spare SRAM bank, round-trips a deterministic pattern through an ECC-protected buffer at the bank base, and reports the ECC error-status register (#130). ...</td></tr> <tr><td><a href="dir_9449b52c34ee0b7a35f7744406174161.html"><code>elc_event_demo</code></a></td><td>Brings the Event Link Controller up, routes external IRQ0 into ELC slot 0, and then fires that slot in software once a second so the demo never depends on anyone pressing a button. The ELC is how one ...</td></tr> <tr><td><a href="dir_245250982ecac786f1c75cdcb68dbd27.html"><code>ereader_align</code></a></td><td>Lays a baked chapter out through reflow with one paragraph each of text-align right, center, justify and the default left, then folds an FNV-1a-32 hash over every laid-out glyph's (x, y) (#108). The ...</td></tr> <tr><td><a href="dir_ad108e4e34dce9402a303d83791ed8c4.html"><code>ereader_chrome</code></a></td><td>Builds a representative e-reader chrome screen as an ra8_box tree -- a status bar over a two-column grid of book cells -- lays it out into a fixed frame, renders the boxes and labels into an RGB565 ...</td></tr> <tr><td><a href="dir_0a3cfe2bd27842707bb9a681fabd4f45.html"><code>ereader_image</code></a></td><td>Decodes a baked RGB PNG cover through ra8_img_decode_blit(), nearest-neighbour scales it to fit a fixed RGB565 framebuffer in internal SRAM, and hashes the framebuffer (#106) -- the same decode, ...</td></tr> <tr><td><a href="dir_a95e03639299e6f9c50d84bdee56ed3c.html"><code>ereader_imgfmt</code></a></td><td>Decodes a baked BMP and a baked GIF through ra8_img_decode_blit() into a fixed RGB565 framebuffer and hashes each result (#143). The firmware links four stb_image decoders; PNG (ereader_image) and ...</td></tr> <tr><td><a href="dir_e67921da5c503719785f60c9d97186fe.html"><code>ereader_input</code></a></td><td>Exercises the e-reader interaction layer with synthetic taps, so it needs no GT911 touch panel (#80, #118). It builds a representative target set -- a book grid plus a toolbar button, each a rect ...</td></tr> <tr><td><a href="dir_cece7fffe2e95a69cf6337c4d3846f40.html"><code>ereader_jpeg</code></a></td><td>Decodes a baked RGB JPEG cover through the zero-heap ra8_img_decode_blit() pipeline, nearest-neighbour scales it into a fixed RGB565 framebuffer in internal SRAM, and hashes the framebuffer (#143) -- ...</td></tr> <tr><td><a href="dir_776cf06afaad848a540d6e323dba8399.html"><code>ereader_link</code></a></td><td>Exercises in-content hyperlink navigation end to end (#110). It lays a baked chapter out through reflow carrying one cross-chapter <a href>, one #fragment link and the matching id anchor; synthesises ...</td></tr> <tr><td><a href="dir_b28b127dc1876231b41f9eecec9fb5c1.html"><code>ereader_rabook</code></a></td><td>Loads a compiled .rabook and renders it -- the on-silicon proof of the book pipeline. It validates the flat blob (magic, table bounds, CRC-32), walks each chapter's pre-parsed DOM back out as XHTML ...</td></tr> <tr><td><a href="dir_d69dd897321105e1f534a9007f5a7076.html"><code>ereader_svg</code></a></td><td>Rasterizes a baked SVG into a fixed RGB565 framebuffer and hashes the result (#143) -- the vector counterpart to the raster stb_image gates ereader_image (PNG) and ereader_jpeg (JPEG). It reads the ...</td></tr> <tr><td><a href="dir_c2e2f9005fcaec32c2b5aa9aa9cb0631.html"><code>ereader_table</code></a></td><td>Lays a baked chapter out through reflow with a heading, a two-column table (a <th> header row plus data rows) and a trailing paragraph, then folds an FNV-1a-32 hash over every laid-out glyph's (x, y) ...</td></tr> <tr><td><a href="dir_85d9d63bb64ec07f374e926cf1048c23.html"><code>ereader_ui</code></a></td><td>The e-reader device chrome on the live GLCDC panel (#80). The application shell is laid out by the bounded box-model engine ra8_box, painted through ra8_gfx into the GLCDC framebuffer, and navigated ...</td></tr> <tr><td><a href="dir_09b9f31a6f5b497e644defa80eb550a6.html"><code>eth_loopback</code></a></td><td>Runs ETHA port 0 through the full descriptor-ring lifecycle in MAC-only internal loopback -- init, CONFIG mode, ring init, OPERATION mode, traffic accounting, stats, deinit -- and reports success on ...</td></tr> <tr><td><a href="dir_8ec335d159594b08c84a2a0ee21b0434.html"><code>eth_open_probe</code></a></td><td>The smallest program that reaches ra8_eth_open() on silicon: clocks, module stop, time, console, ra8_board_ethernet_init(), then open on channel 1 -- the EK-RA8D2 RJ45 is ETHA1. No RTOS, no IP stack, ...</td></tr> <tr><td><a href="dir_97f6fc021ead7930b08ace4fe554bea9.html"><code>fault_crashlog_hil</code></a></td><td>Proof of the cross-reset crash log and reset-loop guard (ra8_crashlog): a decoded fault snapshot is persisted into a .noinit record the reset handler does not zero, crash-reboot cycles are counted, ...</td></tr> <tr><td><a href="dir_fae9eaf0336ccd8afe7b43fdec39670a.html"><code>fault_div0_hil</code></a></td><td>Proof that CCR.DIV_0_TRP, set by the shared boot, turns an integer divide by zero into a decoded UsageFault instead of the ARM-default silent quotient of zero. The app reads CCR back first -- so a ...</td></tr> <tr><td><a href="dir_6b8a55f7d6a3b7aa20123eaa8be81f5e.html"><code>flash_journal</code></a></td><td>Erase, program and read-back round-trip of a small counter record on the on-board IS25LX512M Octo-SPI flash (U16), once a second. g_fj_match advances on every clean round-trip, g_fj_mismatch must ...</td></tr> <tr><td><a href="dir_30c5e7585c97fe4025e986ff3c32b688.html"><code>fs_format_mount</code></a></td><td>Formats, mounts and exercises a real microSD card in every filesystem ra8_fs can write -- FAT12, FAT16, FAT32 and exFAT -- one after another. It assumes no pre-existing layout: for each type it runs ...</td></tr> <tr><td><a href="dir_d4477e623ea72439f781f58948338822.html"><code>glcdc_render</code></a></td><td>Proves the GLCDC hardware is programmed and scanning a real framebuffer (#121). ereader_chrome gates the software rasteriser into an SRAM buffer but never touches the display controller; this app ...</td></tr> <tr><td><a href="dir_e4dace65eaf1b28d9bdd03af710bbd8c.html"><code>gpio_input_demo</code></a></td><td>Polls the on-board user switch SW1 (P009) and drives LED1 to mirror it -- LED1 lit while SW1 is held. There is no UART output; LED1 is the only observable signal.</td></tr> <tr><td><a href="dir_18e147814837ac56f0a1fb8893688a88.html"><code>gpt_capture_input</code></a></td><td>Configures a GPT channel for input capture on a pin pulsed by SW1 and measures the period between presses in counter ticks; LED1 toggles on every captured event.</td></tr> <tr><td><a href="dir_0a8dd830e1d113b978781b8331076d4f.html"><code>gpt_dma_demo</code></a></td><td>Streams a table of GPT period values into GTPR over a DMAC channel, so the CPU never touches the period register per tick. The DMA-completion callback bumps a counter a bench probe watches, and the ...</td></tr> <tr><td><a href="dir_3f930fef5ae995cbaea632414735de8b.html"><code>gpt_one_shot_demo</code></a></td><td>Arms GPT channel 0 in saw-wave one-shot mode (HUM Ch 25.2.1, GTCR.MD = 001b): the counter runs up to the period once, raises an overflow IRQ, then stops on its own. The loop arms, waits for the IRQ ...</td></tr> <tr><td><a href="dir_6f17d162da3a4332f77e1aba6e35e67b.html"><code>gpt_pwm_demo</code></a></td><td>Drives an LED off GPT channel 0 in saw-wave PWM mode, walking the duty cycle from zero to full and back so it visibly breathes.</td></tr> <tr><td><a href="dir_48950286f931421a5a7ee47f8d588051.html"><code>gpt_three_phase_demo</code></a></td><td>Opens GPT channels 0/1/2 as a phase-synchronised three-phase PWM bank (HUM Ch 25.2.3, GTSTR / GTBER): all three are armed by one GTSTR write, so they start on the same PCLKD edge. The duties are ...</td></tr> <tr><td><a href="dir_f75df8963f5459ad579bff07ecc8dd0e.html"><code>i2c_i3c_combined</code></a></td><td>Brings up both of the RA8D2's I2C-capable controllers in one image and proves they run side by side: RIIC channel 1 against the on-board U15 expander at 7-bit 0x43, and the I3C block on channel 0 in ...</td></tr> <tr><td><a href="dir_6356ff45b9c2895187d7189080398ca0.html"><code>i2c_loopback</code></a></td><td>RIIC controller self-test: brings up channel 1 and probes the on-board PI4IOE5V6408 I/O expander (U15) at 7-bit address 0x43 once a second, toggling LED1 on each ACK.</td></tr> <tr><td><a href="dir_ea9c22b09cc5773295b25077d738f68f.html"><code>i3c_loopback</code></a></td><td>I3C controller bring-up self-test, run in I2C-compatibility mode on channel 0. Proves the I3C block's controller powers up and clocks a real START / address / STOP on silicon -- the counterpart to ...</td></tr> <tr><td><a href="dir_29942d2052ffdcc8507812df5e7ce754.html"><code>icu_extint_demo</code></a></td><td>Routes the SW1 push-button (P009 -> IRQ13-DS) through the ICU with falling-edge detection and the digital filter at PCLKB / 64, then polls the IRQCR detect bit directly. Each press toggles LED1 and ...</td></tr> <tr><td><a href="dir_5dbc5f65419f332ac6ed7c945da71a05.html"><code>iic_b_facade_demo</code></a></td><td>Exercises IIC_B -- the RA8D2 I3C block in legacy I2C-compatibility mode, twin of the RIIC path -- through the ra8_io_i2c_bus facade in BOTH roles the peripheral supports, controller and peripheral ...</td></tr> <tr><td><a href="dir_66939d920554834857b7fcc386a79708.html"><code>iwdt_demo</code></a></td><td>IWDT in window mode, as distinct from watchdog_demo, which simply refreshes until it stops. Polls the live 14-bit IWDTSR.CNTVAL counter and writes the refresh sequence only while the counter sits ...</td></tr> <tr><td><a href="dir_aec157d02691dbe9819f76e9558a3932.html"><code>keyboard</code></a></td><td>On-silicon gate for the on-screen keyboard model ra8_keyboard (#105), the text-entry logic behind the e-reader Library search.</td></tr> <tr><td><a href="dir_69af3ecb7a37f64b0128898f4f1d6751.html"><code>kint_demo</code></a></td><td>Programs the on-board user switch SW1 (P009 -> IRQ13-DS, EK-RA8D2 v1 UM Table 25 p 32) as a falling-edge external interrupt source via ra8_icu_configure_irq_pin, then polls the switch and logs each ...</td></tr> <tr><td><a href="dir_5b5fb1e8f538a2815819939ac3a4d02b.html"><code>lpm_deep_sleep_demo</code></a></td><td>Cortex-M85 Deep Sleep on a bare EK-RA8D2. LPSCR.LPMD stays at 0 (System Active, HUM Ch 11.2.20 p 457) but SCR.SLEEPDEEP is asserted before WFI, so the core power-gates harder than in plain Sleep -- ...</td></tr> <tr><td><a href="dir_24f2b041a238fab5a728c1296ec84cfb.html"><code>pdm_mic_demo</code></a></td><td>Captures from the EK-RA8D2's on-board PDM MEMS microphones through the ra8_audio facade and its ra8_pdm backend, then judges whether what came back is plausibly acoustic. Closes gap issue #129.</td></tr> <tr><td><a href="dir_8b7c90fd49434fbc5bcc345d09eb2b8a.html"><code>rtt_log_demo</code></a></td><td>Minimal SEGGER RTT logging demo: allocates an RTT control block in SRAM and writes numbered lines through the in-tree rtt_write shim, toggling LED1 alongside each one.</td></tr> <tr><td><a href="dir_f8f3115a00f57eb8ef1cfce4ac0d0720.html"><code>sd_font_render</code></a></td><td>Loads a TTF/OTF font off an SD card and renders a paragraph of XHTML with reflow into the GLCDC framebuffer -- the firmware promotion of the host test ...</td></tr> <tr><td><a href="dir_1b36caf939a540c645c65eaf17ba5a7f.html"><code>sdram_benchmark</code></a></td><td>Brings up the on-board 64 MB Winbond W9825G6KH SDRAM through ra8_sdramc_init -- the documented PALL -> MRS -> AREF-enable sequence -- at k_ra8_sdram_base_addr (0x68000000), then writes and reads back ...</td></tr> <tr><td><a href="dir_6d1da873ec0fe7834ec81c248042807a.html"><code>secure_boot_hil</code></a></td><td>On-silicon proof that the root of trust enforces the boot.</td></tr> <tr><td><a href="dir_751322b8df8350f1c603fe81ef4f5dc4.html"><code>spi_loopback</code></a></td><td>SPI_B internal-loopback test. Brings up ra8_spi on channel 0 at 1 MHz, mode 0, MSB first, then sets SPCR2.SPLP (HUM Ch 43.2.5 p 2889, k_ra8_spcr2_mask_splp) so COPI is fed back into CIPO inside the ...</td></tr> <tr><td><a href="dir_8f6342f9f557fa0e70231b844e135ac5.html"><code>ssie_audio_loop</code></a></td><td>SSIE I2S audio-integrity check on a bare EK-RA8D2. Brings up SSIE0 in controller / I2S mode (16-bit data, 32-bit system word, AUDIO_MCK / 32 bit clock divider) and round-trips a short sine pattern ...</td></tr> <tr><td><a href="dir_519bf2ce8c05a9b0b725c971bdda9c2c.html"><code>threadx_blink</code></a></td><td>ThreadX bring-up on the EK-RA8D2: two same-priority threads blinking LED1 and LED2 at different rates. It exercises the project's port glue under port/threadx/src/cortex_m85/ and the vendored ...</td></tr> <tr><td><a href="dir_f47f0a6969397b91fe76e475d1855268.html"><code>threadx_canfd_demo</code></a></td><td>Two ThreadX threads around CANFD0 in internal-loopback mode (HUM Ch 41, CFDCnCTR p 2710 -- transmitted frames are echoed back inside the chip, so no transceiver, no bus and no second node are ...</td></tr> <tr><td><a href="dir_9e1d2d498fc28976fed1f32f91821a43.html"><code>threadx_fs_demo</code></a></td><td>FAT file operations under ThreadX against the on-board Octo-SPI NOR flash, via LevelX wear-levelling. No SD card is involved.</td></tr> <tr><td><a href="dir_7343b4989e52d747f51c76f87bb5122a.html"><code>threadx_fs_levelx_demo</code></a></td><td>Formats and mounts a FAT volume on top of LevelX on the on-board ISSI IS25LX512M NOR flash (U16), writes a file and reads it back, all from one ThreadX worker. Same stack as threadx_fs_demo, but this ...</td></tr> <tr><td><a href="dir_8fb56ac1320f16f8985524996e9e395f.html"><code>threadx_ipc_demo</code></a></td><td>Inter-processor mailbox demo, M85 side. A ThreadX thread wakes once a second, pushes a single 32-bit word into the M85 -> M33 IPC FIFO, drains whatever is queued in the M33 -> M85 direction, and ...</td></tr> <tr><td><a href="dir_19bdd8d8c184893f117a3c93337812c4.html"><code>threadx_levelx_demo</code></a></td><td>LevelX wear-levelling burn-in on the on-board Octo-SPI flash, under ThreadX. The worker formats and opens a LevelX partition, then heartbeats: program an incrementing counter into logical sector 0, ...</td></tr> <tr><td><a href="dir_7fba8f39e3b6de75698778566a6b5391.html"><code>threadx_mpu_partition_demo</code></a></td><td>Installs a small static Armv8-M MPU region table at boot via ra8_mpu_configure, then runs one ThreadX worker blinking LED1 to prove the partition did not wedge ordinary code execution. It is the ...</td></tr> <tr><td><a href="dir_fa64ff41574639059b4ae3eab23757b8.html"><code>threadx_netx_tcp_echo</code></a></td><td>ThreadX + NetX Duo serving an RFC 862 TCP echo on 192.168.1.42:7 over the EK-RA8D2's R-Switch ethernet path (ETHA + RMAC + GWCA descriptor DMA), logging each served echo to the console.</td></tr> <tr><td><a href="dir_f66f526867ba2b9893b21c9cc49a39b3.html"><code>threadx_systick_retune</code></a></td><td>Proves the ThreadX kernel tick stays 1 ms whatever CPUCLK0 the app happened to boot at (#287).</td></tr> <tr><td><a href="dir_060f1776dec19996d6821dd2bd41b071.html"><code>timer_capture_demo</code></a></td><td>Runs GPT0 free-running and reports the counter delta across a fixed software delay, once a second, with LED1 as a heartbeat.</td></tr> <tr><td><a href="dir_c8279958ba1e70e79ba11a6346060753.html"><code>tz_secure_only_sd</code></a></td><td>SPI-mode SD round trip: bring the card up, mount its FAT volume through ra8_fs, write a pseudo-random payload, read it back, compare byte for byte.</td></tr> <tr><td><a href="dir_9583e45cc8df64adafbac8a06bb4d8c0.html"><code>uart_hello</code></a></td><td>Brings up CGC + SCI8 in async mode and prints hello, ra8d2! once a second while toggling LED1 as a heartbeat. The EK-RA8D2's on-board J-Link OB bridges SCI8 to a USB CDC port, so a terminal at 115200 ...</td></tr> <tr><td><a href="dir_c038454e6cb61bd2667cd5cdda047137.html"><code>uart_irq_echo</code></a></td><td>Interrupt-driven SCI8 echo, the counterpart to the poll-based uart_hello. It registers the SCI8 RXI / TXI / TEI events through the ICU IELSR table, then attaches an RX callback and arms an interrupt ...</td></tr> <tr><td><a href="dir_9d4dbcad3bb7a2a3c2c556bcfbae1139.html"><code>ulpt_demo</code></a></td><td>Brings up ULPT0 at roughly 1 Hz off the LOCO and treats each underflow as a wake event: log a line, stop the timer to clear ULPTCR.TUNDF, re-arm with the same period.</td></tr> <tr><td><a href="dir_d85788f8f352015d50b3938d176bace8.html"><code>usb_host_keyboard</code></a></td><td>Validates the first-party USB host HID boot-keyboard path with no keyboard in the room: the board hosts on one jack and emulates a boot-keyboard peripheral on the other over the loop cable (J7 HS ...</td></tr> <tr><td><a href="dir_47323897671a65a9aefb2e42a9e0bddf.html"><code>usb_host_msc_browse</code></a></td><td>Validates the first-party USB host MSC stack (ra8_usb_hmsc) with no external drive: the board hosts on one jack and emulates the peripheral on the other over the loop cable (J7 HS host <-> J11 FS ...</td></tr> <tr><td><a href="dir_08276176712f6269c71d6a263c9c964f.html"><code>usb_selftest_cdc</code></a></td><td>The bidirectional bulk member of the USB self-loop matrix: host bulk-OUT -> device receive -> device echo -> host bulk-IN, through a real CDC-ACM class. The two USB ports are cabled to each other and ...</td></tr> <tr><td><a href="dir_6f03f6482570f9d3c59382e33a8b8621.html"><code>usb_selftest_dfu</code></a></td><td>The control-transfer member of the USB self-loop matrix: host DFU_DNLOAD -> device capture -> host DFU_UPLOAD -> byte-exact compare, through a real DFU class. The two USB ports are cabled to each ...</td></tr> <tr><td><a href="dir_65c5f6908350852c488d43dd942d5d3e.html"><code>usb_selftest_fs_host</code></a></td><td>The role-flipped twin of usb_selftest_hs_host: same self-loop cable, same single image running both sides of the link, host and device swapped. USBHS (J7) is the Mass-Storage device exposing the 1 ...</td></tr> <tr><td><a href="dir_6aedf3461fe275abba3f2d39c526ee75.html"><code>usb_selftest_hid</code></a></td><td>The interrupt-transfer member of the USB self-loop matrix: the device streams input reports on its interrupt-IN endpoint and the host reads and byte-checks them, through a real HID class. The two USB ...</td></tr> <tr><td><a href="dir_fa35bf3dc492c77e1dadddc81d82162c.html"><code>usb_selftest_hs_host</code></a></td><td>The board's two USB ports are cabled to each other and ONE image runs BOTH sides of the link, then verifies itself on-chip -- no PC in the loop. USBFS (J11) is the usb_msc_mram Mass-Storage class ...</td></tr> <tr><td><a href="dir_27e04f74dc8b1f3aa1595828ea6d152a.html"><code>usb_selftest_microsd</code></a></td><td>Brings the board's Pmod2 microSD card up as a USB drive and verifies it against itself on-chip -- no PC in the loop. The two USB ports are cabled to each other and one image runs both USB stacks plus ...</td></tr> <tr><td><a href="dir_66fb007d04abfd72c946b765ddb4bd43.html"><code>usb_selftest_mlun</code></a></td><td>Brings up a multi-LUN USB Mass-Storage device and verifies it against itself on-chip -- no PC in the loop. The two USB ports are cabled to each other and one image runs both USB stacks. USBFS (J11) ...</td></tr> <tr><td><a href="dir_a707884dd10e9799f21ddb4afdfe25a4.html"><code>usb_selftest_ospi</code></a></td><td>Brings the board's onboard Octo-SPI flash (IS25LX512M at U16) up as a USB drive and verifies it against itself on-chip -- no PC in the loop. The two USB ports are cabled to each other and one image ...</td></tr> <tr><td><a href="dir_e99f4dc5119b70b2b1f1652f6a7016ed.html"><code>usb_selftest_ospi_rw</code></a></td><td>The non-volatile write-path member of the USB self-loop matrix: it exercises the host-to-device bulk-OUT data phase (SCSI WRITE(10)) landing on the onboard OSPI flash. The two USB ports are cabled to ...</td></tr> <tr><td><a href="dir_1a8b95282c40c3480d858da3cc1f4977.html"><code>usb_selftest_soak</code></a></td><td>The endurance and benchmark member of the USB self-loop matrix. Same dual-stack image as usb_selftest_hs_host -- HS host on J7, FS MSC device on J11, the loop cable between them, no PC involved -- ...</td></tr> <tr><td><a href="dir_33d0a823b57aa76855ae3532a27ba524.html"><code>watchdog_demo</code></a></td><td>Round-trips the IWDT and the reset-cause machinery: log the latched cause on boot (power-on, IWDT, or other), refresh the IWDT for half a minute with LED1 toggling per refresh, then deliberately stop ...</td></tr> <tr><td><a href="dir_054b7a28c40bc1e8784fd0fc63f24ed8.html"><code>wdt_reset_recovery_demo</code></a></td><td>The WWDT (WDT0) half of the watchdog reset story, companion to watchdog_demo, which covers the IWDT.</td></tr> <tr><td><a href="dir_f96023e914d8e405e2874e856c3c2eb9.html"><code>wdt_supervisor_demo</code></a></td><td>Exercises libs/ra8_wdt_supervisor end to end on the bench: the WWDT is refreshed only when every registered worker thread has called ra8_wdt_supervisor_checkin inside its own deadline. Two synthetic ...</td></tr> <tr><td><a href="dir_a6dfded2458d6552e203e672ca794433.html"><code>wdt_window_demo</code></a></td><td>Drives the WWDT in window mode: poll the down-counter and write the refresh sequence only while it sits inside the legal window, which here is the middle half of the period. LED1 toggles on each ...</td></tr> <tr><td><a href="dir_7c84ce03177d7d2cdb485c1b9dc1197d.html"><code>widget_app</code></a></td><td>Headless gate proving the ra8_widget compositor (#145) and the ra8_app framework (#146) work end to end on the M85.</td></tr> <tr><td><a href="dir_966d27339ffe87542612516bc60803be.html"><code>widget_app_demo</code></a></td><td>The panel-visible counterpart to widget_app: where that one CRC-gates an off-screen framebuffer headlessly, this brings the GLCDC panel up so the composition is actually shown, and drives it from the ...</td></tr> <tr><td><a href="dir_c39fc71005c861fd805d9795d5cdcb99.html"><code>widget_chrome_demo</code></a></td><td>The concrete ereader chrome widgets -- extracted into the ra8_widget library for issue #145 -- composited on the live GLCDC panel. Where widget_compose_demo proves the ra8_widget_panel compositor ...</td></tr> <tr><td><a href="dir_6f495ddfff9d83dd16769e49242434a8.html"><code>widget_compose_demo</code></a></td><td>A nested ra8_widget tree composited on the live GLCDC panel. Where widget_app_demo shows the full ra8_widget + ra8_app launcher, this app isolates the structural piece issue #145 added: a container ...</td></tr> <tr><td><a href="dir_11980bbb22e11acdb0546fac990a36a3.html">`widget_kit_demo`	Concrete ra8_widget leaf widgets – a text label and a push button – composited through the ra8_widget_panel compositor on the live GLCDC panel. Where widget_compose_demo proved the panel compositor ...